Abstract: A demodulation apparatus of the present invention comprises: an A/D converter for sampling and quantizing a baseband signal; a transversal filter having time-shifted tap coefficients; a decision unit for decoding the signal which has undergone the transversal filter; and a decision point estimation unit for instructing the transversal filter to select the tap coefficient to be selected based on information from the decision unit. Thus, the demodulation apparatus can operate at the same frequency as a sampling frequency of the A/D converter and can perform decision with accuracy equivalent to an arbitrary oversampling number.

Abstract: A demodulator demodulates a PSK communications signal using a synchronizer, a period window detector, and a logic device. The synchronizer provides a transition signal representing reference edges of the communication signal. The period window detector, coupled to the synchronizer, establishes a time interval based on the period of the transition signal. Finally, the logic device, having logic inputs coupled to the outputs of the period-window detector, yields a logic output signal. The demodulator preferably includes a carrier boundary detector for framing messages and minimizing noise detection in a manner that permits signal strength measurements over a wide dynamic range.

Abstract: A demodulator for demodulating a modulation signal (IF IN) which has been modulated by means of quadrature modulation includes a quasi-coherent detection section, a demodulation section, a signal error detector, a phase error detector, a quadrature error detector and a quadrature controller. The signal error detector detects signal errors (Ei, Eq) and polarities (Di, Dq) of signals (I-ch5, Q-ch5) demodulated by the demodulator. The phase error detector detects the phase error (Pd) of the demodulated signals (I-ch5, Q-ch5) based on the signal errors (Ei, Eq) and the polarities (Di, Dq). In the quadrature error detector, a quadrature error (Qd′) after phase rotation executed in the demodulation section is obtained by calculating Ei·Dq+Eq·Di, and thereafter a quadrature error (Qd) before the phase rotation is obtained by means of polarity switching based on the demodulated signals (I-ch5, Q-ch5) and a phase rotation angle signal (Ang) which is generated from the phase error (Pd).

Abstract: An FM demodulator circuit with reduced sensitivity to noise and performance nearly identical to theoretical predictions. The FM demodulator is a time sampled detector for binary shift key (BFSK) modulated signals. Its inputs are an in-phase and a quadrature outputs of a receiver, which have been oversampled by a predetermined factor with respect to the data rate. The demodulator circuit differentiates the in-phase and the quadrature input signal by computing the difference between the current signal value and the signal value delayed by one clock period. The differentiated values of the in-phase and the quadrature signals may be changed based on the sign of the quadrature and the in-phase signals respectively to produce modified values of the differentiated in-phase and quadrature signals.

Abstract: A device for transmitting digital data includes a selector which selects certain digital data couples which follow each other, a mapper, which, in accordance with a set of rules, maps each digital data couple selected to an amplitude couple, and a transmitter which transmits a signal in quadrature, the two components of such signal being modulated by the first and second amplitudes, respectively, of the amplitude couple. The set of mapping rules includes a rule that states that when the estimated probability that two amplitude couples will be confused, after the transmission has occurred, is greater than a certain value, then the digital data couples corresponding to the two amplitude couples have first or second digital data items whose value is the same.

Abstract: A receiver receives modulated message signals in non-coherent FSK and coherent 8PSK protocols. A selectively configurable processor demodulates the message signals, and includes a demodulator that derives in-phase and quadrature signals based on the message signals. A phase detector is responsive to the in-phase and quadrature signals and delayed in-phase and quadrature signals to derive a phase signal. A selector is responsive to the in-phase and quadrature signals to selectively connect a loop filter between the phase detector and the demodulator. When the selector connects the filter between the phase detector and demodulator, the demodulator is responsive to filtered phase signals to lock onto a frequency of the message signals so that the processor operates as a phase locked loop to demodulate coherent modulated signals.

Abstract: An N-VSB (vestigial sideband) modulation signal is converted into an M-QAM (quadrature amplitude modulation) signal, where M=N2, by shifting the symbol rate frequency of a received N-VSB modulation signal to center the waveform spectrum about zero Hertz prior to complex demodulation so that data symbols will alternately appear on demodulated I and Q channels. A pilot tone of the received N-VSB modulation signal is removed to eliminate any bias in the both I and Q channels. Symbol timing between I and Q channels is offset, and quadrature amplitude demodulation of the I and Q channel signals generate alternating I and Q channel data symbols. Alternating inversion of the alternating I and Q channel data symbols recovers the N-VSB symbol data.

Abstract: A digital demodulator which demodulates information signals that have been phase-modulated using a method such as PSK (Phase Shift Keying). The adder 46 adds a compensation value held by the phase compensator 45 to phase difference data outputted from the comparator 43. The subtractor 47 subtracts phase difference data delayed by the delaying circuit 44 by one information symbol period from the sum of the phase difference data and the compensation value from the adder 46, thus performing delay detection. With this digital demodulator, an input signal can be received and demodulated even if its frequency is not an integral division of the frequency of a master clock signal, and an oscillator can be used even if its frequency is not an integral multiple of the frequency of an input signal to be demodulated.

Abstract: A method for simple synchronization of a receiving device to a transmitting device for a transmission of a dispersed-energy QPSK signal. The signal is composed at the transmitting end of two mixed products, the mixed product of an I signal and a transmitted carrier and the mixed product of a Q signal and the transmitted carrier shifted through 90°. In order to synchronize the received carrier to the transmitted carrier without any problems, it is proposed that an amplitude of an SQ signal be measured at the time of the zero crossing of the rising flank of an SI signal, and that an amplitude of the SI signal be measured at the time of the zero crossing of the falling flank of the SQ signal. The measured values are a measure of a discrepancy from synchronicity between the received carrier and the transmitted carrier, and that the frequency of the received carrier be varied until the amplitude of an error signal obtained from this measurement is zero.

Abstract: Disclosed is a quadrature amplitude modulation (QAM) receiver and a carrier recovery method which receive a signal modulated by the QAM method and recover the frequency offset and phase jitter of the carrier particularly using a weighted phase error inversely proportionate to the magnitude of the deciding signal character, as a result of which the phase jitter of the demodulated signal characters is constant in size irrespective of the magnitude of the deciding signal character. Consequently, acquisition/tracking can be rapidly achieved to minimize the frequency offset of several hundreds of KHz and the phase jitter generated from a tuner or an RF oscillator.

Abstract: A method of efficiently demodulating and isolating a signal within a fixed possibly wider band spectral region, having any of a wide range of baud rates. The signal is sampled at a fixed, first frequency which remains fixed no matter what the baud rate. Thus, the sample rate does not necessarily correspond to the desired baud rate. The sampled signal is then demodulated and low pass filtered to create baseband samples at the first frequency, which are then subject to user-specified arbitrary rate change in a continuously variable interpolator/decimator (continuously variable digital delay (CVDD) device), and decimated by a programmable power of 2, to produce samples at a second frequency. The second frequency is preferably determined to be a whole number multiple of the desired baud rate, e.g., twice the desired baud rate. The samples are equalized to produce output symbols at the target baud rate.

Abstract: A quadrature amplitude modulation type demodulator having a dual bit error rate estimator unit that allows for high bit error rate measurements. The dual bit error rate estimator circuit uses information pertaining to the number of corrected bytes from a forward error correction decoder and the count of recognizable patterns of the frame over a sufficiently large number of frames. The two pieces of information can be compared at the bit error rate levels, where both the pattern recognition counter and the FEC decoder are able to output valid data. A comparison between the two pieces of information provides a way to detect the type of noise which occurs on the network and makes it easier to correct problems in signal transmission.

Abstract: A demodulator for automatically performing quadrature control in which there is no necessity for the modulator side to perform precision adjustment and deterioration in characteristics e.g., error rate is suppressed for long.

Abstract: A method of timing recovery convergence monitoring in modems using an average phase error signal. The method involves continuously tracking the peak of the average phase error. The average phase error is compared to a dynamic threshold (i.e. a threshold that can change over time based on changes to the detected peak at a given time). Convergence is declared when the average phase error remains less than the threshold over a given length of time (i.e. after processing a prescribed number of consecutive samples).

Abstract: A digitized quadrature detected output of a sampling rate R (=16Rs, where Rs is the symbol rate) from a quadrature detector is subjected to FFT processing and the frequency of the peak power spectrum of the FFT output is detected. Then, a frequency error &OHgr;01 between the frequency of the peak power spectrum and a standardized value is calculated and the frequency error &OHgr;01 of the detected output is corrected. The corrected output is decimated by a filter to a signal of a sampling rate 4Rs, which is input into an estimate part, wherein a clock phase is calculated which minimizes variance of the amplitude of the input sample data and a frequency error &OHgr;02 is computed from a deviation of the signal point of the input sample data from a standardized angle value of the signal.

Abstract: A method of estimating the DC offset and the phase offset for a radio receiver operable in a digital passband transmission system, the method comprising; sampling a received radio signal at the symbol rate of the transmission system to produce a set of data samples, processing each data sample in the set in order to determine a received signal point in signal space for each data sample, determining an associated constellation point in signal space for each received signal point, calculating the DC offset and the phase offset which minimises, for the set of data samples, the sum of the square of the random errors between each received signal point and its associated constellation point.

Abstract: The invention is a demodulator (50, 100) and a method of data reception and testing of a demodulator. A demodulator in accordance with the invention includes an input signal source (52, 102) having an output which during data reception is a data signal and which during testing of the demodulator is a reference signal; a tuner (54, 101) having a tuner input coupled to the output of the input signal source and a tuner output, the tuner including a frequency converter (20, 36) which frequency shifts the data signal to a lower carrier frequency during data reception to cause the tuner to output at the tuner output the lower carrier frequency modulated with the data signal and which upwardly frequency shifts the reference signal to a test carrier frequency during the testing; and a test data source (56, 105) which applies a test data signal to the tuner during the testing to cause the tuner to output at the tuner output the test carrier frequency modulated with the test data signal.

Abstract: Received signals are digitized by a comparator, and sampled by regenerated clock signals synchronized to a carrier. Biphase symbol data are demodulated based on the sampling data. A biphase decoder circuit performs subtraction of the biphase symbol data to be paired. The subtraction result is compared with threshold values by data judgment circuitry which then judges inversion of the biphase signals to be paired. An RDS-ID detector circuit detects inversion of RDS signals by detection of either continuity or a ratio of signals received for a certain length period. Alternatively, RDS signals are detected by stability of output from the pair judgment circuit to detect a combination of biphase symbols.

Abstract: At the transmitter side, carrier waves are modulated according to an input signal for producing relevant signal points in a signal space diagram. The input signal is divided into, two, first and second, data streams. The signal points are divided into signal point groups to which data of the first data stream are assigned. Also, data of the second data stream are assigned to the signal points of each signal point group. A difference in the transmission error rate between first and second data streams is developed by shifting the signal points to other positions in the space diagram. At the receiver side, the first and/or second data streams can be reconstructed from a received signal. In TV broadcast service, a TV signal is divided by a transmitter into, low and high, frequency band components which are designated as a first and a second data stream respectively.

Abstract: A method for demodulating a modulated carrier includes sampling the modulated carrier with an A/D converter clocking at a first sampling frequency to generate a modulated carrier series of samples occurring at the first sampling frequency. The first sampling frequency it selected to optimize a digital signal processor (DSP) design from demodulating a carrier modulated in accordance with a first transmission specification to recover base band data. The method includes generating a second series of samples occurring at a second sampling frequency representing the base band data. The second series of samples is calculated from the first series of samples and the second sampling frequency is selected to optimal a DSP design for recovering data from the base band data signal encoded in accordance with a second transmission specification.

Abstract: A quadrature amplitude modulation (QAM) type demodulator having a pair of direct digital synthesizer (DDS) circuits. The first DDS circuit is located in a baseband conversion circuit before a receive filter and digitally tunes the signal within the receive filter bandwidth. The second DDS circuit is within a carrier recovery circuit located after the receive filter and serves to fine tune the signal phase.

Abstract: A QAM demodulator having a carrier recovery circuit that includes a phase estimation circuit and an additive noise estimation circuit which produces an estimation of the residual phase noise and additive noise viewed by the QAM demodulator. The phase noise estimation is based on the least mean square error between the QAM symbol decided by a symbol decision circuit and the received QAM symbol. The additive noise estimation is based on the same error as in the phase noise estimation, except that it is based only on QAM symbols having the minimum amplitude on the I and Q coordinates. The additive noise estimation is not dependent on the phase of the signal, thus, is independent of the phase noise estimator.

Abstract: In order to differentially detect a multiple-phase shift keying (MPSK) signal, a predetermined number of phase signals are stored at successive symbol time points. Next, a plurality of phase differences between the phase signals stored in the above are calculated. Subsequently, a symbol value of the MPSK signal is determined or estimated at a current symbol time point using the calculated phase differences and using symbol values already determined at a plurality of preceding symbol time points.

Abstract: An absolute phasing circuit having a simplified phase rotating means constituting a remapper. The phase rotation angle of a receiving phase for the signal point arrangement on the transmitting side is detected, and a phase rotation signal RT (3) based on the detected phase rotation angle is outputted from a frame synchronization circuit (2). Phases of baseband demodulated signals I and Q through a demodulator circuit (1) are rotated by 45° through a ROM (3) constituting the remapper. A logic conversion circuit (4), receiving the baseband demodulated signals I and Q through the demodulator circuit (1) and phase rotated baseband demodulated signals i and q from the ROM (3), performs inversion of code and exchange of the baseband demodulated signals selectively and delivers a baseband demodulated signal matched with the signal point arrangement on the transmitting side.

Abstract: A quadrature modulator and demodulator which provide the requisite level of performance while minimizing power consumption. In the quadrature modulator, the I and Q signals are provided to two pairs of mixers. Each mixer in a pair of mixers modulates an I or Q signal with the respective inphase or quadrature IF sinusoid. The I and Q modulated signals from each pair of mixers are summed. The signals from the summers are provided to a third pair of mixer and modulated with the respective inphase and quadrature RF sinusoids. The signals from the third pair of mixers are summed and provided as the modulated signal. Using this quadrature modulator topology, the amplitude balance and phase error of the modulated signal are made insensitive to the amplitude imbalance and/or phase error of the quadrature splitters used to generate the IF and RF sinusoids. Furthermore, since the first two pairs of mixers and the two subsequent summers are operated at IF frequency, the performance requirements (e.g.

Abstract: A direct-conversion receiver includes a local oscillator for generating a local oscillator signal, a converter circuit for converting a received radio signal into a pair of a baseband I signal and a baseband Q signal in response to the local oscillator signal, a demodulator for demodulating the pair of the baseband I signal and the baseband Q signal into a demodulation-resultant signal which is neither an I signal nor a Q signal, a detector circuit for detecting a difference between a frequency of the local oscillator signal and a frequency of a carrier of the received radio signal, a clock signal generator for generating a first clock signal providing a timing which corresponds to a center of a symbol period, a signal delay device for delaying the first clock signal to provide a second clock signal, and a symbol deciding circuit for deciding a logic state of the demodulation-resultant signal at a timing determined by the second clock signal.

Abstract: A demodulator with a cross polarization interference canceling function for canceling interference of cross polarization in the main polarization includes a demodulating unit for demodulating a baseband signal of the main polarization, a phase control unit which controls the phase of an interference signal, which is a baseband signal of cross polarization, based upon an error in the demodulated signal, and an interference cancellation unit which cancels an interference signal component from the demodulated signal of the main polarization.

Abstract: According to the invention, information from a differential decoder (1) receiving the MSB of the in-phase component and the MSB of the quadrature component is used to derotate the LSBs of the in-phase component and the LSBs of the quadrature component into the first quadrant with a rotator (2). Then only one quadrant is demapped by a single quadrant demapper (3). Thereby, the look-up table necessary for the demapping circuit is reduced considerably. The output signal of the QAM de-mapping circuit is build from the demapped LSBs of the in-phase and quadrature components output by the single quadrant demapper (3) and the outputs of the differential decoder (1).

Abstract: A method and apparatus for digitally demodulating QPSK signals includes a first portion in which the digitally sampled data burst is resampled with a plurality of predetermined timing hypotheses. The timing offset is determined according to an analysis of the resampled data. The digitally sampled data burst is then resampled according to the timing estimation. Modulation of the resampled data burst is then removed by twice squaring the complex I/Q pairs. The data with the modulation removed is then subjected to a Chirp-Z Transform to move the data into the frequency domain. The highest spectral power is used to determine the frequency offset. The phase offset is determined and the resampled data burst is derotated and dephased according to the phase offset and the frequency offset.

Abstract: The present invention relates to the use of complex non-linear elements in improvements to the recovery of a carrier phase reference from a modulated input signal where the modulation is in accordance with the M-PSK modulation format and where M has a value greater than 4 and the signal-to-noise ratio in the channel is low. A voltage-controlled oscillator is employed to generate first and second oscillations in phase quadrature with respect to each other. The modulated input signal is mixed with the first of the oscillations to detect the (I) signal component and the modulated input signal is mixed with the second of the oscillations to detect the (Q) signal component. A control signal is derived from the (I) and (Q) signal components as an estimate of the phase difference between the input signal carrier and the voltage-controlled oscillator.

Abstract: A circuit for demodulating a signal having a temporal mixture of different modulation schemes applied thereto includes a synchronization-word-detection unit which detects synchronization words included in the signal, and generates first and second position signals, based on the detected synchronization words, indicative of respective predetermined positions in the signal, a first selection unit which selects the first position signals during a first period, and selects the first position signals and the second position signals during a second period, and a carrier-reproduction unit which carries out frequency capturing during the first period by using the first position signals selected by the first selection unit, and carries out phase capturing during the second period by using the first position signals and the second position signals selected by the first selection unit, thereby reproducing a carrier.

Abstract: A digital demodulator which demodulates information signals that have been phase-modulated using a method such as PSK (Phase Shift Keying). The adder 46 adds a compensation value held by the phase compensator 45 to phase difference data outputted from the comparator 43. The subtractor 47 subtracts phase difference data delayed by the delaying circuit 44 by one information symbol period from the sum of the phase difference data and the compensation value from the adder 46, thus performing delay detection. With this digital demodulator, an input signal can be received and demodulated even if its frequency is not an integral division of the frequency of a master clock signal, and an oscillator can be used even if its frequency is not an integral multiple of the frequency of an input signal to be demodulated.

Abstract: The invention provides a block-encoded modulation scheme using multi-level partitioning techniques. This scheme is made transparent to phase ambiguities of ±&pgr;/2 and of &pgr;, by means of differential encoding and appropriate mapping, it is applicable to 16-QAM modulation, and it has theoretical encoding gain that is optimal for the rate of the code. The decoder associated with this scheme uses the Wagner algorithm which is much less complicated to implement than the Viterbi algorithm or than the Reed-Solomon algorithm.

Abstract: A quadrature demodulator detects a phase angle error determined from the phase angle supplied from constellation symbols of outgoing in-phase and quadrature components of a modulated signal and and the phase angle of a NCO. The quadrature demodulator comprises a receiving circuit for receiving a quadrature modulated signal, and a local oscillator for generating a local carrier. A complex multiplier demodulates the quadrature modulated signal by complex-multiplying the quadrature modulated signal with the local carrier generated in the local oscillator. A symbol error detector detects a symbol error between the carrier of the modulated signal and the local carrier supplied from the signal demodulated at the complex-multiplier. A feedback loop controls the local carrier generated at the local oscillator by feeding back the symbol error detected at the symbol error detector to the local oscillator.

Abstract: An apparatus estimates the frequency difference existing between the carrier frequency of a received digital signal and the frequency of a signal from a local oscillator contained in a receiver of the received signal. The receiver performs quadrature demodulation on the received signal. The apparatus includes a detector that detects the noise level received in the band of the receive filters, a processor for computing discrete Fourier transforms on the received signal transposed into baseband, a summer for summing the energy levels detected on either side of the center frequency of the receive filters, a subtractor for subtracting the noise level from the energy bands, and a comparator for comparing the resultant energy levels and delivering an estimate &egr; of the frequency difference.

Abstract: A method to demodulate BPSK or QPSK data using clock rates for the receiver demodulator of one-fourth the data rate. This is accomplished through multirate digital signal processing techniques. The data is sampled with an analog-to-digital converter and then converted from a serial data stream to a parallel data stream. This signal processing requires a clock cycle four times the data rate. Once converted into a parallel data stream, the demodulation operations including complex baseband mixing, lowpass filtering, detection filtering, symbol-timing recovery, and carrier recovery are all accomplished at a rate one-fourth the data rate. The clock cycle required is one-sixteenth that required by a traditional serial receiver based on straight convolution. The high rate data demodulator will demodulate BPSK, QPSK, UQPSK, and DQPSK with data rates ranging from 10 Mega-symbols to more than 300 Mega-symbols per second. This method requires less clock cycles per symbol tan traditional serial convolution techniques.

Abstract: A digital demodulator which demodulates information signals that have been phase-modulated using a method such as PSK (Phase Shift Keying). The adder 46 adds a compensation value held by the phase compensator 45 to phase difference data outputted from the comparator 43. The subtractor 47 subtracts phase difference data delayed by the delaying circuit 44 by one information symbol period from the sum of the phase difference data and the compensation value from the adder 46, thus performing delay detection. With this digital demodulator, an input signal can be received and demodulated even if its frequency is not an integral division of the frequency of a master clock signal, and an oscillator can be used even if its frequency is not an integral multiple of the frequency of an input signal to be demodulated.

Abstract: A phase shift keyed carrier recovery and demodulator circuit which includes a phase detector and subsequent feedback control loop circuitry which maintains an initial phase relationship. By comparing an incoming phase modulated carrier with the multiple phase outputs of a local oscillator, the circuit is able to generate a correcting signal which allows coherent phase tracking of the incoming phase modulated carrier. The phase detector produces a correction signal which allows the circuit to phase lock any two sequential phases of the locally generated phase outputs to phase positions on either side of the phase of the incoming phase modulated carrier. Once the circuit has obtained carrier phase lock, the multiple phases produced by the local oscillator will remain fixed (without phase change) relative to the initial detected phase of the incoming phase modulated carrier.

Abstract: A QAM demodulator having a first automatic gain control circuit which outputs a first signal that is a function of the received signal, the first signal being used to control the gain of an amplifier which supplies the input of an A/D converter, and a second automatic gain controller which outputs a second signal derived from the QAM circuit after filtering, the second signal controlling the gain of a digital multiplier which produces a signal which feeds into a equalizer by way of a receive filter. The dual automatic gain control circuits, situated before and after the receive filters, allow for better resistance to non-linearity caused by signals in adjacent channels. Additionally, the dual automatic gain control circuits allow for the amplification level of the signal to be limited before the demodulator to eliminate signal distortion and to be set to the correct level internally with digital gain. Also, there is no saturation of the A/D converter since there is no QAM feedback to analog circuits.

Abstract: A digital communication method and system wherein in response to input 3-bit data, a phase and amplitude of a carrier signal are controlled so that a symbol at a given time is located at one of allowed signal points depending on the content of the symbol. The allowed signal points include six signal points where a phase shift equal to .+-..pi./4, .+-.2.pi./4, or .+-.3.pi./4 occurs relative to the signal point at which the immediately previous symbol was located and where the amplitude is equal to a first level, and also include two signal points where a phase shift equal to .+-.2.pi./4 occurs relative to the signal point at which the immediately previous symbol was located and where the amplitude is equal to a second level lower than the first level. The digital communication method and system allows for a transmitter which does require a high-performance power amplifier, and a simplified receiver circuit.

Abstract: The present invention relates to methods and devices for such control and supervision of an oscillator signal from a controllable oscillator that is done mainly to control the frequency variation of the oscillator signal. According to the invention, the controllable oscillator is controlled by a controlling voltage, which in turn is modified by a correction signal, generated in a control loop. A time discrete representation of a secondary phase is generated in the control loop, the secondary phase corresponding to a frequency being the difference between the frequency of the oscillator signal and a constant frequency. A time discrete approximation signal is generated in dependence of the time discrete representation of the secondary phase. A time discrete error signal is generated in dependence of the time discrete approximation signal, the time discrete error signal indicating the difference between the actual frequency slope of the oscillator signal and a desired frequency slope.

Abstract: A system and method for the transmission of additional special marker symbols in a circular signal space constellation allows the communication of additional control information without requiring any additional power to transmit the additional symbol. Additional symbols can include "Start of Message", "End of File", "End of Transmission", "Increase Data Rate", "Decrease Data Rate", "Save State" or "Clear", or any additional command signal desired to be transmitted.

Abstract: A receiver includes a demodulator and a false carrier lock detector circuit for a quadrature amplitude modulated (QAM) signal. The demodulator includes a controllable oscillator and an offset frequency generator for generating an offset frequency for the controllable oscillator to lock to a carrier of the QAM signal. The demodulator is susceptible to false carrier locking responsive to the offset frequency being substantially equal to the symbol rate divided by four or an integer multiple thereof. The receiver further includes the false carrier lock detector circuit including a first detector for detecting consecutive symbols spaced 180.degree. apart, and a second detector for determining whether an intervening sample between the consecutive symbols is outside a predetermined distance from the origin. The first and second detectors cooperate to determine false carrier locking based upon the intervening sample being outside a predetermined distance from the origin.

Abstract: In a communication system for communicating on at least one channel group, a demodulator is disclosed. The channel group has at least one forward channel and at least one return channel, where a central station transmits data over the forward channel to a plurality of terminals at a forward data rate, and transmissions by each terminal to the central station are performed on any one of the return channels at a return data rate. The demodulator comprises a burst demodulator that demodulates received, discrete signaling packets of information over the return channels. The demodulator also comprises a message demodulator that is responsively connected to the burst demodulator, such that when the message demodulator is activated, the burst demodulator becomes deactivated when the return channel operates in a messaging mode. Thus, a feature of the demodulator is that it is a dual function demodulator that functions either as a burst demodulator, or as a continuous or message demodulator.

Abstract: In a digital demodulator for phase modulated signals, logical values of a waveform-shaped phase-modulated signal are sampled based on a clock signal having a period that stands in integer ratio relationship to a carrier period of the modulated signal and thereafter subjected to serial/parallel conversion for each predetermined interval, whereby a logical pattern of a digital code train subjected to the serial/parallel conversion is analyzed. As a result, phase information required to demodulate digital data can be logically detected.

Abstract: Circuits embodying the invention include a baseband amplifier to whose input is applied a baseband input signal (I or Q). The gain of the amplifier is controlled by sampling the output of the amplifier and supplying the sampled signals to a dynamic histogram control (DHC) circuit which includes a memory circuit for storing a histogram which contains a statistically expected response of the sampled baseband signal. The DHC circuit includes circuitry for comparing the sampled signals to the stored histogram for producing a gain control signal which is then used to control the gain of the amplifier. In some embodiments, the DHC circuit may also include circuitry for producing an offset adjustment signal to control the direct current (dc) level of the signal being sampled and hence its symmetry.

Abstract: A differentiate and multiply based timing recovery in a quadrature demodulator. A quadrature-modulated signal is received and demodulated by quadrature mixing the received modulated signal with a local oscillator signal. In-phase and quadrature down-converted signals are sampled. The sampled signals are differentially detected to produce binary digits from symbols conveyed by the quadrature-modulated signal. Sampling is controlled by a symbol timing recovery signal derived from the in-phase and quadrature down-converted signal. Thereto, the respective in-phase and quadrature down-converted signals are differentiated with respect to time, the respective differentiated signals are multiplied by the quadrature and in-phase signals, respectively, and the multiplied signals are subtracted from each other so as to produce a difference signal. The difference signal controls the symbol timing recovery in that a clock signal controlling the timing of the sampling is locked to the difference signal.

Abstract: In a clock recovery circuit in a demodulator of a multi-level quadrature amplitude modulation (QAM) system, an analog/digital (A/D) converter performs an A/D conversion upon an analog baseband signal in synchronization with a sampling clock signal having a time period that is a symbol time period. A phase detector receives successive first and third data sampled from the A/D converter, calculates second data by addition of the first and third data, determines whether or not a signal transition formed by the first and third data crosses a zero value within a predetermined deviation, and compares a polarity of the second data with a polarity of one of the first and third data, and generates a comparison result as a phase detection signal when the signal transition crosses the zero value. A loop filter passes a low-frequency component of the phase detection signal therethrough.

Abstract: It is an object of the invention to provide a demodulator, which improves a BER characteristic in a ordinary state, reduce a time constant of a AGC amplifier, and quickly follows the fluctuation of an input signal level. A demodulator for 2.sup.q -QAM system is composed of an AGC amplifier, which keeps an average power of its output signal constant, A/D convectors for A/D converting the output signal of the AGC amplifier, an equalizer for removing interference components between codes contained in output signals of the A/D convectors, AGC circuits, which operate so that convergent points of output signals of the equalizer have amplitudes expressed by binary numbers composed of q/2 bits, and a control circuit, which is supplied with output signals of the AGC circuits and generates control signals for the AGC circuits.

Abstract: Disclosed is a delay detection demodulation system which has: a plurality of receiving systems; a plurality of instantaneous phase detecting circuits for detecting an instantaneous phase from the output of each of the plurality of receiving systems; a plurality of phase difference operating circuits for determining a phase difference in one symbol section from the output of each of the plurality of instantaneous phase detecting circuits; a combining circuit for combining the outputs of the plurality of operating circuits; a delay detection circuit for conducting error diffusion type delay detection after the combining of the combining circuit; and a demodulation logical circuit for conducting demodulation logical operation.