Abstract: A demodulation circuit can perform a capturing operation although a frequency error is large. A phase comparator out puts a predetermined value other than 0 as a determination result of a phase error when a phase error of a carrier wave is large and a signal point is located at a predetermined position. A loop filter outputs a negative minimum value to an integrator when an integrated value of a determination result reaches a positive maximum value of a limiter. Thus, when a phase error is large, a value changing from a negative minimum value to a positive maximum value is output from the loop filter, thereby realizing a broad synchronous capture range.

Abstract: Method and device for modulating a signal comprising data symbols and reference symbols, characterized in that it comprises at least one step (3) wherein semi-pilot symbols are introduced that transport less information than the symbols customarily used but enough to obtain decisions decided during a decoding step (9), the semi-pilot symbols being disposed between the data symbols and the reference symbols.

Abstract: In one embodiment, a receiver of the invention has a detector coupled to a digital processor. The detector is adapted to mix the received PSK signal with a local oscillator (LO) signal having a time-varying phase offset with respect to the carrier frequency of the PSK signal to produce a digital measure of the PSK signal.

Abstract: The invention relates to a device for demodulating an input signal containing information being conveyed by phase modulation of a carrier wave. A transmitter generates a signal controlling a phase variation in the carrier wave, for each symbol having N cycles, N being an integer strictly greater than 1. The phase variation stretches on the receiver side over n cycles, n being an integer greater than 1 and less than N. The device generates a single pulse for each symbol received suited to generate the leading edge of the pulse corresponding to the symbol considered after a constant duration from the moment the symbol considered starts; and generates the trailing edge of the pulse considered at a moment the phase shift corresponding to the symbol considered has to be measured. Conversion means generate an output signal with a voltage varying as a function of the duration of the pulse produced.

Abstract: A radio receiver comprising: an antenna for receiving a radio frequency signal amplitude modulated with an audio frequency signal; a digitizer for periodically sampling the radio frequency signal and generating a digital reception signal representative of the amplitude of the radio frequency signal; and a demodulator for demodulating the digital reception signal to generate a representation of the audio frequency signal.

Abstract: An apparatus, method and computer program for correcting a common phase error (CPE) of symbols of a received OFDM signal is described, in which FFT processing may be performed on a time domain OFDM to transform the received signal to a signal in the frequency-domain. Reordered output values resulting from the FFT processing and locations of the reordered output values may be stored. One or more of the stored reordered output values for a current symbol of the OFDM signal may be transferred based on receipt of an address, and each of the transferred reordered output values may be multiplied by a corresponding reordered output value of a previous OFDM signal symbol, so as to determine phase differences between the reordered output values of the current and previous OFDM signal symbols. The CPE of the transformed OFDM signal may be corrected based on the detected phase differences.

Abstract: The present invention relates to a multiple differential demodulator using a weighting value. The multiple differential demodulator according to the present invention includes a weighting value generator for integrating a real part and an imaginary part of a value acquired by multiplying one of a plurality of differentiated reception signals by a conjugated value of a differentiated PN code signal corresponding to a preset symbol, and determining the greater of the integrated real and integrated imaginary parts to apply a predetermined weighting value to the greater value, where the PN code signal is differentiated in the same fashion as the differentiated reception signals.

Abstract: A quadrature demodulator includes a reception section which receives a signal transmitted by an RFID tag and containing a specific pattern and data following the specific pattern and multiplies the reception signal by a local signal to generate an I-signal, while multiplying the reception signal by the local signal shifted in phase by 90 degrees to generate a Q-signal, a first demodulating circuit which squares the I- and Q-signals and adding the resulting I- and Q-signals together to generate data on the basis of the addition result, a second demodulating circuit which detects the specific pattern in the I- and Q-signals to decode the data following one of the detected specific patterns, and a control section which selects one of the first and second demodulating circuits in accordance with a gain determined by the result of the addition between the values of the squared I- and Q-signals.

Abstract: An apparatus and method for use by a receiver in decoding information sent by phase-shift keying over a carrier frequency for use with power line carrier (PLC) applications as it is adapted to appropriately position the sampling window based on a zero crossing of one of the phases of the power line. The method allows for receipt and processing of information on more than one carrier frequency and from transmitters operating on a phase of the power line that is different than the phase used by alternating current at the power grid frequency on the receiver to detect the zero crossings of the power line. Optionally, a threshold parameter may be dynamically adjusted in reaction to the underlying level of noise so as to reduce the number of bursts carrying actual data that are discarded as having only noise. A number of alternative embodiments are included.

Abstract: A phase detector, including a sampling device, a comparing device, and an output device, is provided. The sampling device samples a data signal according to a plurality of clock signals, so as to provide a plurality of corresponding sampling values. The clock signals have the same frequency and different phases. The comparing device is coupled to the sampling device, and provides a plurality of corresponding comparison values according to comparison results of each of the sampling values comparing with the next sampling value. The output device is coupled to the comparing device, and outputs two of the comparison values in response to edges of the clock signals. The two outputted comparison values serve as a first instruction signal and a second instruction signal respectively. The first and the second instruction signals are referred to in controlling the frequency and the phase of the foregoing clock signals.

Abstract: A method of generating a phase value representative of a phase of a complex signal that includes an in-phase component and a quadrature-phase component includes determining a first sign for a first value and a second sign for a second value based on a quadrant occupied by the complex signal. The in-phase component is multiplied by the first value with the first sign, thereby generating a first multiplication result. The quadrature-phase component is multiplied by the second value with the second sign, thereby generating a second multiplication result. The first multiplication result, the second multiplication result, and a bias value are added, thereby generating the phase value for the complex signal.

Abstract: A demodulator and demodulation method includes a bit/symbol hard demodulator configured to obtain hard bit or symbol information from a received signal. At least one lookup table is configured to reference coefficients for computation of log-likelihood ratios (LLRs) from the hard bit or symbol information. A log-likelihood ratio calculation module is configured to compute bit-level LLRs from the coefficients and the received signal.

Abstract: A modulation system includes a modulator configured to employ a modulation mechanism on data. The mechanism includes a signal constellation configured to map sub-carriers which include a signal to be modulated. The signal constellation has a plurality of points asymmetrically disposed on a circle about an origin and a point at the origin wherein a number of sub-carriers becomes variable over different symbol intervals. Corresponding demodulators and corresponding methods are also disclosed.

Abstract: A receiving circuit and method for receiving an amplitude shift keying signal is provided. At least one exponent signal, an exponent-removed in-phase signal, and an exponent-removed quadrature-phase signal are generated from an in-phase input signal and a quadrature-phase input signal. An amplitude is determined as a sum of several summands, whereby the summands are determined from the exponent signal and/or from the exponent-removed in-phase signal and/or from the exponent-removed quadrature-phase signal (Q?), and wherein the amplitude (A) is demodulated.

Abstract: A system and method of switching from a first receiver receiving a constant bit rate signal to a second receiver receiving the constant bit rate signal, where the constant bit rate signal received by the first and second receivers is converted to a first baseband signal and a second baseband signal comprising estimating a signal quality metric of the first baseband signal, comparing the signal quality metric to a predetermined threshold, and switching from the first baseband signal to the second baseband signal if the signal quality metric is greater than the threshold.

Abstract: Compensating for wideband quadrature imbalance error by introducing inverse complex inputs to phase quadrature estimator filters to generate estimated quadrature distortion; summing estimator quadrature distortion with a delayed version of the actual complex input to obtain estimated quadrature output; comparing the output with the true output to obtain residual quadrature imbalance error; applying a least mean square to the inverse input and imbalance residual error to obtain an updated estimate of filter coefficients; updating the filter coefficients of the phase quadrature estimator; and updating the filter coefficients of a phase quadrature compensator with the filter coefficients of the phase quadrature estimator to obtain a quadrature output pre-compensated for quadrature imbalance error.

Abstract: A BPSK type reception device that includes a decoder for decoding a digital input signal, first and second comparators for delivering a decoded data signal and a data capture clock signal also includes a clock generator for generating a replacement clock signal, first and second latches controlled by the replacement clock signal to store the data taken, respectively, from the decoded data signal and from a signal that represents the sign of the signal at the output of the decoder, and a selection circuit for capturing, at each pulse edge of a clock signal that is offset with respect to the replacement clock signal, either the stored data originating in the sign signal in the case of loss of the previous data capture clock pulse edge at the output of the clock comparator, or the stored data originating in the data signal.

Abstract: A system for the coherent demodulation of Binary Phase Shift keying (BPSK) signal at a frequency f, includes recovering a carrier signal (C) at a frequency 2f from the BPSK signal; injecting the signal having a frequency 2f in an injection locking oscillator (ILO), which has a natural resonant frequency fr which is substantially equal to f, to provide differential output (Op, On) signals which recover the original carrier with a phase shift of (?e?k)/2, where ?e=arcsin ((fr?f)/(?Aif)) where ? and k are parameters that depend on the type of predominant non-linearity in the injection locking oscillator (ILO), and Ai is the amplitude of the recovered carrier signal at a frequency of 2f, and combining the differential output (Op, On) signals with a copy of the incoming BPSK signal to generate a demodulated signal (DEMOD).

Abstract: The present disclosure is directed to a system and method for directly sampling RF signals. In some implementations, an RF reader includes a clock generator and an Analog-to-Digital Converter (ADC). The clock generator is configured to generate a sample clock signal based, at least in part, on an input signal associated with transmitting RF signals. The ADC is configured to directly sample RF signals in a receive path of the reader using the sample clock signal to generate a digital signal. Mixing of the RF signal and the sample clock, through the sampling process in the ADC, reduces phase noise associated with the transmission signal in the receive path.

Abstract: Disclosed herein is a harmonic quadrature demodulation apparatus and method. The harmonic quadrature demodulation apparatus includes an input terminal for externally receiving an input focused signal, a harmonic phase estimation unit for estimating a second-order harmonic phase component from the input focused signal, and a harmonic detection unit for detecting a second-order harmonic component from the input focused signal. The second-order harmonic detection unit includes an in-phase component extractor, a quadrature component extractor, a Hilbert transformer, an adder and a low pass filter. The in-phase component extractor extracts an in-phase component of the input focused signal. The quadrature component extractor extracts a quadrature component of the input focused signal. The Hilbert transformer Hilbert-transforms a signal transmitted from the quadrature component extractor.

Abstract: A plurality of reference voltages are generated by a reference voltage generation circuit. A plurality of comparators is supplied respectively with an analog input voltage and any two reference voltages out of the plurality of reference voltages. A threshold voltage of each of the comparators is adjusted according to the two reference voltages. Each of the comparators compares the analog input voltage with the threshold voltage. A plurality of comparison output signals of the plurality of comparators are supplied to an encoder circuit, and digital signals which correspond to the plurality of comparison output signals are output.

Abstract: Carrier phase detector for calculation of a feedback signal (D) for a carrier phase loop in a receiver, which loop detects a phase error (??) between a phase (?in) of a received signal (Ein), which comprises a sequence of received data symbols, and a nominal phase (?nom) of a nominal data symbol (Enom), with the carrier phase detector in each case calculating the feedback signal (D) as a function of the real part and of the imaginary part of a received data symbol (Ein) , with a received data symbol (Ein) whose phase is in a boundary phase area being weighted gradually to a lesser extent during the calculation of the feedback signal (D), with the boundary phase area in each case being arranged symmetrically with respect to a mid-phase (?mid) which is located in the centre between the two nominal phases (?nom) of equidistant nominal data symbols (Enom), and having a phase extent which is determined by a boundary phase (?g).

Abstract: An apparatus and method for use by a receiver in decoding information sent by phase-shift keying over a carrier frequency is disclosed. The method is well suited for use with power line carrier (PLC) applications as it is adapted to appropriately position the sampling window based on a zero crossing of one of the phases of the power line. The method allows for receipt and processing of information on more than one carrier frequency and from transmitters operating on a phase of the power line that is different than the phase used by the receiver to detect the zero crossings of the alternating current at the power grid frequency on the power line. A number of alternative embodiments are included.

Abstract: A method and apparatus for the demodulation, filtering, decimation and optional voltage multiplication of modulated signals to produce in-phase and quadrature outputs using a discrete time architecture.

Abstract: The present invention provides for making code rate adjustments and modulation type adjustments in a pseudonoise (PN) encoded CDMA system. Coding rate adjustments may be made by changing the number of information bits per symbol, or Forward Error Code (FEC) coding rate. A forward error correction (FEC) block size is maintained at a constant amount. Therefore, as the number of information bits per symbol are increased, an integer multiple of bits per epoch is always maintained. The scheme permits for a greater flexibility and selection of effective data rates providing information bit rates ranging from, for example, approximately 50 kilobits per second to over 5 mega bits per second (Mbps) in one preferred embodiment.

Abstract: Synchrodyning apparatus in which a PAM IF signal is mixed with unmodulated carriers nominally at the frequency of the carrier, which unmodulated carriers are in quadrature with respect to each other. E.g., the PAM IF signal may be an intermediate-frequency 8VSB digital television signal. The baseband signals resulting from the mixing procedures are additively combined and differentially combined to generate real and imaginary components of a complex baseband signal. The real component of the complex baseband signal is processed for reproducing the digital signal used to modulate the transmitted RF carrier. An automatic frequency and phase control (AFPC) signal for controlling the oscillator circuitry generating the unmodulated carriers is generated by an AFPC detector responding to the imaginary component of the complex baseband signal or to both components of the complex baseband signal.

Abstract: When a first half of a transmission packet is sent by an FSK modulating signal, and a latter half thereof is sent by a PSK modulating signal, a received signal is converted into an intermediate frequency signal by a mixer. The converted intermediate frequency signal is switched to an FSK demodulation unit and a PSK demodulation unit by a received signal changeover switch. A frequency error detection circuit is provided in the FSK demodulation unit to detect a frequency error detection value. A demodulation circuit of a phase locked loop type of the PSK demodulation unit includes a loop filter. The frequency error detection value detected by the frequency error detection circuit is set as an initial value of this loop filter, whereby a time until lockup of a phase locked loop is reduced at the time when reception of a PSK modulating signal is started.

Abstract: In an OFDM receiver with a diversity configuration having a plurality of demodulation modules, to perform FFT window position recovery and clock recovery, the gain values calculated by the AGC units (16, 26) provided in the demodulation modules for adjusting the level of the received signal are supplied to a correlation combiner (35); the correlation combiner (35) multiplies the correlation signals supplied from the correlation detectors (17, 27) in the demodulation modules by coefficients calculated from the gain values, then adds the products to generate a combined correlation signal and supplies it to an FFT window position recovery unit (32) and a clock error detector (33). FFT window position recovery and clock recovery can thus be performed properly without depending on any one demodulation module.

Abstract: In a receiving section, a first mixer and a second mixer generate an I signal and a Q signal from a modulated reception signal, a local signal, and a local signal obtained by shifting a phase by 90 degrees. These I signal and Q signal are supplied to a digital signal processing section via a low path filter, a capacitor, a variable gain amplifier, and an ADC. In addition, the generated I signal and Q signal are directly supplied to the digital signal processing section. The digital signal processing section detects a sign of the I signal and a sign of the Q signal, the signals being directly input. In addition, the detected sign of the I signal is multiplied with the I signal input from the ADC, and then, the detected sign of the Q signal is multiplied with the Q signal input from the ADC, whereby the signs are commonly established in a positive state. Then, the I signal and the Q signal are added, and decoded into two-values.

Abstract: Methods and apparatuses employing symmetrical phase-shift keying (SPSK) for data modulation and demodulation. Each symbol in a transmission signal carries n-bit information and is transmitted with one of 2n+1 directions. Half directions among the 2n+1 directions are regarded as default directions and the remaining are regarded as complementary directions. Each default direction has a corresponding complementary direction with a phase difference of ? and representing the same n-bit information as the default direction. The phase difference between any two successive symbols after modulation is less than or equal to ?/2.

Abstract: Method and device for modulating a signal comprising data symbols and reference symbols, characterized in that it comprises at least one step (3) wherein semi-pilot symbols are introduced that transport less information than the symbols customarily used but enough to obtain decisions decided during a decoding step (9), the semi-pilot symbols being disposed between the data symbols and the reference symbols.

Abstract: A device and method for a symbol recovery in a digital television are disclosed. The device includes a symbol clock recovery device includes a remained phase error remover operating a digital baseband real/imaginary number component signals, and removing remained phase error, a timing error detector nonlinearly operating the real/imaginary number component signals having the remained phase error removed, and detecting symbol clock phase error information therefrom, and an oscillating part generating a symbol clock frequency compensated to at least two times from the detected symbol clock phase error information and outputting the compensated frequency.

Abstract: The exemplary demodulator of the present invention can eliminate effectively a phase fluctuation which cannot be fully eliminated by a carrier recovery loop (feedback loop), with subsequent feed-forward phase compensation loop which shares a phase detector of the carrier recovery loop. A carrier recovery loop receives a digital signal after a semi-synchronous detection, detects a phase shift of the digital signal to a predefined phase position in rectangular coordinate, and compensates for the phase of the received digital signal by a first compensation value on the basis of the detected phase shift to generate an output signal. A feed-forward phase compensation loop generates an average value of the phase shift, and compensates for the phase of the output signal by a second compensation value on the basis of the averaged phase shift value.

Abstract: In a timing component extractor for a digital modulated signal, a frequency converting section 30 receives a complex baseband signal having a symbol rate fs and formed from an I signal and a Q signal, and converts frequency components ±fs/2, which are present in the complex baseband signal as the data changes, to frequency components ±fs/4. The I signal and Q signal of the complex baseband signal are then nonlinearly processed. In other words, multipliers 31, 32 square the I signal and the Q signal, respectively, and an adder 33 adds the respective results of the multipliers 31, 32. A BPF 34 extracts the frequency components ±fs/2 from the output of the adder 33, and outputs the extracted frequency components ±fs/2 as a timing signal. Accordingly, processing can be conducted at a sampling frequency which is twice the symbol rate fs. Moreover, timing extraction can be stably conducted without being affected by a carrier frequency offset.

Abstract: Systems and methods for receiving layered modulation for digital signals are presented. An exemplary apparatus comprises a tuner for receiving a layered signal and producing a layered in-phase signal and a layered quadrature signal therefrom, an analog-to-digital converter for digitizing the layered in-phase signal and the layered quadrature signal and a processor for decoding the layered in-phase signal and the layered quadrature signal to produce one or more discrete layer signals.

Abstract: Systems and methods are disclosed for feeder link configurations to layered modulation. One feeder link system employs feeder link spot beam to antennas in distinct coverage areas to enable frequency reuse. Another system employs narrow beam width feeder link antenna to illuminate individual satellites also enabling frequency reuse. Yet another system uses layered modulation in the feeder link. Another feeder link system employs a higher order synchronous modulation for the satellite feeder link than is used in the layered modulation downlink signals.

Abstract: A method and pre-processor for processing a MCPM signal including a phase multiplier for multiplying a MCPM signal by a scaling factor. The pre-processor also includes a frequency shifter for shifting the scaled MCPM signal to create a frequency offset. The pre-processing allows a MDPSK demodulator to demodulate the received MCPM signal. This Abstract is provided to comply with rules requiring an Abstract that allows a searcher or other reader to quickly ascertain subject matter of the technical disclosure. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: A system for and method of converting successive bits of digital data into BPSK symbols using one or more BPSK symbol constellations such that orthogonal BPSK constellations are referenced to successive bits of the digital data. The system and method may toggle between referencing first and second orthogonal constellations as successive bits of the digital data are encountered. Alternatively, the system and method may successively rotate by 90° the constellation to be referenced as successive bits of the digital data are encountered. The reversal of the systems and methods described can be used to decode a transmission made by the methods described or specifically to reference a succession of orthogonal BPSK constellations to convert a succession of BPSK symbols to a succession of bits of digital data. Furthermore, a standard quadrature receiver can be used to perform the conversion.

Abstract: A cutoff rate may be used to determine an optimal binary input distribution for a communications system which operates with imperfect receiver channel state information (CSI) at the receiver. First, the cutoff rate may be evaluated and used to analyze the optimal binary input as a function of CSI quality and receiver Signal to Noise Ratio (SNR). Next, limiting distributions of BPSK and On-Off Keying (OOK) may be examined and an analytic design rule for adaptive modulation between these two inputs (as the receiver CSI changes) may be derived. The modulation scheme may provide near optimal performance by employing only these limiting distributions rather than the full spectrum of binary inputs. Finally, the results may be used to design an adaptive modulation scheme for Pilot Symbol Assisted Modulation (PSAM) systems.

Abstract: Embodiments of the present invention are directed to processing an incoming signal by using a demodulation signal, while controlling the phase of the demodulation signal in relation to the incoming signal. The incoming signal can be processed by being mixed with the modulation signal at a mixer. The mixing may thus cause various beneficial modifications of the incoming signal, such as noise suppression of the incoming signal, rectification of the incoming signal, demodulation of the incoming signal, etc.

Abstract: This invention provides a reception synchronization control device that controls reception synchronization of demodulated signals to be established, the demodulated signals being obtained by demodulating a phase modulated signal transmitted by a phase modulation, wherein the reception synchronization control device includes a signal level detector that detects signal levels of sampled demodulated signals extracted by sampling analog demodulated signals; a constellation position specifier that specifies constellation positions of plural kinds of data contained in the sampled demodulated signals displayed on a polar coordinates display based on the detected signal levels; and a phase angle difference calculation processor that calculates a difference between a phase angle calculated based on the specified constellation positions and a reference phase angle, thereby controlling the phase angle so that the difference is within a predetermined range.

Abstract: A demodulation method using phase detection and an apparatus thereof are provided. The demodulation method includes detecting phase information by sampling a received signal, synchronizing at least one clock signal by using the detected phase information, oversampling the received signal by the synchronized clock signal, and demodulating the received signal by using the oversampled result. With this, the demodulating apparatus can demodulate the modulated signal by using the phase detection, and use a digital filter as a filter for removing a jitter from the demodulated signal, thereby allowing a size thereof to be minimized.

Abstract: An algorithm for correcting the output of an analog I/Q demodulator without the need for calibration or storing state information. The output of the analog I/Q demodulator is digitized, and the discrete-time samples are divided into segments. A digital frequency transform (e.g., a Discrete Fourier Transform) is computed for each segment. The effects of the non-ideal I/Q demodulator are removed by identifying a set of image frequency candidates for each digital frequency transform, and for each image frequency candidate, estimating a set of demodulator imbalance parameters to characterize the demodulator imbalance at that frequency and correcting the digital frequency transform at the image frequency candidate using the imbalance parameters in order to minimize the effects of the imbalance. Each digital frequency transform is corrected independently and consequently no persistent state information needs to be saved between transforms.

Abstract: The invention provides a semiconductor device that generates a clock signal with a fixed pulse width from a carrier. The invention also provides a semiconductor device where data can be obtained accurately from a carrier using a clock signal with a fixed pulse width. Further, the invention provides a semiconductor device that has a simpler circuit configuration and a smaller scale, and consumes less power as compared to the PLL circuit. According to the invention, a signal obtained by dividing a carrier including 100% modulation is not used as a clock signal, and a correction circuit is used to generate a clock signal using a demodulated signal and a signal obtained by dividing the carrier including 100% modulation. According to the invention having such a configuration, a clock signal with a fixed pulse width can be generated.

Abstract: An apparatus for demodulating an analogue input signal comprises a hard limiter stage (4) for converting the signal to a two level signal, A digital down converter/low pass filter stage (6) converts the signal to a base band signal, and a symbol synchronization stage (8) extracts symbol timing. An instantaneous phase detector (10) calculates the instantaneous phase of the one or more symbols associated with the input signal. If the input signal has been modulated according to a pi/4DQPSK, pi/2DBPSK, GMSK, or a GFSK modulation scheme, a differential detector (12) determines a difference in the phase between adjacent symbols, a coarse frequency offset compensation stage (14) applies a compensation signal to compensate for frequency offset, and a frequency offset estimation stage (16) updates this compensation signal. A demapper (18) generates a demodulated output signal after compensation by the frequency offset compensation stage.

Abstract: A carrier frequency in a filtered received M-ary phase-shift keyed (MPSK) modulated signal having in-phase and quadrature components is detected by processing the filtered received signal to remove modulation components and thereby generate a test signal at the carrier frequency; processing the test signal to provide an amplitude spectrum of samples at different test frequencies; and processing the amplitude spectrum to detect the carrier frequency in accordance with the test frequency at which there is a test statistic of the highest magnitude. The magnitude of the test statistic is determined by processing a signal statistic in relation to a noise statistic. The signal statistic is the amplitude of the largest-amplitude sample. The filtered received signal is processed to provide approximate values of the modulus of the received signal and the phase of the received signal; and the approximate modulus and phase values are processed to generate the test signal.

Abstract: A demodulator with a phase-adjusting function including a detector including a delay detector delaying an input signal in delaying stages using a first clock obtained by frequency-dividing a sampling-clock at a first-ratio to output a delayed modulated signal, the sampling-clock having a predetermined frequency and a predetermined clock number, and a phase-adjustor which, when the stage number of the delaying stages obtained by dividing the predetermined clock number at the first-ratio does not become an integer, delays the input modulated signal using a second clock, the second clock obtained by frequency-dividing the sampling clock at a second-ratio, a ratio between the second-ratio and the first-ratio corresponding to a shortage in a final delaying stage to produce a phase-adjusted modulated signal that has been adjusted to cause the phase of the input modulated signal to coincide with the phase of the delayed modulated signal.

Abstract: A radio receiver with a low intermediate frequency has a first mixer stage that can be fed with a modulated input signal and at whose output a complex intermediate frequency signal can be derived. Connected downstream of the first mixer stage is a limiting amplifier at whose output the intermediate frequency signal is present in a discrete-value and continuous-time fashion. A sampling device, for sampling the intermediate frequency signal, and a digital demodulator unit are connected to the output of this limiter. The demodulated input signal can be derived at the output of this digital demodulator unit. The present radio receiver requires a low chip area in conjunction with low power consumption, but offers a high sensitivity and accuracy based on the digitally implemented demodulation.

Abstract: A fading rate of a mobile terminal unit is estimated by a fading rate estimation unit and an optimum step constant is decided by a step constant determiner depending on the estimated fading rate. This step constant is fed back to a feedback data calculator, so that a reception level can be converged to an ideal level even under a fading environment and the like.

Abstract: The present invention relates to a clock phase detecting circuit and a clock regenerating circuit each arranged in a receiving unit of multiplex radio equipment. The receiving unit of the multiplex radio equipment includes an identifying circuit for identifying a signal obtained by demodulating a multilevel orthogonal modulation signal; a clock regenerating circuit for regenerating a signal identification clock for the identifying circuit to supply the clock to the identifying circuit; an equalizing circuit for subjecting the signal obtained by demodulating a multilevel orthogonal modulation signal to an equalizing process. A clock phase detecting unit detects the phase component of the signal identification clock based on signals input to or output from the equalizing circuit and then supplies the phase component to the clock regenerating circuit.