Abstract: The present invention provides a method and system for estimating common amplitude and phase errors of a multiple channel wireless system. The multiple channel wireless system includes a plurality of transmission channels formed between a plurality of transmission antennas and a plurality of receiver antennas. The method includes estimating transmission channel elements between each transmission antenna and receiver antenna pair of the multiple channel wireless system. Calibration symbols are transmitted from each transmit antenna. Signals are received that correspond to the calibration symbols having traveled through the transmission channels. Received calibration symbols are estimated based upon spatial processing of the received signals and the estimated transmission channel elements. Common amplitude and phase errors are estimated for each transmit and receive antenna pair by comparing the transmitted calibration symbols with the received calibration symbols.

Abstract: A television receiver system capable of receiving and demodulating television signal information content that has been modulated and transmitted in accordance with a variety of modulation formats is disclosed. In particular, the system is able to accommodate receipt and demodulation of at least 8 and 16-VSB modulated signals in order to support US HDTV applications, as well as 64 and 256-QAM modulated signals, for European and potential US CATV implementations. The system includes carrier and timing recovery loops adapted to operate on an enhanced pilot signal as well as decision directed carrier phase recovery loops. Phase detectors operate on I and Q rail signals, or generate a Q rail from a Hilbert transform of the I rail. Decision directed loops incorporate a trellis decoder in order to operate on sequence estimated decisions for improved reliability in poor SNR environments.

Abstract: A vestigial sideband/quadrature amplitude modulation (VSB/QAM) receiver, which receives both VSB and QAM signals and restores a carrier wave with a restored symbol clock after restoring a symbol timing in a front portion of a carrier wave restoration unit.

Abstract: Disclosed is a quadrature amplitude modulation (QAM) receiver and a carrier recovery method which receive a signal modulated by the QAM method and recover the frequency offset and phase jitter of the carrier particularly using a weighted phase error inversely proportionate to the magnitude of the deciding signal character, as a result of which the phase jitter of the demodulated signal characters is constant in size irrespective of the magnitude of the deciding signal character. Consequently, acquisition/tracking can be rapidly achieved to minimize the frequency offset of several hundreds of KHz and the phase jitter generated from a tuner or an RF oscillator.

Abstract: Apparatus for eliminating sign uncertainty in a coherent phase generated carrier demodulator in a multi-channel sensor system has a downconverter array arranged to separate the in-phase component I and the quadrature phase component of the sensor output for each channel. A coordinate transformer uses the in-phase component and quadrature phase component to calculate an arctangent for the phase angle for each channel. A digital signal processor adds 180° to each arctangent calculation for which the tangent is a negative number.

Abstract: Methods and devices for demodulators for continuous phase modulation waveforms. A modulated sampled signal is received. A consecutive sequence of the modulated sampled signal is buffered. The consecutive sequence is compared with all possible valid modulated sampled signals. A bit decision representing a demodulation of the consecutive sequence of the modulated sampled signal is determined based on a closest valid modulated sampled signal located closest to the consecutive sequence of the modulated sample signal in a constellation.

Abstract: Quadrature demodulator (10) and quadrature modulator (30) which comprise a first oscillator (11) and a second oscillator (12), a separate excitation signal being fed to the first osciallator (11) and second oscillator (12) in order to determine the point in time at which switching between two stable states lakes place, and the quadrature demodulator (10) and quadrature modulator (30) further comprise excitation means (17, 18). In the quadrature demodulator (10), an input signal Si(t) is fed, by means of which signal a parameter of one of the elements of the first and the second oscillator (11, 12) is influenced and a set of quadrature Output signals Io, Qn is produced.

Abstract: A digital demodulator which coherently demodulates a low-IF or zero-IF complex signal using a complex-valued phase-locked loop (CPPL). The CPPL includes a numerical controlled oscillator, four multipliers and two combiners to provide independent phase/frequency and amplitude outputs. The CPLL exhibits in first order PLL dynamics without a loop filter in the feedback loop to the NCO. However a filter with one or more poles may be included in the feedback circuit to exhibit 2nd or higher order PLL dynamics. The CPLL allows coherent demodulation of extremely low FM modulation indexes whereby the incoming frequency drift may be larger than the frequency deviation. It can also be used to coherently demodulate signals which have combined amplitude and phase characteristics.

Abstract: A circuit for demodulating a modulated carrier includes a sampler receiving the modulated carrier signal and generating a digital carrier signal represented by a sequence of sample values in accordance with a clock signal at a first sampling frequency. A complex mixer frequency shifts the digital carrier signal by a frequency equal to one fourth the sampling frequency to generate a frequency shifted data signal with a sampling rate at the first sampling frequency. A decimation circuit generates four decimated signals from the frequency shifted signal, each at a decimated sampling rate. A resampling circuit generates a data signal at the decimated sampling rate and at a phase independent of the clock signal.

Abstract: A system and method for detecting the presence of a transmitted waveform in a high noise environment. The system and method can detect and classify a modulated waveform without first demodulating the signal, and can detect and classify a waveform having a frequency offset without compensating for the frequency offset.

Abstract: A demodulator demodulates a modulated signal waveform in a data communication system. A phase tracking loop tracks the phase of said modulated signal waveform and having an inner block decoder configured to decode a set of vector pairs of the modulated signal waveform at a decode rate to generate associated codewords and phase estimates. A group of data symbols consisting of the first data symbols of the modulated signal waveform are run backwards through the phase tracking loop. An outer block decoder receives the associated codewords generated by said inner block decoder and utilizes and corrects only codewords associated with symbols after and including the group of data symbols consisting of the first data symbols of the modulated signal waveform.

Abstract: An automatic gain control circuit capable of accurately executing control irrespective of the conditions of control is to be provided. This automatic gain control circuit includes a multiplier, low pass filters, a comparator, first and second absolute value circuits, and a delay circuit. The multiplier multiplies a first quadrature signal Ich by a signal supplied from the low pass filters. The first absolute value circuit figures out the amplitude of the first quadrature signal Ich supplied from the multiplier, and the second absolute value circuit figures out the amplitude of the second quadrature signal Qch. The delay circuit delays the output signal from the second absolute value circuit by at least an equivalent of one symbol. The comparator compares, after the delay circuit delays the output signals, the amplitude of first quadrature signal and the amplitude of second quadrature signal.

Abstract: A frequency and phase estimator simultaneously estimates the frequency and phase of an MPSK modulated signal with a frequency uncertainty range on the order of the symbol rate. The estimator defines a plurality of contiguous bands within the frequency uncertainty range of the signal, estimates the frequency to one of the bands, and utilizes the frequency estimate to derive a phase estimate. In a preferred embodiment, a plurality of signal samples of the frequency shifted signal in each of said bands are accumulated to produce a vector for each band, and the frequency estimate is selected in one of said bands, based upon the magnitude of the corresponding vector. The phase is estimated from the argument of the corresponding vector. The present invention is particularly suited for burst modems or TDMA systems, where frequency and phase estimates must be derived reliably from a limited number of incoming symbols at the beginning of each burst.

Abstract: A radio receiver improves audio quality by eliminating the audio clicks caused by fading conditions. The receiver detects the presence of the fading condition based on a large phase variation of a faded received signal during a time interval. When a fading condition is detected, the radio receiver reduces the large phase variation associated with the received signal to eliminate the audio clicks.

Abstract: A proximity IC card (PICC) which relates to and provides a carrier synchronization type demodulator, which is able to stably receive a PSK signal from a PICC and is enhanced in noise immunity, and which is realized at a low cost and in such a way as to have a small size. The carrier synchronization type demodulator is adapted to receive and demodulate PSK-modulated subcarrier signals to be synchronized with and superposed onto a sent carrier signal.

Abstract: A demodulator of a differential detection system for a &pgr;/4 shifted QPSK or DQPSK modulation wave in digital communication. The demodulator includes a differential detector connected to receive orthogonal components of the modulation wave, a corrector connected to receive an output of the differential detector for correcting a deviated distribution of signal points on a constellation, and a slicer/decoder connected to receive an output of the corrector. The slicer/decoder decodes a received bit from the signal points after the deviated distribution is corrected. The corrector has average calculators connected to receive respective outputs of the differential detector, and subtractors connected to receive the associated outputs of the differential detector and also to receive associated outputs of the average calculators for subtracting an average value of the outputs of the differential detector from the outputs of the differential detector.

Abstract: Alignment methods and apparatus for I/Q phase and amplitude error correction and image rejection improvement that may be used at the time of circuit fabrication or on chip for use during operation. The alignment method may be used to improve the I/Q phase and amplitude accuracy of a direct conversion transceiver or to improve image rejection in an up or downconversion mixer. For alignment purposes, a pilot tone of a selected frequency is used to provide a calibration reference, with adjustments being made in phase and amplitude to drive the I and Q phase and amplitude mismatch toward a minimum.

Abstract: A digital modulation signal measuring device of the present invention is designed to generate a signal string of an ideal base band component after correcting frequency deviation of a base band component included in a digital modulation signal to be measured, detect a noise component included in the digital modulation signal based on this ideal base band component, and output (display) the spectrum of the detected noise component together with the spectrum of the base band component. Therefore, according to the digital modulation signal measuring device of the present invention, it is possible to easily recognize the quality of a noise component included in a digital modulation signal during actual transmission of the digital modulation signal, to guess the cause of generating the noise and to improve the transfer quality at easy.

Abstract: A fading rate of a mobile terminal unit is estimated by a fading rate estimation unit and an optimum step constant is decided by a step constant determiner depending on the estimated fading rate. This step constant is fed back to a feedback data calculator, so that a reception level can be converged to an ideal level even under a fading environment and the like.

Abstract: A demodulation circuit for demodulating a frequency diverse complex modulated carrier comprises an A/D converter generating a series of samples representing the modulated carrier, a mixer operating to mix the series of samples with a sine wave of one fourth the sampling frequency represented by a series of sine wave values occurring at the sampling frequency, and a decimation filter operating at a decimation factor equal to the sampling frequency divided by the frequency difference between adjacent sub-spectra for folding the sub-spectra and retaining a portion of the mixed down series of samples.

Abstract: The present invention relates to a demodulation structure and method for downconverting and demodulating a digitally modulated signal So, with a local oscillator means (1; 5; 8) for providing a local oscillator signal Slo a mixer means (2) for mixing said local oscillator signal Slo and said digitally modulated signal S0 in order to obtain a mixed signal, a lowpass filter means (3) for lowpass filtering the mixed signal from the mixer means (2) and an analog-to-digital converting means (4) for converting the filtered signal from the lowpass filter means (3) into a downconverted and demodulated digital signal Sl, whereby the local oscillator signal is set in respect to the modulated digital signal so that the downconverted and demodulated digital signal output from the analog-to-digital converting means comprises to serially arranged information parts. The present demodulation structure provides a very simple structure with improved amplitude and phase imbalances.

Abstract: A phase correction circuit for a radio communication apparatus includes a variable gain amplifier and phase correction unit. The variable gain amplifier amplifies a transmission/reception signal on the basis of a gain variably set in accordance with a gain signal. The phase correction unit has a phase characteristic opposite to that of the variable gain amplifier, corrects the phase of the transmission/reception signal on the basis of the gain signal supplied to the variable gain amplifier, and cancels a phase change of the signal caused in the variable gain amplifier.

Abstract: A demodulation method and apparatus applicable to e.g., digital broadcast in accordance with the orthogonal frequency division multiplexing system (OFDM), in which synchronization of carrier frequency correction control of OFDM signals can be maintained in stability. Based on the information indicating the demodulation reliability, such as the result of cumulative addition of CP values, supplied from the wide range fc error—CPE calculating circuit (10), or the transmission control signal detection information, supplied from the transmission control information demodulating communication (17), a holding circuit (14) verifies whether or not the wide range fc error—CPE calculating circuit (10) is making an erroneous detection operation. If the wide range fc error—CPE calculating circuit (10) is making an erroneous detection operation, the holding circuit (14) outputs the wide range fc error output in the previous symbol, without updating the information on the wide range fc error.

Abstract: Algorithms are provided to adjust the gain and phase imbalance of I/Q modulators and demodulators. The imbalances are adjusted through an adjustment range and the corresponding image signal powers determined. The minimum image signal power identifies the calibration settings for the gain and phase imbalances.

Abstract: A system for recovering and demodulating a carrier includes a carrier recovery loop and a data detector. The carrier recovery loop receives the carrier as an input and produces a recovered carrier at a frequency approximately equal to that of the carrier. The carrier recovery loop includes a downconverting mixer, a ×5 multiplier, a ×4 multiplier, and a phase locked loop. The downconverting mixer receives the carrier input, and the phase locked loop provides a VCO reference frequency through the ×5 multiplier to the downconverting mixer, which provides a frequency shifted signal. The frequency shifted signal is passed through the ×4 multiplier as input to the phase locked loop. The data detector receives the carrier and the recovered carrier as inputs and uses the recovered carrier to demodulate the carrier and detect I channel data and Q channel data.

Abstract: A method and offset removing apparatus for removing DC offset from a digital baseband signal value pair included in a set of digital baseband signal value pairs is described. The digital baseband signal value pairs, when plotted on a complex signal space I-Q diagram, lie on a predetermined figure. The I and Q coordinates of the central point of this predetermined figure are determined by a two-dimensional fitting of this figure through a subset of signal value pairs included within the set. These coordinates of this center point are subsequently subtracted from the I and Q coordinates of the digital baseband signal.

Abstract: A method and apparatus for phase-domain semi-coherent demodulator including a receiver for receiving at least a phase component of an input signal. The phase domain semi-coherent demodulator may include a decision unit for forming a decision based on a delayed reference signal and the phase component of the input signal. In addition the phase domain semi-coherent demodulator may include a phase sum adder for subtracting the decision from the phase component of the input signal to form a rotated input phase, a second phase sum adder for subtracting the delayed reference signal from the rotated input phase to form a resulting signal, and a scaler for scaling the resulting signal to form an update signal. A third phase sum adder adds the update signal to the delayed reference signal to form a reference signal.

Abstract: A small scale circuit can be realized. A timing circuit 30 detects a burst symbol signal period from outputs I and Q of a demodulating circuit 1A for orthogonally detecting a received signal obtained by time-multiplexing digital signals by BPSK, QPSK, and 8PSK modulation. A pattern regeneration circuit 40 outputs the same PN code pattern as on a transmission side. Inverting circuits 13 and 14 output I, Q as RI, RQ for a bit ‘0’ of a PN code pattern, and −I, −Q as RI, RQ for a bit ‘1’. A phase error table 15A contains a phase error between the phase of a received signal point as an output of the inverting circuits 13 and 14 and an absolute phase only for a first quadrant of RI, RQ. A phase error detecting processing circuit 16A reads the phase error data corresponding to the absolute value of RI, RQ, and adjusts the data into the data depending on the current quadrant of the RI, RQ.

Abstract: A wideband fast-hopping receiver front-end uses direct digital synthesis (DDS) to provide quadrature LO signals to the front-end's mixers. A DDS circuit stores multiple digital word sequences which represent desired waveforms, and outputs desired sequence pairs to a pair of DACs in response to a clock signal and a command signal. The DACs convert the sequences to analog signals, which are filtered and squared as necessary to provide quadrature LO signals to the mixers. Frequency hopping is accomplished by changing the command signal, which causes a different pair of sequences to be output and the frequency of the LO signals provided to the mixers to be changed. Active image rejection is combined with DDS LO generation to provide faster frequency hopping. The front-end is combined with an ADC and a communications signal processor to provide a complete system, all of which can be integrated together on a common substrate.

Abstract: In-phase and orthogonal components of a base band signal having a preamble symbol are squared to obtain squared in-phase orthogonal components. Amount of correlation is obtained between the squared in-phase component and a ½ symbol frequency component output from a VCO or an oscillator, and amount of correlation is obtained between the squared orthogonal component and the ½ symbol frequency component. Finally, a phase control signal for carrying out a phase control is generated by using the obtained amount of correlations.

Abstract: When reception of a multiplexed wave to be PSK-modulated of BPSK, QPSK, and 8PSK is started, a selector (16A) of a demodulating circuit (1A) reads high-order three bits &Dgr;&phgr;(3) of phase error data corresponding to I and Q symbol streams out of one phase error table (15-1) for BPSK among phase error tables provided for each modulation system and each phase rotation angle. A received-signal-phase rotation angle detecting circuit (8A) detects phase rotation angles of portions corresponding to bits (1) and (0) of a frame-synchronizing signal of a received symbol stream from the &Dgr;&phgr;(3) and the MSB of I symbol stream and outputs the phase rotation angles to a remapper (7) to make the remapper perform absolute phasing.

Abstract: A modulator for modulating carrier wave signals with an in-phase component signal and a quadrature component signal includes a fixed frequency signal generating means for generating two fixed-frequency signals differing 90 degrees in phase, a variable frequency signal generating means for generating a signal whose frequency can be varied according to a modulated signal to be produced, an in-phase component carrier wave signal generating means for mixing one fixed-frequency signal and the variable-frequency signal to generate a carrier wave signal for an in-phase component, a quadrature component carrier wave signal generating means for mixing the other fixed-frequency signal and the variable-frequency signal to generate a carrier wave signal for a quadrature component, an in-phase component modulating means for modulating the in-phase component carrier wave signal with the in-phase component signal, and a quadrature component modulating means for modulating the quadrature component carrier wave with the quadr

Abstract: A network receiver is configured for receiving a modulated carrier signal representing a data frame from another network transceiver via a network medium, the modulated carrier signal may be either a pulse position modulated (PPM) carrier, a quadrature amplitude modulated (QAM) carrier, or a compatibility mode frame including both PPM and QAM portions. The network receiver is configured to select an A/D sampling clock frequency corresponding to the detected frame type.

Abstract: Disclosed is a 16-ary QAM (Quadrature Amplitude Modulation) demodulation apparatus for receiving an input signal Rk(Xk, Yk) comprised of a kth quadrature-phase component Yk and a kth in-phase component Xk, and generating soft values &Lgr;(sk,0), &Lgr;(sk,1), &Lgr;(sk,2) and &Lgr;(sk,3) for the input signal Rk(Xk, Yk) by a soft decision means. A first calculator decides a soft value &Lgr;(sk,2) of a third demodulated symbol among 4 demodulated symbols by subtracting a distance 2a between two demodulated symbols on the same axis of a mapping table from a level |Yk| of the quadrature-phase component Yk. A second calculator decides a soft value &Lgr;(sk,3) of a fourth demodulated symbol by calculating Yk+&agr;*Zk using a first variable a determined by the soft value of the third demodulated symbol and a sign bit of the quadrature-phase component Yk.

Abstract: The present invention relates to n-port junction devices for processing modulated digital RF signals, n being an integer larger than 3, the n-port junction device comprising two RF input ports (4, 5), two passive signal-combining means (2, 3) connected to each other wherein respectively one of the passive signal-combining means (2, 3) is connected to one of the RF inputs (4, 5), and at least two power sensors (P1, P2) wherein each of the passive signal-combining means (2, 3) has at least an output port (6, 7) and each output port (6, 7) is connected to a power sensor (P1, P2). The two passive signal-combining means (2, 3) are connected with each other by means of a phase shifting element (10).

Abstract: A carrier recovery apparatus for digital Quadrature Amplitude Modulation (QAM) receivers is disclosed. The carrier recovery apparatus includes a phase detector, a lock controller, a frequency locker and a phase loop filter, and provide phase/frequency error information for a numerically controlled oscillator (NCO) to generate recovered carrier frequency. The phase detector detects the symbol energy information and the phase error information of the extracted symbols from the I/Q extractor. The lock controller monitors the symbol energy from the phase detector, separates the extracted symbols into two groups: valid and non-valid, and outputs the control flag of valid symbols into both the frequency locker and the phase loop filter. To achieve a wide range acquisition and a good tracking performance, the lock controller controls the operation of the frequency locker and the phase loop filter in three operations.

Abstract: A method for detecting the lock-in of a loop that synchronizes an internal clock on the transmission of value pairs provided by a demodulator. According to the method, a module of a vector that has as components the values of one of the value pairs is calculated, and the module is compared with a threshold that is smaller than a theoretical module. The locked-in condition is determined according to the ratio of the number of modules found to be greater than or smaller than the threshold to the total number of modules. In one preferred method, the threshold is incremented by a first value if the module is greater than the threshold and is decremented by a second value if the module is less than the threshold. A lock-in detection circuit for detecting the lock-in of a loop is also provided. A calculation circuit calculates a module of a vector that has as components the values of one of the value pairs. A register stores a threshold and a comparator compares the stored threshold with the calculated module.

Abstract: A phase detection apparatus for receiving an I-channel signal an a Q-channel signal as a received signal modulated with a quadrature phase-shift keying and compensating a phase rotation error of the received signal, includes: a phase detector for detecting a phase error through the use of the I- and Q-channel signals and providing an error signal; a shifting unit for shifting said I-channel signal by a plurality of predetermined different numbers of bits and providing shifted I-channel signals; a first multiplexing unit, in response to an external selection signal, for selecting signals among said shifted I-channel signals; a subtracting unit for providing difference signals between said selected signals and said Q-channel signal; a comparison unit for comparing said difference signals with a reference signal and producing logic signals; a logic gate for producing a logically ORed signal of said produced logic signals; and a second multiplexing unit, in response to said ORed signal, for selecting a signal fro

Abstract: A system for recovering and demodulating a carrier includes a carrier recovery loop and a data detector. The carrier recovery loop receives the carrier as an input and produces a recovered carrier at a frequency approximately equal to that of the carrier. The carrier recovery loop includes a downconverting mixer, a ×5 multiplier, a ×4 multiplier, and a phase locked loop. The downconverting mixer receives the carrier input, and the phase locked loop provides a VCO reference frequency through the ×5 multiplier to the downconverting mixer, which provides a frequency shifted signal. The frequency shifted signal is passed through the ×4 multiplier as input to the phase locked loop. The data detector receives the carrier and the recovered carrier as inputs and uses the recovered carrier to demodulate the carrier and detect I channel data and Q channel data.

Abstract: Reduction in an output level of an IQ demodulator starts when a QPSK modulation signal is at a first level. Reduction in an output level of a first variable attenuater occurs when the QPSK modulation signal is at a second level higher than the first level. Reduction in an output level of a second variable attenuater starts when the QPSK modulation signal is at a third level higher than the second level.

Abstract: I and Q symbol streams are demodulated from a received signal of a wave to be PSK-modulated in which BPSK-modulated frame-synchronizing signal and superframe-identifying signal respectively having a 20-symbol length and an 8 PSK-modulated digital signal are time-multiplexed by a demodulating circuit (1). BPSK-demapped bit streams B0 to B3 are generated by a BSPK demapper (3) in accordance with criterion border lines obtained by rotating a basic BPSK criterion border line and a basic criterion border line whose received-signal points are the same as Q-axis on, I-Q phase plane by &pgr;/4, 2&pgr;/4, and 3&pgr;/4 counterclockwise.

Abstract: The serial data signal obtained by carrying out an N/D conversion at two times the modulation speed is S/P-converted, at a data ratio of 1:2, into a pair of parallel data signals of the modulation speed. The demodulation process is carried out by parallelly processing the pair of parallel data signals, resulting in that the demodulation speed is equal to the modulation speed. The serial data obtained by carrying out the A/D conversion at four times the modulation speed is S/P-converted at a data ratio of 1:4, and is then similarly subjected to demodulation at the demodulation speed equal to the modulation speed. With this arrangement, the demodulator carrying out the digital signal processing can be applied to communication systems having a high modulation speed.

Abstract: A demodulation circuit for demodulating a received signal including carriers in quadrature modulated by digital signals and/or in which the processing is performed on two carriers in quadrature. The circuit includes a demodulator, an analog-to-digital converter, a correcting circuit, and a derotator. The correcting circuit provides signals to the derotator based on the derotator output signals and on signals provided by the analog-to-digital converter.

Abstract: An angular difference detector detects an angular variation according to respective signs of current xy coordinate values supplied from an FFT calculation unit and respective signs of preceding xy coordinate values. An angle calculation unit calculates an angle value of a frequency component according to respective absolute values of xy coordinate values supplied from the FFT calculation unit. Another angular difference detector classifies a difference between a current angle value and a preceding angle value supplied from a subtractor as one of a plurality of angle regions to detect an angular difference. A demapper performs demapping according to a sum of the angular variation supplied from the angular difference detector and the angular difference supplied from that another angular difference detector.

Abstract: An automatic gain control circuit capable of accurately executing control irrespective of the conditions of control is to be provided. This automatic gain control circuit includes a multiplier, low pass filters, a comparator, first and second absolute value circuits, and a delay circuit. The multiplier multiplies a first quadrature signal Ich by a signal supplied from the low pass filters. The first absolute value circuit figures out the amplitude of the first quadrature signal Ich supplied from the multiplier, and the second absolute value circuit figures out the amplitude of the second quadrature signal Qch. The delay circuit delays the output signal from the second absolute value circuit by at least an equivalent of one symbol. The comparator compares, after the delay circuit delays the output signals, the amplitude of first quadrature signal and the amplitude of second quadrature signal.

Abstract: A caller identification (ID) demodulating apparatus and method using multiple thresholds. An apparatus according to one embodiment comprises a zero crossing detector for generating pulses at points where the modulated caller ID information crosses zero and outputs each pulse as a zero crossing signal, a data extractor for computing a zero crossing interval between each output pulse of the zero crossing signal, and comparing the zero crossing interval with a plurality of thresholds to generate extracted data, and a clock generator for generating a data recovery clock signal for recovering the extracted data in response to the extracted data, wherein the data recovery clock signal is enabled at the middle point of the unit data length of the extracted data. The apparatus and method use multiple thresholds to extract data from caller ID modulated in a CPFSK format, thereby accurately extracting data at an interval where data “0” and “1” coexist.

Abstract: An I/Q demodulator optimized with a minimum amount of hardware. First and second multiplexers generate I and Q signals with respect to an input data signal; and first and second 2-decimation units decimate the I and Q signals generated by the first and second multiplexers, to output effective I and Q signals. A filtering unit filters the effective I and Q signals. As a result, a size of the hardware is reduced, and an operation frequency of the filter is reduced.

Abstract: A QPSK modulation scheme uses a data spreading mechanism to rob a relatively limited portion of available transmitter power, and inject into the QPSK waveform a prescribed amount of carrier signal power, through which detection and non-regenerative extraction of the carrier at the receiver may be achieved without incurring a signal-to-noise degradation penalty. In addition, the injected carrier-based modulation scheme of the invention may employ high performance forward error correction coding, to significantly reduce the signal power required for achieving a very low energy per bit-to-noise density ratio (Eb/N0)—on the order of one to zero dB.

Abstract: A demodulator for demodulating clear mode waveforms such as Phase Shift Keyed and Quadrature Amplitude Modulated waveforms, is capable of demodulating signals with much greater data rates than the clock rate of the device in which the demodulator resides by converting serial input samples into vectors. The input vectors are converted to “soft-decision” (data estimate) vectors which are input to a parallel-to-serial multiplexer, and the vector elements are output serially at the symbol clock rate to represent demodulated data. In the preferred embodiment, the vector demodulator at least includes a preprocessor, a digital phase shifter, and a symbol demodulator which, inter alia, outputs a phase rotator command signal to control the carrier recover phase rotation process in the digital phase shifter.

Abstract: The present invention is a demodulator and a method of demodulating burst communications. A demodulator (100, 200) includes a phase angle source (18), coupled to a current received burst communication, which provides a phase angle of the current received burst communication; a comparator (20), coupled to the phase angle source and a source of an estimated phase angle, which provides an output signal representing an angular difference between a phase of the current received burst communication and the estimated phase angle; and a phase lock loop (20), coupled to the output signal, which provides the estimated phase angle. The phase lock loop includes a Doppler accumulator (102) which provides a Doppler output which provides compensation in the estimated phase angle for the Doppler effect produced by relative motion between the demodulator and a source of the burst communications.