Abstract: A circuit and method for correcting phase of a received phase modulated (PM) signal. The method uses k most recently received data bits, which alternate between in-phase I and quadrature Q bits, as an address for a lookup table 60. The lookup table outputs a phase figure 62 derived from a reconstructed waveform. When the most recent k bit is a Q bit, the complement 68 of the phase figure 62 is calculated to yield a phase correction. Otherwise, the phase figure is the phase correction, which is applied to adjust the phase of a delayed version of the received signal. The delayed, phase adjusted signal is then applied to correct the phase of a received signal. The circuit splits an input PM signal in parallel between a matched filter 54 and a delay block 76, 88. The matched filter output provides the input to a register 58 for storing the k data bits. The delay block holds the PM signal until it is input into a loop phase shifter 78 synchronously with the phase correction.

Abstract: A time-sliced discrete-time Phase Locked Loop which is suitable for simultaneously synchronizing multiple input signals to multiple output signals is provided by implementing a discrete-time phase detector, loop filter, and voltage controlled oscillator that together operate as a single discrete-time PLL in hardware and applying control logic to retrieve the history for each signal pair from a context memory (RAM), to enable the discrete-time PLL hardware, and to store the resulting history in the context memory for use in subsequent operations for a particular input/output signal pair.

Abstract: A circuit and method for correcting timing of a received phase modulated signal. The method uses k most recently received data bits as an address for a lookup table 60. The lookup table includes reconstructed waveforms from which a timing weighing factor is determined. The received PM from time t1 is delayed, phase adjusted, and multiplied by the timing weighing factor, the product of which is used by a timing adjust block 50 to adjust timing of the PM signal at a time after t1. The circuit inputs a PM signal to a timing adjust block 50. The output is split between a matched filter 54 and a loop phase shifter 78. The matched filter feeds alternating I and Q bits into a register 58 that holds k data bits, which are used as an address for a lookup table 60. The output of the lookup table 60 becomes a timing weighing figure, which is multiplied 74 with an output of the loop phase shifter 78 and then input into the timing adjust block 50 for adjusting timing of a PM signal.

Abstract: To provide a clock and data recovery circuit which facilitates alteration of the frequency range and adjustment of characteristics.

Abstract: A demodulating device capable of high-efficiency, high-accuracy phase noise correction control and improved in quality and reliability. A digital signal generating portion synchronously detects a modulated input signal and subjects the signal to A/D conversion to generate digital signals corresponding to phase axes. A timing recovery portion extracts symbol timing of the digital signals to recover timing. A carrier recovery portion sets a gain for a phase difference between the timing-recovered digital signals in accordance with a phase noise correction signal, and rotates symbols in a direction to suppress phase noise in accordance with an oscillation signal generated based on the gain, to recover carrier.

Abstract: A method and apparatus are provided that performs timing acquisition for multiple radio terminals. According to one aspect of the present invention the invention includes receiving a sequence of symbols modulated onto a carrier frequency over a channel and demodulating the symbols using a clock frequency. The invention further includes determining a frequency offset of the received symbols with respect to the clock frequency and applying the determined frequency offset to adjust the clock frequency.

Abstract: A demodulator demodulates a modulated signal waveform in a data communication system. A phase tracking loop tracks the phase of said modulated signal waveform and having an inner block decoder configured to decode a set of vector pairs of the modulated signal waveform at a decode rate to generate associated codewords and phase estimates. A group of data symbols consisting of the first data symbols of the modulated signal waveform are run backwards through the phase tracking loop. An outer block decoder receives the associated codewords generated by said inner block decoder and utilizes and corrects only codewords associated with symbols after and including the group of data symbols consisting of the first data symbols of the modulated signal waveform.

Abstract: When a clock reproduction circuit (6) is locked, a phase comparator (9) detects a level difference &Dgr;E between a zero crossing point and a true 0 level. The level difference &Dgr;E represents an offset level and is output as an offset detection signal. After being planarized in the LPF (12), the level difference &Dgr;E is input to adders (14) and (15) so as to cancel a DC offset.

Abstract: In some embodiments of the present invention, there is a system and method of synchronizing a QAM demodulator by determining a phase offset error value between an actual phase shift of a received symbol and an estimated phase shift value.

Abstract: A system for recovering and demodulating a carrier includes a carrier recovery loop and a data detector. The carrier recovery loop receives the carrier as an input and produces a recovered carrier at a frequency approximately equal to that of the carrier. The carrier recovery loop includes a downconverting mixer, a ×5 multiplier, a ×4 multiplier, and a phase locked loop. The downconverting mixer receives the carrier input, and the phase locked loop provides a VCO reference frequency through the ×5 multiplier to the downconverting mixer, which provides a frequency shifted signal. The frequency shifted signal is passed through the ×4 multiplier as input to the phase locked loop. The data detector receives the carrier and the recovered carrier as inputs and uses the recovered carrier to demodulate the carrier and detect I channel data and Q channel data.

Abstract: In-phase and orthogonal components of a base band signal having a preamble symbol are squared to obtain squared in-phase orthogonal components. Amount of correlation is obtained between the squared in-phase component and a ½ symbol frequency component output from a VCO or an oscillator, and amount of correlation is obtained between the squared orthogonal component and the ½ symbol frequency component. Finally, a phase control signal for carrying out a phase control is generated by using the obtained amount of correlations.

Abstract: Improved carrier recovery, symbol timing, and carrier phase tracking systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system are disclosed. Carrier and phase recovery systems operate on complex signals representing symbols having the same time stamp for each phase error term. in-phase signals are sampled twice a symbol at the in-phase symbol sampling time and at the quadrature-phase symbol sampling time. The signals are de-multiplexed to generate I and XI data streams, where I represents the in-phase sampling time signals and XI represents mid-symbol point sample times. A similar procedure is carrier out on quadrature-phase signals. When the in-phase signal is de-multiplexed to generate a symbol I, the quadrature-phase signal is de-multiplexed to generate its mid-symbol point XQ. Both I and Q are decoded in a decision device to define a symbol error term, which is combined with the opposite mid-symbol signal to define a phase error term PI and PQ for each rail.

Abstract: A reproduced signal is adaptively equalized in an adaptive equalizer after going through an AD converter. The AD converter, the adaptive equalizer, a phase error detector, a phase shifter, a DA converter, a loop filter, and a variable frequency oscillation circuit, all of which structure a PLL circuit, and a clock signal phase-locked to reproduced data is fed back to the AD converter. The phase shifter slightly shifts, as appropriate, a phase error detected in the phase detector according to the change in a barycenter of tap coefficients detected in a tap barycenter detection circuit. With such structure, signals can be processed in an accurate manner without causing competition in operation between the PLL and adaptive equalization.

Abstract: A decoder of a data signal subjected to phase shifting keying (PSK) modulation uses a plurality of phase locked loops (801-1 to 801-n) having an inner decoder for short block codes, at least one of which is adapted to apply excess processing power to process a selected burst of the data signal, such as processing the burst with multiple initial phase/frequency error estimates. A selection circuit identifies the burst and supplies to said one of said plurality of phase-locked loops (801-1 to 801-n) for re-processing the bust with excess processing power. An outer Reed-Solomon block decoder (319) may be used to correct errors in the codewords from the phase locked loops and may be used in the selection of the burst by the selection circuit.

Abstract: The present invention is a method for demodulating a PSK modulated signal wherein the PSK system incorporates a transmitter generating a PSK modulated signal and wherein the transmitter is crystal based. A crystal based receiver receives the PSK modulated signal and the delta phase between the recovered PSK signal and a receiver generated reference signal is measured; the measurement is repeated with a predetermined phase shift. Voltage values are derived representing the results of each of the measurements and are applied to an analog-to-digital converter to derive digital values representing the two phases measured, and a corresponding delta phase. The digital values are applied to a look up table to derive a phase correction for the reference signal, and several methods are described to perform various types of PSK demodulation.

Abstract: The invention relates to a method of estimating the frequency offset of a packet of phase modulated symbols received with phase error, the method comprising: applying a phase correction to the symbols of the received packet for all possible pairs of frequency offset and phase offset; and selecting from said offset pairs, the pair which provides the most likely packet of corrected symbols, thereby determining the frequency offset of the received packet. Compared with known solutions, the invention makes it possible to reduce errors concerning estimated frequency. Advantageously, the method comprises a step of quantizing the possible phase corrections, thereby making it possible to reduce the complexity of the calculations to be performed, without degrading performance.

Abstract: Improved carrier recovery, symbol timing, and carrier phase tracking systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system are disclosed. Carrier and phase recovery systems operate on complex signals representing symbols having the same time stamp for each phase error term. in-phase signals are sampled twice a symbol at the in-phase symbol sampling time and at the quadrature-phase symbol sampling time. The signals are de-multiplexed to generate I and XI data streams, where I represents the in-phase sampling time signals and XI represents mid-symbol point sample times. A similar procedure is carrier out on quadrature-phase signals. When the in-phase signal is de-multiplexed to generate a symbol I, the quadrature-phase signal is de-multiplexed to generate its mid-symbol point XQ. Both I and Q are decoded in a decision device to define a symbol error term, which is combined with the opposite mid-symbol signal to define a phase error term PI and PQ for each rail.

Abstract: A system for demodulating narrowband signals from a received signal is disclosed. The system includes a downconverter that is operative to downconvert the received signal. Furthermore, the system includes a baseband processor that is configured to decode the narrowband signal from the received signal, as well as decode wideband signals. In this respect, the system is operative to demodulate both narrowband and wideband signals without the use of separate demodulation paths.

Abstract: In a demodulator, a local oscillator 7 feeds a local oscillation signal having a frequency of f/n to a phase shifter 8. In the phase shifter 8, all-pass filters 9 and 10 produce two oscillation signals separated in phase by 90/n degrees from each other, which are then fed individually to n-times frequency multiplier 11 and 12. The n-times frequency multipliers 11 and 12 multiply the frequency of those oscillation signals by a factor of n and thereby produce two carriers having a frequency of f and separated in phase by 90 degrees from each other, which are then fed to mixers 2 and 3.

Abstract: In the present invention, the amplitude subtracting type of phase detector of the timing recovery section outputs a difference &ggr;i of a synthesized amplitude deviation at ½ of a symbol time. The averaging section computes an average value of this difference &ggr;i and outputs a phase control signal Vi corresponding to the average value to the phase controller. The phase controller controls a timing phase of the sampling clock according to this phase control signal Vi. Dichotomizer generates a recovered symbol clock by dichotomizing the sampling clock that has been timing phase controlled. Removal of DC offset from and demodulation of the sampled baseband signal is executed in parallel to the above processing using the recovered symbol clock with the Nyquist data extracting section, the offset detector, the offset correcting section, and the data determining section.

Abstract: A demodulation device having a demodulating circuit that conducts the primary demodulation of received modulation wave, and a carrier recovery circuit that regenerates a carrier from demodulation signal by the demodulating circuit and conducts the secondary demodulation of baseband signal using the carrier.

Abstract: In a detection circuit for ASK or OOK modulation, the received modulated signal is ac coupled to a dc restoration circuit and amplified. The dc restoration is carried out on signal peaks corresponding to “mark” intervals of the modulated signal. Thus data may be recovered even in the presence of high levels inband continuous interfering signals.

Abstract: A phase-noise compensated digital communication receiver (40, 40′, 40″) includes a carrier tracking loop (56) which imposes a transport delay on a carrier tracking loop signal (60) before that signal (60) is fed back upon itself. The carrier tracking loop (56) includes a phase rotator (58) that rotates a down-converted digital communication signal (50) by a phase determined by a phase-conveying signal (72). A carrier tracking loop signal is obtained from the carrier tracking loop and delayed in a delay element (82) by a duration that compensates for the transport delay. A phase rotator (84) then rotates the delayed carrier tracking loop signal through a phase value determined by the phase-conveying signal (72) to obtain an open-loop phase signal (86) from which data are extracted. Different embodiments of the receiver (40, 40′, 40″) are provided to accommodate adaptive equalizer (54) issues.

Abstract: An AFC (Automatic Frequency Control) device and a method of controlling reception frequency in a dual-mode terminal. When a dual-mode terminal uses one or two AFC devices, the time required for acquiring tracking synchronization in a PLL circuit for a first frequency can be reduced using a test augmentation frequency which is an integer multiple of a tracking synchronization acquiring residual frequency of a PLL circuit for a second frequency to which the first frequency transitions for reliable synchronization acquisition. Errors with respect to an output dynamic range caused by use of two AFCs are reduced and thus the demodulation performance of a receiver is ensured by varying quantization bits of an A/D clock based on the dynamic range of residual errors in a frequency area. The demodulation performance can also be ensured by operating an ACPE circuit for an AFC device having many residual frequency errors.

Abstract: A first order phase-locked loop includes a tuning circuit which allows phase lock to be quickly reached, and to be maintained during transient situations such as loss of the data signal. Such an improved circuit has a tuning circuit for the voltage controlled oscillator which utilizes two capacitors. Two signals are used to drive a first, larger, capacitor, and have the same duty cycle when the capacitor voltage is proper and the voltage controlled oscillator is operating at the correct frequency. A second, smaller, capacitor is used to quickly achieve phase lock with the incoming data signal. The use of two oppositional signals to drive the capacitors allows them to more quickly be charged or discharged to the proper voltage level to obtain both frequency and phase lock with the incoming data signal. Thus, the circuit is able to quickly acquire lock during power-up, or reacquire lock under circumstances where the operating condition of the circuit changes suddenly.

Abstract: A phase error detector in a digital demodulator estimates phase error by dividing the difference between an in-phase demodulated signal and the transmitted data values included in the in-phase demodulated signal by the sum or difference of a quadrature demodulated signal and a product signal. The product signal is equal to the in-phase demodulated signal multiplied by a fixed gain constant. The phase error detector thereby obtains an error estimate that is substantially independent of the transmitted data values.

Abstract: A method for simple synchronization of a receiving device to a transmitting device for a transmission of a dispersed-energy QPSK signal. The signal is composed at the transmitting end of two mixed products, the mixed product of an I signal and a transmitted carrier and the mixed product of a Q signal and the transmitted carrier shifted through 90°. In order to synchronize the received carrier to the transmitted carrier without any problems, it is proposed that an amplitude of an SQ signal be measured at the time of the zero crossing of the rising flank of an SI signal, and that an amplitude of the SI signal be measured at the time of the zero crossing of the falling flank of the SQ signal. The measured values are a measure of a discrepancy from synchronicity between the received carrier and the transmitted carrier, and that the frequency of the received carrier be varied until the amplitude of an error signal obtained from this measurement is zero.

Abstract: Proposed is a switchable loop filter structure which allows a dual mode operation. A low bandwidth mode is used during acquisition of a channel. In case of high rate reception the low bandwidth synthesizer loop is combined with a high bandwidth carrier recovery loop. This combination allows steps of the synthesizer which are tracked in the carrier recovery loop. The tuner steps are used to compensate input signals frequency drift. An algorithm is proposed which allows acquisition in a low synthesizer loop bandwidth mode and switching to a high bandwidth synthesizer loop mode while maintaining frequency lock. This allows the use of a high bandwidth synthesizer loop and a low bandwidth carrier recovery loop. This combination is best for reception of low rate input signals. The synthesizer loop compensates for residual FM of the tuner Local Oscillator.

Abstract: A method and apparatus for timing recovery in modem receivers. The timing recovery circuit includes a voltage controlled oscillator for controlling the voltage controlled sampling frequency of an analog-to-digital converter. The oscillator generates a timing clock that is dependent on an average phase error signal calculated from Nyquist signals of the input signal. A phase detector circuit is used for generating an instantaneous phase error signal of the in-phase and quadrature-phase signals. A digital loop filter receives the instantaneous phase error signal over time to generate the average phase error signal. The average phase error signal is conditioned further (after conversion to analog) by an analog loop filter such that the average phase error signal adjusts the timing clock generated by the oscillator. The low pass filter provides control of the acquisition and steady state operations by changing the gain and pole parameters of the filter.

Abstract: Improved phase synchronization circuits shorten the length of the synchronization pull-in time. The phase synchronization circuit according to the first invention changes the free-running frequency of the voltage control oscillation means starting from one limit frequency of the sweep range when detecting a state of non-synchronization and performing a synchronization pull-in operation. The phase synchronization circuit according to the second invention changes the free-running frequency of the voltage control oscillation means starting to one limit frequency of the sweep range faster than a prescribed speed and then changes the free-running frequency of the voltage control oscillation means to the other limit frequency of the sweep range at the prescribed speed when detecting a state of non-synchronization and performing a synchronization pull-in operation.

Abstract: A two-mode demodulating apparatus for use in a radio terminal in a mobile communication system has a linear reception demodulating circuit and a non-linear reception demodulating circuit which can be selectively operated by selecting a mode. The non-linear reception demodulating circuit has a second frequency converting unit for frequency-converting a received signal into a low-frequency signal, a variable-band filtering unit for allowing a signal in a desired band contained in an output of the second frequency converting unit to pass therethrough, and a non-linear reception demodulating process unit for performing a non-linear reception demodulating process on an output from the filtering unit, thereby receiving and demodulating a linear modulated wave and a non-linear modulated wave while suppressing increases of the circuit scale and the power consumption, and generalizing a hardware structure for an applied non-linear modulating system.

Abstract: An apparatus estimates the frequency difference existing between the carrier frequency of a received digital signal and the frequency of a signal from a local oscillator contained in a receiver of the received signal. The receiver performs quadrature demodulation on the received signal. The apparatus includes a detector that detects the noise level received in the band of the receive filters, a processor for computing discrete Fourier transforms on the received signal transposed into baseband, a summer for summing the energy levels detected on either side of the center frequency of the receive filters, a subtractor for subtracting the noise level from the energy bands, and a comparator for comparing the resultant energy levels and delivering an estimate &egr; of the frequency difference.

Abstract: A phase shift keyed carrier recovery and demodulator circuit which includes a phase detector and subsequent feedback control loop circuitry which maintains an initial phase relationship. By comparing an incoming phase modulated carrier with the multiple phase outputs of a local oscillator, the circuit is able to generate a correcting signal which allows coherent phase tracking of the incoming phase modulated carrier. The phase detector produces a correction signal which allows the circuit to phase lock any two sequential phases of the locally generated phase outputs to phase positions on either side of the phase of the incoming phase modulated carrier. Once the circuit has obtained carrier phase lock, the multiple phases produced by the local oscillator will remain fixed (without phase change) relative to the initial detected phase of the incoming phase modulated carrier.

Abstract: A remote data collection system for collecting usage data from an endpoint includes a monitoring module coupled to the endpoint, the monitoring module having a wireless transmitter to transmit the usage data. The system also includes a receiver to receive usage data from the wireless transmitter of the monitoring module, the receiver capable of receiving in parallel data transmitted at arbitrary frequencies within a radio channel.

Abstract: The invention relates to methods and apparatus for synchronizing a local data clock with timing information from received data, during a fraction of a frame period. The apparatus includes a transition detect unit, a digital phase comparator, a phase regulator, and a control unit, for detecting the bit transitions of received data, determining the phase difference between timing information and a local data clock, advancing or retarding the local data clock, and enabling and disabling the synchronization in accordance with a predetermined rate.

Abstract: A phase-noise compensated digital communication receiver (40, 40', 40") includes a carrier tracking loop (56) which imposes a transport delay on a carrier tracking loop signal (60) before that signal (60) is fed back upon itself. The carrier tracking loop (56) includes a phase rotator (58) that rotates a down-converted digital communication signal (50) by a phase determined by a phase-conveying signal (72). A carrier tracking loop signal is obtained from the carrier tracking loop and delayed in a delay element (82) by a duration that compensates for the transport delay. A phase rotator (84) then rotates the delayed carrier tracking loop signal through a phase value determined by the phase-conveying signal (72) to obtain an open-loop phase signal (86) from which data are extracted. Different embodiments of the receiver (40, 40', 40") are provided to accommodate adaptive equalizer (54) issues.

Abstract: The present invention relates to methods and devices for such control and supervision of an oscillator signal from a controllable oscillator that is done mainly to control the frequency variation of the oscillator signal. According to the invention, the controllable oscillator is controlled by a controlling voltage, which in turn is modified by a correction signal, generated in a control loop. A time discrete representation of a secondary phase is generated in the control loop, the secondary phase corresponding to a frequency being the difference between the frequency of the oscillator signal and a constant frequency. A time discrete approximation signal is generated in dependence of the time discrete representation of the secondary phase. A time discrete error signal is generated in dependence of the time discrete approximation signal, the time discrete error signal indicating the difference between the actual frequency slope of the oscillator signal and a desired frequency slope.

Abstract: A device for demodulating a binary signal having a predetermined carrier frequency and phase-modulated by encoded pulses. The device includes a phase-locked loop circuit having a phase comparator followed by a low-pass filter and a voltage-controlled oscillator, which is voltage-controlled by the output of the filter. The voltage-controlled oscillator outputs a binary signal that is synchronous with the modulated signal and at a frequency N times the carrier frequency. The phase-locked loop circuit also includes a divider that divides by N the output signal of the oscillator and supplies the divided signal to one input of the phase comparator. Thus, a binary signal synchronous with the modulated signal and having a frequency equal to the carrier frequency is supplied to one input of the phase comparator. The other input of the phase comparator receives the modulated signal.

Abstract: A differentiate and multiply based timing recovery in a quadrature demodulator. A quadrature-modulated signal is received and demodulated by quadrature mixing the received modulated signal with a local oscillator signal. In-phase and quadrature down-converted signals are sampled. The sampled signals are differentially detected to produce binary digits from symbols conveyed by the quadrature-modulated signal. Sampling is controlled by a symbol timing recovery signal derived from the in-phase and quadrature down-converted signal. Thereto, the respective in-phase and quadrature down-converted signals are differentiated with respect to time, the respective differentiated signals are multiplied by the quadrature and in-phase signals, respectively, and the multiplied signals are subtracted from each other so as to produce a difference signal. The difference signal controls the symbol timing recovery in that a clock signal controlling the timing of the sampling is locked to the difference signal.

Abstract: A high frequency signal receiving apparatus comprises a microcomputer, coupled to a control terminal of PLL circuit, interface circuit of demodulating section and to a control terminal of decoding section. The microcomputer has input/output terminals coupled to external equipment. The microcomputer controls any one of the PLL circuit, demodulating section and decoding section, based on a signal from the external equipment. With the above described constitution, the burden of external equipment may be alleviated.

Abstract: A signal from a local oscillator is separated by a 90.degree. phase sifter into an in-phase component and an orthogonal component. Each of the components is multiplied by a received IF signal in a mixer to perform pseudo-synchronous detection. The pseudo-synchronously detected signals are subjected to A/D conversion in an A/D converter, and preamble portions are integrated in integrating circuits. The integrated signals are latched in latch circuits. The timing of the latch is controlled by a timing circuit. A power detector detects the power of the latched signal, and the maximum value is detected in a maximum value detector to determine timing at which the power becomes maximum in selectors. A phase (.theta.) is determined from the inverse tangent of the maximum value, and is used as an initial value of a voltage controlled oscillator (VCO) in a demodulator.

Abstract: Circuit and method for generating a signal for use in locking a second signal on a first signal. The first and second signals have an associated frequency. A first beat note signal and a second beat note signal are generated from the first and second signals, respectively, when the frequencies of the first and second signals are not equal. The circuit includes a first and second flip-flop and detector circuitry. The first flip-flop is configured to receive the first and second beat note signals for generating a first state signal. The first flip-flop generates the first state signal by sampling the second beat note signal at a first periodic interval of the first beat note signal. The second flip-flop is configured to receive the first and second beat note signals for generating a second state signal. The second flip-flop generates the second state signal by sampling the second beat note signal at a second periodic interval of the first beat note signal.

Abstract: A method and an apparatus for generating an error estimate as input for an error recovery loop of a demodulator which receives an offset quadrature phase shift keyed (OQPSK) signal having a symbol interval. The method comprises the following operations: (a) receiving at least four consecutive complex samples z.sub.-1/2, z.sub.0, z.sub.1/2 and z.sub.1 obtained by sampling the OQPSK signal at half the symbol interval; and (b) computing the error estimate based on the complex samples z.sub.-.sub.1/2, z.sub.0, z.sub.1/2 and z.sub.1.

Abstract: A Steered Frequency Phase Lock Loop (SFPLL) comprises a phase loop that functions like a normal phase locked loop (PLL) and locks to the input signal, and a frequency loop that uses a reference frequency to influence the phase loop and effectively confines the output frequency of the phase loop and the SFPLL to be in a range of frequencies close to the reference frequency. The reference frequency is chosen to be very close to the input signal frequency that it is desired the SFPLL lock to. The SFPLL comprises a phase detector (10), a frequency detector (22), first and second gain components (12, 24), first, second and third filter components (14, 18, 26), a summer (16) and a voltage controlled oscillator (VCP)(20). By a judicious choice of the gains in the phase and frequency loops the SFPLL can be designed so that the range of frequencies to which the SFPLL will lock can be confined to an arbitrarily small region around the reference frequency (.omega.'.sub.r).

Abstract: Known is a zero intermediate frequency receiver or zero-IF receiver in which DC-offset correction is done in the I- and Q-paths, after mixing down of the received RF-signal or of an IF-signal. Such a DC-offset correction is not sufficient for high gain I- and Q-paths, particularly not in pagers for receiving long messages. Furthermore, no optimal power saving is achieved if such a receiver alternately operates in receive mode and sleep mode. A zero intermediate frequency receiver is proposed in which DC-offset correction is distributed over the high gain I- and Q-path. Preferably, blocking means are provided between DC-offset correction circuits and low pass filters in the I- and Q-path to prevent that an output signal of an upstream DC-offset correction circuit in the path excites a downstream low pass filter in the path during DC-offset correction. Herewith, considerable power savings are achieved.

Abstract: In a method for realizing carrier wave synchronization in the receptio of a multi-level, two-dimensional modulation signal, the received signal is demodulated by using at least one local oscillator (3) in order to generate the local oscillator frequency. In the method, the local oscillator (3) performs a frequency scanning within the frequency range of the reception; during the frequency scanning, a demodulated signal point system is formed of the received signal by using the frequency generated by the local oscillator (3). Furthermore, the demodulated signal point system in the method is examined in order to determine at which point of time the frequency of the local oscillator is synchronized to the carrier wave frequency of the received modulation signal.

Abstract: By using the two square-law circuits for squaring the common mode and orthogonal components of the carrier wave and by using the multiplying circuit for multiplying these squared signals, the Costas loop carrier recovery circuit can be constituted. The carrier recovery circuit is constituted such that a phase synchronous circuit constituted by a PLL is controlled by a signal obtained by removing a sign component from an input carrier wave.

Abstract: A demodulator with a filter having a reduced number of filter taps without a sacrifice in filter accuracy. The demodulator includes elements that generate a data stream that carries a component of an input signal in response to a data stream that carries samples of the input signal. The demodulator also includes elements that generate a sample clock for sampling the input signal such that the sample clock is preselected to cause the data stream that carries the component to carry alternating samples that are substantially equal to zero. The filter in the demodulator has a set of filter taps which are arranged to tap only the samples in the data stream that carries the component that are not substantially equal to zero.

Abstract: A digital receiver includes a mixer stage receiving a carrier signal S(t) and delivering an intermediate frequency signal S.sub.FI (t) to a demodulation stage. The mixer stage is furnished with a PLL circuit for generating a signal at a given frequency. The digital receiver further includes a phase noise digital correction stage for tapping off a noise signal .phi..sub.n (t) generated by the PLL circuit in the mixer stage and for compensating the noise signal .phi..sub.n (t) in the demodulation stage.

Abstract: Analog signals encoded with quadrature amplitude modulation (QAM) pass through a coaxial cable at a particular baud rate. These signals have a carrier frequency individual to the TV station being received. They are mixed with signals from a variable frequency oscillator to produce signals at a particular intermediate frequency (IF). An analog-digital converter (ADC) converts the IF signals to corresponding digital signals which are demodulated to produce two digital signals having a quadrature phase relationship. After being filtered and derotated, the digital signals pass to a symmetrical equalizer including a feed forward equalizer (FFE) and a decision feedback equalizer (DFE) connected to the FFE in a feedback relationship. The DFE may include a slicer providing amplitude approximations of increasing sensitivity at progressive times. Additional slicers in the equalizer combine the FFE and DFE outputs to provide the output data without any of the coaxial cable noise or distortions.