Abstract: The invention provides a PSK signal demodulation device of small circuit scale that is capable of both rapid synchronization pull-in and stable demodulation operation following demodulation synchronization pull-in. To achieve these capabilities, the phase shift keying signal demodulation device of this invention is provided with an adaptive line enhancer demodulation circuit, a PLL demodulation circuit, and a switching circuit that switches the demodulation circuits from the adaptive line enhancer demodulation circuit to the PLL demodulation circuit. The switching circuit switches between the demodulation circuits such that, upon start of input of an N-phase PSK signal, demodulation is effected by the adaptive line enhancer demodulation circuit until phase synchronization is established between the input N-phase PSK signal and the recovered carrier, and demodulation is effected by the PLL demodulation circuit after establishment of phase synchronization.

Abstract: A carrier phase synchronizing circuit is disclosed, that comprises an AFC loop and a PLL, the AFC loop including an AFC complex multiplexing device, an LPF, a PLL complex multiplying device, a phase detector, a loop filter, an AFC filter, and a NCO, the PLL including a PLL multiplying device, a phase detector, a PLL filter, and a NCO. A loop range, a frequency control width, and a control time interval of each of the AFC filter and the PLL filter are controlled corresponding to a time change amount of the frequency error that is detected in the PLL.

Abstract: A digital demodulator (10) reads symbol samples into a memory buffer (38) that can be played forward and backward into a phase locked loop (48). During an initial non-data directed symbol timing estimating phase (56) the demodulator (10) achieves an approximate frequency synchronization and starts to achieve phase synchronization on an incoming stream of symbols. During a first forward readout pass (58) of stored samples, the phase locked loop (48) begins the frequency and phase convergence. During subsequent pass (60) using a reverse readout of stored samples, phase locked loop (48) continues to converge toward zero phase error. Then another forward pass (66), phase locked loop (48) achieves usable frequency and phase synchronization of carrier and begins valid data extraction.

Abstract: It is an object to enlarge the phase range in which a phase error can be determined. An operating block (1) calculates a power of carriers from data DI and DQ. An ideal symbol estimating block (2a) outputs a plurality of ideal symbols which correspond to the power of carriers outputted from the operating block (1). A phase error tan(.theta.) calculating block (2b) calculates prediction phase errors between the ideal symbols and the symbol given by the data DI and DQ. A phase error determining block (3) determines a phase error from among the prediction phase errors outputted from the phase error tan(.theta.) calculating block and outputs the phase error.

Abstract: The demodulator is for processing a signal having a carrier modulated by (0, .pi.) phase shifts and sampled at a rate that is at least twice the frequency of the carrier co. It comprises, in cascade: a first multiplier for squaring successive samples e(t), a phase locked loop adjusted to the frequency of the carrier, thereby performing programmable digital filtering; a divider for dividing the frequency by two, reconstituting the carrier from the output of the phase locked loop; a second multiplier receiving the sampled input signal and the output signal from the divider and an output lowpass digital filter. A phase adjustment circuit is placed upstream of one of the inputs of the second multiplier.

Abstract: A carrier recovery apparatus includes a loop filter that converges quickly and corrects a large frequency error. The carrier recovery apparatus includes a multiplier, a matched filter, a phase error detector, a loop filter and a numerically controlled oscillator (NCO). A bandwidth varying circuit varies the bandwidth of the loop filter according to whether the signal output from the matched filter is phase-locked. A frequency error detector detects a frequency error from the output of the matched filter. An adder adds each level of an input sweep signal and the output of the loop filter, and supplies the added results to the NCO. A switch selectively supplies the output of the loop filter to the adder. A controller generates a sweep signal having a plurality of levels and controls turning the switch on and off.

Abstract: A digital phase detector which generates low jitter when the phase-locked-loop is in lock. A delay line, combined with an UP/DOWN phase detector causes substantial overlap in the UP and DOWN signals from the detector. When the PLL is in lock, the overlapping signals substantially cancel each other out, minimizing the variations in the output frequency. Two approaches are disclosed: one delaying the UP signal sufficiently to overlap the DOWN signal, the other using a delay and an exclusive OR gate to generate the DOWN signal.

Abstract: A demodulator for radio data communications is provided, which is capable of an optimum demodulation operation in response to the environmental condition under which communications are made independent of the preamble length. A phase angle calculator calculates a phase angle of the input signal. A frequency offset calculator calculates an offset of a carrier frequency of the input signal. A PLL generates a compensated phase angle of the input signal to compensate the frequency offset. A first detector detects the input signal using the uncompensated phase angle to generate a first detected signal. A second detector detects the input signal using the compensated phase angle to generate a second detected signal. A first phase distortion calculator calculates a phase distortion of the first detected signal. A second phase distortion calculator calculates a phase distortion of the second detected signal.

Abstract: Analog signals encoded with quadrature amplitude modulation (QAM) pass through a coaxial cable at a particular baud rate. These signals have a carrier frequency individual to the TV station being received. They are mixed with signals from a variable frequency oscillator to produce signals at a particular intermediate frequency (IF). An analog-digital converter (ADC) converts the IF signals to corresponding digital signals which are demodulated to produce two digital signals having a quadrature phase relationship. After being filtered and derotated, the digital signals pass to a symmetrical equalizer including a feed forward equalizer (FFE) and a decision feedback equalizer (DFE) connected to the FFE in a feedback relationship. The DFE may include a slicer providing amplitude approximations of increasing sensitivity at progressive times. Additional slicers in the equalizer combine the FFE and DFE outputs to provide the output data without any of the coaxial cable noise or distortions.

Abstract: The number of oscillators required to construct a digital radiocommunication terminal can be reduced and a circuit used for the digital radiocommunication terminal can be reduced in size. For this purpose, the digital radiocommunication terminal for effecting information transmission using an N (integer)-phase-shift-keyed signal (identification symbol number N=4 upon .pi./4 shifted QPSK modulation), is constructed such that an oscillation frequency generated from a reference oscillator employed with a frequency synthesizer is selected to have a common multiple of a second intermediate frequency and an identification symbol phase N and is supplied to a detector for outputting received data therefrom.

Abstract: An apparatus and accompanying method for demodulating with baseband Doppler frequency shift compensation. An RF section (20) down-converts received data communication signals (12) to baseband. A/D converters (24, 26) digitize I, Q quadrature baseband signal components. Phase (32) and frequency (50) tracking loops reside on a common digital ASIC substrate (28). A complex multiplier (30) rotates digitized baseband signals by a digitized oscillation signal, producing Doppler shift compensated signals. The phase tracking loop (32) estimates data and generates a pure phase error signal from which data modulation and Doppler shift compensation influences have been removed, which drives a frequency discriminator (52) that identifies either clockwise or counterclockwise phase rotation for each symbol (18). An integrator (54) combines identification results over a burst and a numerically controlled oscillator (56) adjusts the digitized oscillation signal frequency in a constant frequency step.

Abstract: In a receiver, a frequency offset estimating circuit inputs a received signal and a decision value from a decision circuit, and estimates a frequency offset. A CIR estimating circuit inputs the estimated frequency offset, the received signal and the decision value, and estimates CIR. A complex conjugate circuit calculates a complex conjugate of the CIR. A multiplication circuit multiplies the complex conjugate and the received signal. Receiving the multiplied value, the decision circuit outputs a decision value.

Abstract: A multi-level demodulator has a VCO (32) and two reference frequency sources (50, 41). A relatively long time-constant loop (45, 47) has an input coupled to the VCO, an input coupled to one of the reference frequency sources (41) and an output coupled to the VCO. A relatively short time-constant loop (51, 30) has an input coupled to the VCO, an input coupled to the other reference frequency source (50) and an output coupled to the VCO.

Abstract: A receiver comprises a demodulator for demodulating a received signal, a clock recovery circuit for regenerating a clock phase-synchronized with a symbol clock component included in the received signal and a frequency offset compensating unit for controlling a variable division ratio of a variable divider constituting a phase-controlled loop of the clock recovery circuit so as to compensate for a frequency offset corresponding to a difference between a frequency of the symbol clock component included in the received signal and a free-running frequency of the clock recovery circuit. The receiver is constructed such that the compensation for the frequency offset is performed with operation timing different from that of the clock recovery circuit.

Abstract: A method of and an apparatus for phase synchronization of a bit rate clock signal generated in an RDS receiver with a digital RDS signal demodulated on the receiver side, in which both the bit rate clock signal and the RDS signal have the same bit rate. Upon turning on of the RDS receiver and/or switching over of the same to a transmitter receiving frequency different from that received so far, a control signal is generated which, upon occurrence of the next rising edge or, alternatively, of the next falling edge of the RDS signal, effects such a phase angle shift of the bit rate clock signal that the bit rate clock signal, starting from that occurrence, is in phase synchronism with the RDS signal.

Abstract: A first AFC apparatus receives and detects I and Q signals from a received first FSK signal with a local osc signal; demodulates the I and Q signals; F/V-converts I or/and Q signals into a voltage; compares it with a reference; and detects a frequency deviation direction of the local osc signal from the carrier signal according to the results of comparing and the demodulating. The local osc frequency is controlled by a given amount according to the result of the frequency deviation direction detection. A second AFC apparatus receives and detects I and Q signals using a first osc signal; FSK-modulates the I and Q signals with a second local osc signal having a lower frequency than the first local osc signal; and compares the frequency of the second FSK signal and the second local osc signal to supply a demodulation result. A frequency control for the first local osc signal is obtained by an averaging circuit averaging the modulation result.

Abstract: In the case where a received multi-level orthogonal amplitude signal is not synchronized with a local carrier frequency signal, a digital multiplexing radio receiver recognizes that an adaptively-equalized data exist in a specified area on the phase plane of Ich and Qch orthogonal coordinates. The receiver controls an operation of amplifying Ich and Qch demodulated signals to a fixed level, based on the data of which exist in the specified area. Similarly, the receiver controls a phase of the local carrier frequency signal based on the data of existing in the specified area, and controls tap coefficients of an adaptive transversal filter which equalizes the received multi-level orthogonal amplitude signal. In the specified area, a distance between signal points of multi-level orthogonal amplitude signal is large so that influence caused by a phase rotation is small. Accordingly, the digital multiplexing radio receiver can rapidly and stably return to a synchronous mode.

Abstract: A synchronous detector has first and second mixer circuits and a voltage controlled oscillator. The voltage controlled oscillator provides a local oscillator signal directly to the second mixer circuit and indirectly to the first mixer circuit through a phase transformer. The output of the first and second mixer circuits are combined in combiner circuitry to produce a jitter cancelled output signal. The jitter cancelled output signal is filtered in a loop filter and applied to the voltage controlled oscillator to control the frequency and phase of the local oscillator signal. The combiner circuitry includes a summer and a jitter cancellation filter. The jitter cancellation filter is preferably a high pass filter matched to spectrum of the signal detected. The output of the first mixer circuit is passed through the high pass filter into one input of the summer while the output of the second mixer circuit is passed to the second input of the summer. The output of the summer is passed to the loop filter.

Abstract: An automatic frequency control apparatus includes a sampling portion for sampling the signal transmitted according to a phase-shift keying method, a phase difference detector for detecting the phase difference between the currently sampled signal and the immediately preceding sampled signal, and a phase bin comparator for determining which of a number of reference phases the phase of the transmitted signal is closest to, using a quantization characteristic of phase during transmission. The frequency offset generated by the distance between the frequency of a carrier wave and the local oscillation frequency of a receiver, or by the Doppler shift, in a MPSK communication method is determined as the phase difference between the detected phase difference information and the determined reference phase information. The apparatus can be used for the automatic frequency control of a modem using any type of MPSK modulation.

Abstract: A delay detection is performed to baseband signals subjected to an orthogonal demodulation to obtain a delay detection output and a frequency error is found from the delay detection output. The frequency error is converted into a control frequency which is accumulated to generate a phase rotation .phi. which is used to rotate the input baseband signals before being subjected to the delay detection, thereby to perform frequency correction. By providing filters downstream of a phase rotation circuit and upstream of a delay detection circuit, automatic frequency control can be realized without performance deterioration.

Abstract: A demodulating apparatus for receiving and demodulating a signal transmitted by use of a plurality of carriers having different frequencies employs a demodulator for frequency-analyzing a specific time waveform defined by data in one modulation symbol duration and guard times accompanying the data to provide a demodulated waveform. A correlation detector determines a correlation value between the received signal and a signal spaced apart from the received signal by a period corresponding to one modulation symbol duration. An integrating circuit integrates the correlation detected signal, and a peak-position discriminator determines a peak-position of an integrated value supplied thereto from the integrating circuit. Correction of timing and frequency offsets in the demodulation processing is carried out on the basis of the peak-position information discriminated by the peak-position discriminator.

Abstract: In a PSK-modulating arrangement including a voltage controlled oscillator (VCO), a demodulator, a phase detector and a loop filter, a carrier phase lock detecting apparatus is equipped with the arrangement, the apparatus comprising a first multiplier for inversely modulating a demodulated signal by a reference carrier signal from the VCO, a second multiplier for multiplying the output of the first multiplier by an input PSK-modulated signal and a decision circuit for detecting carrier phase lock in response to the output of the second multiplier.

Abstract: A Radio Frequency (RF)-band tuner stage is combined with a quadrature downconverter stage in a single shielded enclosure as an RF-to-baseband pulse amplitude modulated tuner suitable for receiving RF-band signals from an LNB or the like and converting the signals directly to signals in a desired digital format. The bandwidths within the two stages are optimized for digital PAM demodulation, such as PSK or QAM, and certain functions are shared, such as automatic gain control and carrier tracking information. Electronically switchable attenuators and voltage-variable gain controlled amplifiers, in connection with a low-phase-noise local oscillator employing a microstrip resonator, provide for over 70 dB of dynamic range. The IF frequency and bandwidth are selected so that voltage-variable tunable bandpass filters of conventional design may be used to obtain over 40 dB of radio frequency image rejection necessary for reception of PAM signals.

Abstract: In quadrature amplitude modulation, circular concentric decision regions capitalize on the observation that when the sample matrix is rotating, it is possible to identify samples more accurately by the radius of their orbit rather than their phase at any given time. The first embodiment provides that a scalar 1.sub.i is calculated for each constellation point so that the constellation point corresponding to the minimum 1.sub.i value is the symbol which the decision device decides was transmitted. The nearest constellation point having the minimum magnitude difference represents the decision. In the second embodiment, two complementary weighting factors are used to provide a weighted average of the two decision criteria in order to make the correct decision. .alpha. is the weight for representing standard rectangular decision regions, while (1-.alpha.) is the weight for representing the circular decision regions. The range for .alpha. is 0<.alpha..ltoreq.1. The variable .alpha.

Abstract: An adaptive equalizer includes a multiplier for multiplying, by corrective data, an output signal from a filter unit for compensating for a signal distortion to which input digital data are subjected, a decision unit for estimating and outputting symbols of output data from the multiplier, a subtractor for subtracting an output signal of the decision unit from the output data from the multiplier, multipliers for inversely correcting the output signals from the decision unit and the subtractor which are corrected by the multiplier, a coefficient updating unit for updating the coefficients of the filter unit based on an output signal from the multiplier which inversely corrects the output signal from the subtractor, and a frequency offset estimating unit for estimating corrective data based on a frequency offset on the basis of the output signal from the multiplier which inversely corrects the output signal from the subtractor, and using the estimated corrective data as corrective data for the multiplier which

Abstract: A QAM demodulator that samples an IF input modulated with data at a fractional complex sampling rate between one and two times the data rate. The use of a fractional sampling rate significantly reduces the number of components necessary to implement the demodulator, particularly in the equalizer section of the demodulator which corrects for channel distortion. The fractional sampling rate demodulator architecture of the invention provides a significant reduction in integrated circuit surface area needed in a VLSI implementation.

Abstract: The present invention relates to a carrier recovery (CR) circuit for recovering carriers from offset quadrature phase shift keying (O-QPSK) modulated carriers, in which each of two orthogonal sequences of burst signals, to be modulated by the O-QPSK system, has a preamble field set in a prescribed bit pattern. In a Costas loop for recovering carriers by the QPSK system, a 1/2 symbol delay circuit makes the phases of burst signals inputted to two orthogonal channels identical to each other. A phase comparator for the bit timing recovery field adds with an adder 193 a detected carrier value detected by an arc tangent calculating circuit and a value resulting from the delaying of the detected carrier value with a one-symbol delay circuit, and supplies the added detected carrier value. A switching circuit switches and supplies the outputs of phase comparators, and enters the output into a loop filter.

Abstract: A digital phase shifter for phase-shifting a cyclic input signal includes first--third dividers 1, 4 and 8, first and second phase detectors 2 and 6, first and second voltage controlled oscillators (VCOs) 3 and 7, and a digital comparator 5. The input signal F(IN) and a clock signal F(VCO3) output from the first VCO3 are divided by N and M at the first and second dividers, respectively and phases of the divided signals are compared at the first phase detector 2, whereby the leading edges of the input and clock signals are synchronized. The second divider 4 also generates a count value (m) representing a cycle order number to the comparator, where it is compared with a preset value (.phi.) for determining the amount of phase shift, and an equate pulse EQ5 is generated when the compared values are the same.

Abstract: To demodulate an analog signal having information modulated by a carrier, the analog signal is chopped by a chopper, the chopped signal is digitized by a sigma-delta analog-to-digital converter to produce a series of digital samples at a sampling frequency, the digital samples are filtered in a digital decimating filter to produce data words, and the data words are modulated by an intermediate frequency signal to produce a detected information signal. The various frequency signals are generated by a phase-lock loop so that the intermediate frequency is the difference between the carrier frequency and the chopping frequency, and both the chopping frequency and the intermediate frequency are sub-multiples of the sampling frequency.

Abstract: A demodulator circuit and a demodulating method are disclosed. A demodulator including a phase-locked loop for a receive carrier recovery or a phase lock recovery demodulates an input received signal and a band of a loop filter of the phase-locked loop is controlled by a control signal. A bit error rate monitor detects a bit error rate of a demodulated outputs the control signal on the basis of the bit error rate result of the demodulator, and a loop filter band controller output from the bit error rate monitor. Hence, the bit error rate of the demodulated signal is detected and the loop filter band of the phase-locked loop of the demodulator is controlled based on the detected bit error rate. As a result, an exact control of the loop filter band of the demodulator can be performed on the basis of the received signal state without using any received signal power detector, any C/N detector or the like.

Abstract: A clock recovery circuit having a feedback system in a .pi./4 shift QPSK demodulator, comprising a signal state transition detector for detecting state transitions between consecutive symbols of the demodulated baseband signal which is formed from the detected baseband signal by .pi./4 reverse shifting. According to degree of the detected symbol state transition, the 1/2-symbol delayed baseband signal is shifted by the amount of .pi./8 in phase. According to direction of the detected symbol state transition, the .pi./8 phase shifted baseband signal is converted into an error signal in use for the feedback system. An oscillator generates a clock signal of a frequency controlled by the error signal such that the error signal is reduced in the feedback system.

Abstract: A phase locked loop circuit for synchronizing with carrier wave includes: a variable divider for generating a first reference signal and a second reference signal whose frequency is same as the frequency of the first reference signal and whose phase is shifted by 90 degrees with respect to the phase of the first reference signal, the variable divider varying the frequencies of the first reference signal and the second reference signal in accordance with a control signal; a first multiplier for multiplying an input signal by the first reference signal; an exclusive OR circuit for operating an exclusive OR of the input signal and the output signal of the first multiplier; a phase comparator for receiving the first reference signal, the second reference signal and the output signal of the exclusive OR circuit, and detecting a value and a direction of a phase difference between the input signal and the first reference signal to produce phase comparison signal including series of clock pulses whose number correspo

Abstract: In a timing extraction device coupled to a demodulator which derives a real signal component and an imaginary signal component from a signal received via a transmission line, a band-pass filter extracts a 1/2-Nyquist frequency from either the real signal component or the imaginary signal component. The 1/2-Nyquist frequency includes two symmetrical frequency components. A vector conversion unit processes the 1/2-Nyquist frequency so that a vector signal corresponding to one of the two symmetrical frequency components of the 1/2-Nyquist frequency is output from the vector conversion unit. A square multiplier squares the vector signal received from the vector conversion unit and thereby generates a phase error signal indicating timing information concerning the analog signal. The phase error signal has an angle which is double an angle of the vector signal.

Abstract: A demodulating apparatus, which includes an up/down counter which counts up and down in accordance with a phase detection signal from a phase detector, an addition/subtraction unit which adds and subtracts the value (.DELTA.F1, .DELTA.F2) of the synchronization pull-in range to the count output, a counter stoppage unit which monitors a recovered carrier synchronization detection signal INIT and freezes the count output of the up/down counter immediately when detecting a disconnection of the input signal, and a synchronization pull-in range setting unit which expands the synchronization pull-in range at the same time as this to make it .DELTA.F2. The time required until establishment of synchronization with the input signal next to be received after the disconnection of an input signal is shortened.

Abstract: In a receiver for use in demodulating a modulated wave modulated by a digital data signal arranged within a preselected channel to produce a reproduced data signal by the use of a local frequency signal of a local frequency, a VCO and a PLL circuit are intermittently put into active states with reference to an offset frequency between a channel frequency and the local frequency. The PLL circuit is put into the active state for a time interval determined by the offset frequency before reception of the preselected channel while the VCO is put into the active state during the active state of the PLL circuit and during reception of the preselected channel. A duration of the active state in the PLL circuit becomes long when the offset frequency does not fall within a predetermined range determined by predetermined offset frequencies and, otherwise, the duration of the active state in the PLL circuit becomes short.

Abstract: A timing circuit having an analog to digital converter to sample an analog signal, a controlled oscillator for controlling sample times of the analog to digital converter, a circuit to detect pulses in the analog signal, a phase error circuit to subtract one of two samples from the other to create a phase error measurement and a frequency error circuit to add two samples together to create a frequency error measurement. The two samples are taken from either side of a pulse. The phase error measurement is used by the controlled oscillator to adjust the sample timing to take samples at desired locations on the pulse. The circuit also contains constant values used to compensate for the pulse being asymmetrical and to compensate for other pulses that occur close to the detected pulse. The circuit also inserts a known frequency in place of the analog signal to establish a frequency of the controlled oscillator.

Abstract: A method and apparatus for coherent demodulation for phase shift keyed signals including:a phase estimation stage based on a sequence of reference symbols transmitted at the start of each block of data anda second order phase-locked loop stage.

Abstract: L-band tuner stage is combined with a quadrature downconverter stage in a single shielded enclosure as an L-band-to-baseband PSK tuner suitable for receiving L-band signals from an LNB and converting the signals directly to signals in a desired digital format. The bandwidths within the two stages are optimized for digital PSK demodulation, and certain functions are shared, such as automatic gain control and carrier tracking information. Electronically switchable attenuators and voltage-variable gain controlled amplifiers, in connection with a low-phase-noise local oscillator employing a microstrip resonator, provide for over 70 dB of dynamic range. The IF frequency and bandwidth are selected so that voltage-variable tunable bandpass filters of conventional design may be used to obtain over 40 dB of radio frequency (RF) image rejection necessary for reception of PSK signals.

Abstract: The channel frequency of a digital radiotelephone is coarse tuned utilizing the phase information of the symbols. According to the invention the phase change between the measured phases of one or more received symbols (d) and the previous symbol (e) is detected, the phase change being compared with allowed phase changes. Based on this a decision (g) is made concerning the phase of the transmitted symbol, the phase error (f.sub.err) or difference between the decision (g) and the measured phase change (d) is generated, and on this basis the channel frequency is adjusted.

Abstract: A received analog signal applied to a data modem receiver is sampled and converted into a digital signal which is demodulated into a complex baseband signal. If the demodulated complex baseband signal is deviated in phase from a QAM signal point due to phase jitter, the phase error is detected, and a replica of the phase jitter is calculated and applied to impart phase rotation for canceling out the phase jitter that is contained in the complex baseband signal. In each sampling cycle, the phase error between the phase-rotated signal and the modem output signal is detected in order to correct equations for calculating the replica of the phase jitter in the next sampling cycle.

Abstract: A non-coherent demodulator 1 multiplies a modulated intermediate frequency (IF) signal with a signal from a local oscillator 2 to produce a first pseudo baseband signal having frequency error. The first pseudo baseband signal is supplied to a wide band PLL type demodulator 15. A low-pass filter 26 removes noise component from a first control signal from a loop filter 19 in the wide band PLL type demodulator 15 to produce a second control signal. Multipliers 24 and 25 multiply the first pseudo baseband signal with an output of a voltage-controlled oscillator 27 controlled by the second control signal to produce a second pseudo baseband signal having smaller frequency error. The second pseudo baseband signal is supplied to a narrow band demodulator 14 and converted into a baseband signal.

Abstract: The presence of a communication signal having a predetermined recognition pattern of symbols that occur at a predetermined rate (1/T) is detected by processing the communication signal to extract in-phase (I) and quadrature-phase (Q) components of the symbols; processing the extracted components to compute a complex autocorrelation function of the extracted components with a time parameter equal to an integer multiple (nT) of the symbol period (T); integrating the complex autocorrelation function over a substantial portion of the recognition pattern; and comparing the magnitude of the integrated complex autocorrelation function with a predetermined threshold value to detect the presence of the recognition pattern.

Abstract: A spread spectrum demodulator for use with a phase-shift-keying modulated spread spectrum signal used in mobile satellite communications. An objective of the spread spectrum demodulator is to perform tracking by producing from a correlation pulse signal an error signal having a time discrimination characteristic. The spread spectrum demodulator generates from the correlation pulse signal an error signal whose level varies in response to a phase difference between a pseudonoise signal contained in a received signal and a reference pseudonoise signal. A clock in synchronism with the received signal is generated from this error signal, thereby demodulating the received signal.

Abstract: There is disclosed a local oscillating device useful for a communication system where frequency conversion is implemented to data signals received in a burst manner, particularly for INMARSAT STC-C (International Maritime Satellite Organization Standard - C) system.

Abstract: A digital phase detector circuit is designed for particular application with a phase-locked loop voltage controlled oscillator system for synchronizing the MFM synchronization pulses on a floppy disk with the operation of the computer in which the disk is used. A classical Type 4 digital phase detector is employed, to which a bistable latch is added. The latch is set upon coincidence of reference and data pulses applied to the phase detector within a pre-established time interval or window. The output of the phase detector then is utilized only when the output of the latch indicates such coincidence; so that erroneous control signals are not supplied through the loop whenever data pulses fail to occur in adjacent time frames or windows.

Abstract: In order to coherently demodulate an incoming multi-phase PSK analog signal irrespective of large frequency deviation, an automatic frequency feedback loop is provided. An analog baseband signal is generated by multiplying the IF analog signal by a local signal and then is converted into the corresponding digital baseband signal. A multiplier multiplies the digital baseband signal by another local signal. The output of the multiplier is further multiplied and then applied to a plurality of single-tuned filters which are arranged in parallel and have tuning frequencies each different from an adjacent frequency by a predetermined frequency interval. Each of the plurality of single-tuned filters generates a signal for use in carrier recovery, a frequency error signal and a correlation coefficient. Subsequently, one of the plurality of single-tuned filters is selected in a manner wherein the maximum value is detected among the correlation coefficients.

Abstract: A receiving circuit is designed for an MSK (Minimum Shift Keying) receiver and a QPSK (Quadrature Phase Shift Keying) receiver. The circuit provides a synchronous state determining device and a control voltage sweeping device for sweeping the output of a voltage oscillator. In the asynchronous state, a switch is turned off for interrupting a reproducing phase error signal so that the output of the voltage oscillator may be swept for causing the synchronous state. Then, the sweeping operation is stopped and the switch is turned on for controlling the voltage of the voltage controlled oscillator so that the low-frequency error component is removed from the phase error signal of the demodulating circuit. This results in implementing the simply-arranged demodulating circuit which keeps the proper demodulating performance against the shifted carrier frequency without any degrade and demodulates the input signal stably if the signal has a low C/N ratio.

Abstract: A digital receiver, such as "C-QUAM" receiver (10), has phase error correction. In another form, a software program may be executed by a conventional digital signal processor to also implement phase error correction. A digital input signal is demodulated to form an in-phase and a quadrature component. The in-phase and quadrature components are processed by a digital envelope detector (24) to form a composite signal containing left and right audio channel information. The in-phase component and composite signal are both processed by a reciprocal cosine estimator (28) and a quadrature channel circuit (38) to provide a difference signal also containing left and right audio channel information. The difference signal is input to phase error correction circuitry (16, 22, 26) to estimate a phase error of the digital input signal. The estimated phase error is then used to correct an actual phase error of the digital input signal during demodulation.

Abstract: In a differential-detection demodulator circuit, a PSK modulated signal is compared with a locally oscillated signal to obtain a phase difference between the two signals, whereupon the phase difference is demodulated. A phase detector circuit of the digital type outputs the phase difference signal. The digital phase comparator circuit compares plural reference signals, which give predetermined delays to the locally oscillated signals having carrier frequencies, with the inputted modulated signals. Preferably, a pulse signal having a phase difference between the inputted modulated signal and the locally oscillated signal is produced, and the pulse width of this pulse signal is measured by a counter. By digitalizing the entire phase comparator, it is possible to realize demodulation with low electrical power consumption and simple circuit construction.

Abstract: A phase error processor interfaces a proportionate phase detector to a digital loop filter in a high frequency phase-locked loop (PLL). The PLL receives a high frequency stream of NRZI encoded data, which contains a variable density of data signal transitions. A phase detector in the PLL generates proportionate phase error information in the form of a phase error pulse signal PD1 and a reference pulse signal PD2 for each data transition in the incoming data s The phase error processor, using a "decimation" technique, integrates the proportionate phase error information from just one pair of adjacent positive and negative data transitions during each period of N clock cycles if the number of input data transitions which occur during that time period exceeds the expected minimum, otherwise the phase error processor passes no phase error information. The selection of window width is based on the coding scheme of the incoming data stream.