Having Field Effect Transistor Patents (Class 330/253)
  • Patent number: 11223333
    Abstract: Provided is an amplification circuit for amplifying an input signal. The amplification circuit includes an input stage including an input matching circuit that receives the input signal and an input attenuation circuit that attenuates a gain for the input signal outside an operating frequency band of the amplification circuit, a transistor that amplifies the input signal provided from the input stage, and an output stage including an output matching circuit that receives a signal amplified by the transistor and an output attenuation circuit that attenuates the gain for the input signal outside the operating frequency band of the amplification circuit, and the input attenuation circuit includes a first resistor and a second resistor that are connected to a ground voltage, a first passive element connected between the input matching circuit and the second resistor, and a second passive element connected between the first passive element and the first resistor.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: January 11, 2022
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Woojin Chang, Seong-Il Kim, Sang-Heung Lee, Jongmin Lee
  • Patent number: 11190140
    Abstract: A wide voltage trans-impedance amplifier includes a first P-channel metal oxide semiconductor (PMOS) transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a first bias voltage VB1, a second bias voltage VB2, a third bias voltage VB3, a first N-channel metal oxide semiconductor (NMOS) transistor NM1, and a second NMOS transistor NM2. A common-gate amplifier detects a change of an input voltage, and a negative feedback is constructed by injecting a current into a current mirror to achieve a low input impedance. The trans-impedance amplifier uses a common-gate amplifier to monitor an input voltage and uses a current mirror to perform the transconductance enhancement on an input transistor, while ensuring a relatively high loop gain.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: November 30, 2021
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Chao Chen, Jun Yang, Xinning Liu
  • Patent number: 11183982
    Abstract: Methods and systems are described for receiving, at an input differential branch pair, a set of input signals, and responsively generating a first differential current, receiving, at an input of an offset voltage branch pair, an offset voltage control signal, and responsively generating a second differential current, supplementing a high-frequency component of the second differential current by injecting a high-pass filtered version of the set of input signals into the input of the offset voltage branch pair using a high-pass filter, and generating an output differential current based on the first and second differential currents using an amplifier stage connected to the input differential branch pair and the offset voltage branch pair.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: November 23, 2021
    Assignee: KANDOU LABS, S.A.
    Inventor: Armin Tajalli
  • Patent number: 11183983
    Abstract: Methods and systems are described that include a differential amplifier driving an active load circuit, the active load circuit having a pair of load transistors and a high-frequency gain stage providing high frequency peaking for the active load circuit according to a frequency response characteristic determined in part by resistive values of a pair of active resistors connected, respectively, to gates of the pair of load transistors, and a bias circuit configured to stabilize the high frequency peaking of the high-frequency gain stage by generating a process-and-temperature variation (PVT)-dependent control voltage at gates of the active resistors to stabilize the resistive values of the pair of active resistors to account for PVT-dependent voltages at the gates of the pair of load transistors.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: November 23, 2021
    Assignee: KANDOU LABS, S.A.
    Inventors: Armin Tajalli, Christoph Walter
  • Patent number: 11159086
    Abstract: A buck voltage converter is disclosed. The buck voltage generator includes a controller configured to generate one or more pulse width modulation (PWM) signals, and a plurality of serially connected switches configured to receive the PWM signals and to generate an output voltage signal at an output terminal based on the received PWM signals. The output voltage signal has an average voltage corresponding with a duty cycle of the PWM signals, a first switch of the plurality of serially connected switches has a first breakdown voltage and a second switch of the plurality of serially connected switches has a second breakdown voltage, and the first breakdown voltage is less than the second breakdown voltage.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: October 26, 2021
    Assignee: Empower Semiconductor, Inc.
    Inventor: Timothy Alan Phillips
  • Patent number: 11159135
    Abstract: A circuit (e.g., implemented as part of a controller area network (CAN) bus receiver includes a pre-amplifier stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output of the pre-amplifier stage, and the second input is coupled to the second output of the pre-amplifier stage. The comparator includes an input differential transistor pair, a second pair of transistors coupled to the input differential transistor pair in a cascode configuration, and a push-pull output stage coupled to the second pair of transistors.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: October 26, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Richard Sterling Broughton, Vijayalakshmi Devarajan, Richard Edwin Hubbard
  • Patent number: 11147973
    Abstract: A circuit for charge-balanced current-controlled stimulation. The circuit includes a transistor differential pair, a first current mirror, a second current mirror, and a third current mirror. The transistor differential pair includes a first differential input node, a second differential input node, a first differential output node, a second differential output node, and a common node. The transistor differential pair is configured to generate a first differential current that passes through the first differential output node and a second differential current that passes through the second differential output node. The first current mirror is configured to generate a first mirrored current based on the first differential current. The second current mirror is configured to generate a second mirrored current based on the second differential current. The third current mirror is configured to generate a third mirrored current based on the first mirrored current.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: October 19, 2021
    Assignees: AMIRKABIR UNIVERSITY OF TECHNOLOGY
    Inventor: Mohammad Mahdi Ahmadi
  • Patent number: 11128273
    Abstract: A variable-gain amplifier includes two amplification and attenuation branches, and first and a second resistive elements that are coupled between the two branches. Each branch includes a voltage follower stage and a configurable amplification stage. The voltage follower stages are intended to receive a differential signal and are configured to deliver, via the first resistive element, an intermediate differential current signal. The amplification stages are intended to receive the intermediate differential current signal and a digital control word, and are configured to deliver, via the second resistive element, an output differential voltage signal depending on the value of the digital control word.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: September 21, 2021
    Assignee: STMicroelectronics SA
    Inventor: Renald Boulestin
  • Patent number: 11114036
    Abstract: A scan driver includes a plurality of circuit stages, each circuit stage including a first input part configured to transfer a carry signal to a first node in response to a first clock signal, a second input part configured to transfer the first clock signal to a second node in response to a signal of the first node, a first output part configured to transfer a third clock signal to an output terminal in response to a signal of the second node, a holding part configured to maintain a signal of a third node response to a second clock signal, and a second output part configured to transfer a signal of the third node to the output terminal in response to the second clock signal.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: September 7, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Boyoung Chung, Youngwan Seo, Dongwoo Kim, Yeonkyung Kim, Chong Chul Chai
  • Patent number: 11108981
    Abstract: A compact ADC circuit can include one or more comparators, and a serial DAC (Digital-to-Analog) circuit that provides a signal to the comparator (or comparators). In addition, the ADC circuit can include a serial DAC redistribution sequencer that can provide a plurality of signals as input to the serial DAC circuit and is subject to a redistribution cycle and which receives as input a signal from a data multiplexer whose input connects electronically to an output of the comparator. The circuit can further include an ADC code register that provides an ADC output that connects electronically to the output of the comparator and the input to the data multiplexer. Shared logic circuitry for sharing common logic between pixels can be included, wherein the shared logic circuitry connects electronically to the data multiplexer and the ADC code register, wherein the shared logic circuitry promotes area and power savings for the pixel detector circuit.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: August 31, 2021
    Assignee: FERMI RESEARCH ALLIANCE, LLC
    Inventors: Tom Zimmerman, Grzegorz Deptuch, Farah Fahim
  • Patent number: 11095261
    Abstract: An amplification interface includes a drain of a first FET connected to a first node, a drain of a second FET connected to a second node, and sources of the first and second FETs connected to a third node. First and second bias-current generators are connected to the first and second nodes. A third FET is connected between the third node and a reference voltage. A regulation circuit drives the gate of the third FET to regulate the common mode of the voltage at the first node and the voltage at the second node to a desired value. A current generator applies a correction current to the first and/or second node. A differential current integrator has a first and second inputs connected to the second and first nodes. The integrator supplies a voltage representing the integral of the difference between the currents received at the second and first inputs.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: August 17, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Calogero Marco Ippolito, Michele Vaiana, Angelo Recchia
  • Patent number: 11088667
    Abstract: Various embodiments of the present technology comprise a method and apparatus for a dual mode operational amplifier. According to various embodiments, the operational amplifier functions as both a fully-differential amplifier and a single-ended amplifier. The operational amplifier may comprise additional transistors that function as switches, which can be selectively operated according to a desired mode.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: August 10, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Tsutomu Murata
  • Patent number: 11082012
    Abstract: An amplifier includes input transconductors that receive an input signal, the input signal having a voltage swing. A supply side current mirror generates a gate voltage as a function of input signal voltage and current sources that provide a bias current of the input transconductors as a function of the gate voltage to maintain a constant bias current across the voltage swing of the input signal. Resistors average source voltages of the transconductance-cancelling transconductors to provide an average source voltage and apply the average source voltage to wells of input devices of the transconductance-cancelling transconductors to reduce back bias effect. The input devices are laid out in a same well and have a common centroid to cancel out process mismatches. A first I-DAC trims an offset of first transconductors, and a second I-DAC trims an offset of second transconductors to attain low offsets across a rail-to-rail input common mode range.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: August 3, 2021
    Assignee: Cirrus Logic, Inc.
    Inventors: Vaibhav Pandey, Bhoodev Kumar
  • Patent number: 11075610
    Abstract: A receiver includes an amplifier that receives a transmission signal and amplifies a first voltage difference between the transmission signal and a reference signal to generate a first output signal and a second output signal at a first node and a second node. An equalizer is provided, which is connected to the first node and the second node and receives the transmission signal. The equalizer compensates a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: July 27, 2021
    Inventors: Seunghwan Hong, Yoo-Chang Sung, Wangsoo Kim, Indal Song
  • Patent number: 11073854
    Abstract: Embodiments described herein present a new LDO design that eliminates the need for the sleep bias circuitry included in other systems. Further, the new LDO design can be biased with a small fraction of the operating current enabling the LDO to wake up substantially faster than previous LDO designs that include separate sleep circuitry. In some cases, the LDO can instantly (or faster than other LDOs) transition from a sleep mode to an operating mode enabling improved operation compared to prior LDOs. Furthermore, the new LDO design maintains a non-breakdown voltage across the transistors reducing the need to enter sleep mode to prevent transistors of the LDO from entering a breakdown region.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: July 27, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventor: Bo Zhou
  • Patent number: 11062842
    Abstract: A device includes a first inductor and a second inductor. The first inductor has a first inductive coupling profile. A first circuit component is coupled to the first inductor. A second inductor has a second inductive coupling profile. A second circuit component coupled to the second inductor.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: July 13, 2021
    Assignee: X-Card Holdings, LLC
    Inventor: Mark A. Cox
  • Patent number: 11050386
    Abstract: An inverse pseudo fully-differential amplifier having a common-mode feedback control circuit and a method for maintaining a stable output common-mode level are provided. The inverse pseudo fully-differential amplifier includes the pseudo fully-differential operation circuit and a common-mode feedback control circuit. The pseudo fully-differential operation circuit includes inverter amplifiers (2) and (3). The inverter amplifiers (2) and (3) respectively have a first feedback control terminal and a second feedback control terminal. Input terminals of the common-mode feedback control circuit are respectively connected with output terminals of the inverter amplifier (2) and (3), and are configured to detect common-mode output voltages of the inverter amplifier (2) and (3).
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: June 29, 2021
    Assignee: BEIJING SMARTCHiP MICROELECTRONICS TECHNOLOGY COMP
    Inventors: Yubo Wang, Xiaoke Tang, Yi Hu, Dejian Li, Jin Shao, Xi Feng, Wennan Feng, Jiali Hou
  • Patent number: 11043948
    Abstract: A bandwidth enhanced amplifier for high frequency CML To CMOS conversion is disclosed. In some implementations, an improved CML to CMOS converter includes a differential amplifier having a first and a second input transistors, and a first and a second load transistors. The first input transistor is coupled in series with the first load transistor, and the second input transistor is coupled in series with the second load transistor. The improved CML to CMOS converter further includes a first capacitor and a second capacitor. The first capacitor is coupled directly between a gate of the first input transistor and a gate of the first load transistor.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 22, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Suresh Naidu Lekkala, Sajin Mohamad
  • Patent number: 11031916
    Abstract: A circuit includes a first common mode amplifier including a first input, a second input, and a first output. The first common mode amplifier comprises a first plurality of self-biased differential amplifiers. The circuit also includes a second common mode amplifier including a third input, a fourth input, and a second output, The third input is connected to the second input and the fourth input is connected to the first input. The second common amplifier comprises a second plurality of self-biased differential amplifiers. The circuit further includes a first gain amplifier including a fifth input and a sixth input and a second gain amplifier including a seventh input and an eighth input. The first output is connected to the fifth and eight inputs and the second output is connected to the sixth and seventh inputs.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: June 8, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Niko Bako, Narayanan Seetharaman
  • Patent number: 11025214
    Abstract: Described is high-current drive class AB operational trans-conductance amplifier (OTA) output that can operate under low supply voltages (e.g., below 0.9 V) while maintaining desired functionality (e.g., reliable startup behavior, well-defined biasing currents, phase margins for improved stability) over a broad range of process, voltage, and temperature variations. The class AB OTA comprises a pre-amplifier stage, and a differential OTA output stage coupled to the pre-amplifier stage, wherein the differential OTA output stage comprises at least four folded cascode transistors.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventor: Krzysztof Dufrene
  • Patent number: 11005434
    Abstract: An output stage circuit of an operational amplifier, the operational amplifier, and a signal amplifying method applied to the operational amplifier are provided. The output stage circuit includes an inverting circuit and a compensation module. The inverting circuit is electrically connected to a gain stage circuit of the operational amplifier. The inverting circuit generates an output signal of the operational amplifier. The compensation module includes a first compensation circuit, including a first current providing path and a first suppression activation circuit. The first current providing path provides a first compensation current. The first suppression activation circuit conducts the first compensation current to the inverting circuit if a first compensation condition related to a first gain stage signal generated by the gain stage circuit is satisfied. Variation of the output signal is suppressed because of the first compensation current.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: May 11, 2021
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventor: De-Shiou Tseng
  • Patent number: 10996698
    Abstract: A circuit that includes an input stage circuit and an output stage circuit is provided. The input stage circuit includes a differential pair circuit and two output current mirror circuits. The differential pair circuit operates according to a first voltage source to receive a first and a second input voltages and generate a first and a second output currents. The two output current mirror circuits operate according to a second voltage source to generate a first current mirror output current fed to an input stage output node according to the first output current and generate a second current mirror output current flowed from the input stage output node according to the second output current. The output stage circuit operates according to the second voltage source to receive an input voltage from the input stage output node to generate an output voltage.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: May 4, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Ya-Hsuan Sung
  • Patent number: 10985750
    Abstract: An integrated circuit includes at least one differential pair of transistors, a bias current generator that is configured to generate a bias current on a bias node that is coupled to a source terminal of each transistor of said differential pair by a respective resistive element. A compensation current generator is configured to generate a compensation current in one of the two resistive elements so as to compensate for a difference between actual values of the threshold voltages of the transistors of said differential pair.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: April 20, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Yohan Joly, Vincent Binet, Michel Cuenca
  • Patent number: 10971080
    Abstract: The differential difference amplifier circuit includes a differential input stage circuit, a loading stage circuit coupled to the differential input stage circuit, and an output stage circuit coupled to the loading stage circuit. The output stage circuit is configured to generate an output signal. The differential input stage circuit includes a first differential pair having a first transconductance and a second differential pair having a second transconductance. The first differential pair is biased by a first current source and receives a first input signal and the output signal. The second differential pair is biased by a second current source and receives a second input signal and the output signal. At least one of the first transconductance and the second transconductance is adjusted according to the image data.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: April 6, 2021
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Chih-Hsien Chou, Po-Yu Tseng, Jhih-Siou Cheng
  • Patent number: 10965252
    Abstract: Modern modulator drivers must be capable of delivering a large output voltage into a tens of ohms modulator, while minimizing the amount of distortion added by the driver. The driver should deliver the output voltage without exceeding a maximum distortion while minimizing the DC power consumption. Accordingly, a modulator driver includes a final stage amplifier with auxiliary transistors that turn on when the conventional differential pair of transistors approaches their maximum voltage of the linear region of their transfer function, thereby providing a more linear transfer function, in particular at large input voltages.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: March 30, 2021
    Inventors: Ariel Leonardo Vera Villarroel, Mohamed Megahed Mabrouk Megahed, Alexander Rylyakov
  • Patent number: 10958225
    Abstract: An amplifier circuit includes a first input unit, a second input unit, a first current supply unit, and a second current supply unit. The first input unit changes a voltage level of a first output node based on a first input signal. The second input unit changes a voltage level of a second output node based on a second input signal. The first current supply unit supplies a first current to the first output node based on a voltage level of the first output node and boosts the voltage level of the first output node for a predetermined time when the voltage level of the first output node is changed. The second current supply unit supplies a second current to the second output node based on the voltage level of the first output node.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: March 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Kyu Dong Hwang
  • Patent number: 10951185
    Abstract: A differential amplifier circuit has a first current circuit comprising a first transistor and a second transistor, and to flow a current depending on a voltage of a first input signal, a second current circuit comprising a third transistor and a fourth transistor, and to flow a current depending on a voltage of a second input signal, a fifth transistor comprising a gate connected to a gate and the drain of the second transistor, and to flow a current that is M times greater than the current flowing between the drain and the source of the second transistor, and a sixth transistor comprising a gate connected to a gate and the drain of the fourth transistor and cascode-connected to the first transistor, and to flow a current that is N times greater than the current flowing between the drain and the source of the fourth transistor.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: March 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinsuke Fujii
  • Patent number: 10951252
    Abstract: Methods and devices addressing design of reconfigurable wideband LNAs to meet stringent gain, noise figure, and linearity requirements with multiple gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements, such as 5G NR radios. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: March 16, 2021
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Patent number: 10943536
    Abstract: Provided are an external compensation circuit and method, and display device in the field of display techniques. The external compensation circuit includes a regulation sub-circuit that may collect a driving current loaded to a light-emitting unit and a reference current from a reference current source, and regulate potentials at two nodes connected to a compensation sub-circuit according to the collected current, to enable the compensation sub-circuit to calibrate a data signal to be input to a pixel circuit according to a potential difference between the two nodes.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: March 9, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tangxiang Wang, Chen Song
  • Patent number: 10938364
    Abstract: A vacuum tube subwoofer extraction circuit system includes: a front-end circuit; and a vacuum tube subwoofer extraction circuit connected to the front-end circuit, the vacuum tube subwoofer extraction circuit including: a small signal amplification vacuum tube for receiving an input signal from the front-end circuit and outputting an audio signal; and a passive filtering circuit connected to the small signal amplification vacuum tube and adapted to perform a filtering process on the audio signal so as to output a filtered signal, wherein the front-end circuit includes a switch power circuit for providing low voltage to the vacuum tube subwoofer extraction circuit, wherein the small signal amplification vacuum tube does not have gain effect on the input signal.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: March 2, 2021
    Assignee: ECHOWELL ELECTRONIC CO., LTD.
    Inventor: Hsi-Hsien Chen
  • Patent number: 10931240
    Abstract: An amplifier circuit can be configured to receive a differential input signal having a common mode component that can extend to at least one power supply rail for the amplifier circuit. The amplifier circuit can include an input stage, such as having a first differential transistor pair, and the input stage can receive the differential input signal and in response conduct a differential first current to a cascode output stage. The cascode output stage can include or use a cascode control signal that is adjusted in response to the differential input signal. The cascode control signal can be independent of a transconductance of the first differential transistor pair. In an example, the amplifier circuit includes a slew boost circuit configured to source or sink current at an output of the amplifier based on a magnitude and polarity of the differential input signal.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: February 23, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventor: Asit Shankar
  • Patent number: 10924066
    Abstract: An operational amplifier is disclosed. The operational amplifier activates/couples either a first or a second differential pair of transistors to an input based on the input voltage. The first and second pair of transistors are each biased with a current having a first portion that is constant with temperature and a second portion that is proportional to temperature. By adjusting the ratios of the first and second portions, the transconductance of each differential pair may be made relatively constant with temperature. Each differential pair is coupled to a trim current source that is adjusted to reduce the voltage offset at each output. The resulting voltage offset for the operational amplifier is relatively constant over a range of input voltages and has temperature coefficient unaffected by the trimming process.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: February 16, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Anca Purdila, Constantin Pasoi
  • Patent number: 10917046
    Abstract: Provided is an electronic circuit including a resonant circuit configured to output a resonance voltage having a resonance frequency to a first node, and an oscillation circuit configured to output an oscillation voltage having a level changed according to a first current and a second current based on the resonance voltage received from the first node, wherein the first current is delivered between a first voltage supply terminal and a second node in a first time period, the second current is delivered between the second node and a second voltage supply terminal in a second time period, and a sum of a length of the first time period and a length of the second time period corresponds to the resonance frequency.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: February 9, 2021
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Ja Yol Lee
  • Patent number: 10917058
    Abstract: A servo-amplifier includes a first bipolar transistor, a second bipolar transistor, a cascode transistor, and a bias transistor. The second bipolar transistor includes an emitter terminal that is connected to an emitter terminal of the first bipolar transistor to form a differential amplifier. The cascode transistor includes a source terminal that is connected to a collector terminal of the first bipolar transistor. The bias transistor is coupled to the first bipolar transistor, the second bipolar transistor and the cascode transistor. The bias transistor is configured to generate a bias voltage to drive a gate terminal of the cascode transistor based on a voltage at a base terminal of the first bipolar transistor and a voltage at a base terminal of the second bipolar transistor. As a result, neither of the bipolar transistors enters a saturation region during transient or steady state operation.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: February 9, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aalok Dyuti Saha, Bhaskar Ramachandran
  • Patent number: 10903804
    Abstract: Disclosed examples include differential amplifier circuits and variable neutralization circuits for providing an adjustable neutralization impedance between an amplifier input node and an amplifier output node, including neutralization impedance T circuits with first and second impedance elements in series between the amplifier input and output, and a third impedance element, including a first terminal connected to a node between the first and second impedance elements, and a second terminal connected to a transistor. The transistor operates according to a control signal to control the neutralization impedance between the amplifier input node and the amplifier output node.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: January 26, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Krishnanshu Dandu, Brian P. Ginsburg
  • Patent number: 10897236
    Abstract: Wideband signal buffers that can be employed for mmWave (millimeter wave) communication are disclosed. One example signal buffer comprises a variable gain amplifier (VGA) that receives two control words and outputs a feedback signal, wherein both an amplitude and a phase of the feedback signal are based on the two control words and on a bias voltage; and a matching network comprising a first inductor that outputs the bias voltage, a second inductor, and a third inductor that receives the feedback signal from the VGA, and wherein the first, second, and third inductors are magnetically coupled to each other, wherein the signal buffer is configured to receive a RF (Radio Frequency) input and to generate a RF output from the RF input based on a transfer function of the signal buffer, wherein the transfer function is based at least in part on the feedback signal.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: January 19, 2021
    Assignee: Apple Inc.
    Inventors: Chuanzhao Yu, Kurt Hausmann, Stephen Rector
  • Patent number: 10897250
    Abstract: Systems and methods for mitigating occurrences of dynamic avalanche events are presented. An electrical system may include a gate-drive unit electrically coupled to a semiconductor switching device and used to drive the switching device by applying a voltage to a gate terminal of the switching device. The electrical system may also include a controller that indicates the switching device to turn off and determines system parameters in response to the switching device turning-off. The controller may determine an intermediate gate voltage based at least in part on the system parameters and may modify the gate-drive unit configuration to apply the appropriate intermediate gate voltage to the gate terminal. The controller may additionally modify the gate-drive unit configuration to apply a turn-off voltage at the gate terminal subsequent to the application of the intermediate gate voltage.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: January 19, 2021
    Assignee: TRANSPORTATION IP HOLDINGS, LLC
    Inventors: Thomas Alois Zoels, Henry Todd Young, Jason Daniel Kuttenkuler
  • Patent number: 10892717
    Abstract: A circuit includes a first common-source amplifier configured to receive a first voltage at a first gate node and output a first current to a first drain node in accordance with a first source voltage at a first source node; a second common-source amplifier configured to receive a second voltage at a second gate node and output a second current to a second drain node in accordance with a second source voltage at a second source node; a first diode-connected device configured to couple the first source node to a DC (direct current) node; a second diode-connected device configured to couple the second source node to the DC node; and a source-degenerating resistor inserted between the first source node and the second source node.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: January 12, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10886881
    Abstract: An amplifier comprises eight transistors: the first coupled to a linked node and to a positive output node, the second coupled to the linked node and to a negative output node, the third coupled to the positive output node and a common potential, the fourth coupled to the negative output node and the common potential, the fifth coupled to a battery node, the sixth coupled to the fifth transistor and to the positive output node, the seventh coupled to the battery node, and the eighth coupled to the seventh transistor and to the negative output node. The amplifier also includes a charge pump to convert the battery voltage to an increased voltage on the linked node. The charge pump includes capacitors and operates at a lower frequency in lower power mode and a higher frequency in higher power mode to increase power provided to the linked node.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: January 5, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yinglai Xia, Shailendra Kumar Baranwal, Junmin Jiang, Yogesh Kumar Ramadass
  • Patent number: 10873303
    Abstract: An amplifier includes an input stage. The input stage includes a differential pair and a load circuit. The differential pair includes a first transistor and a second transistor. The first transistor and the second transistor are configured to amplify a received differential signal. The load circuit connects the differential pair to a reference voltage. The load circuit is configured to vary in resistance in inverse proportion to the transconductance of the first transistor and the second transistor.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: December 22, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Neil Gibson
  • Patent number: 10868506
    Abstract: The present disclosure describes exemplary line drivers for use in an exemplary wireline transmission device. In some situations, the exemplary line drivers are electrically connected to a wireline communication channel to transmit information. The exemplary line drivers prevent charge sharing with the wireline communication channel. The exemplary line drivers disclosed herein charge various circuit nodes to various logical values, such as a logical zero or a logical one, to prevent charge sharing with the wireline communication channel.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: December 15, 2020
    Inventors: Xin Jie Wang, Dirk Pfaff
  • Patent number: 10860045
    Abstract: A voltage regulator having a buffer circuit and method for operating the same is disclosed. A voltage regulator having a buffer circuit includes an input stage coupled to receive an input voltage and an output stage configured to provide an output signal on an output node. The output stage includes first and second output transistors coupled to the output node. The circuit further includes a buffer stage coupled between the input and output stages. The buffer stage includes a first buffer transistor having a gate terminal coupled to the input stage and a source terminal coupled to a gate terminal of the first output transistor. The circuit further includes a first current mirror coupled to the first buffer transistor, and a second current mirror coupled to the first current mirror, the second current mirror including the second output transistor.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: December 8, 2020
    Assignee: Apple Inc.
    Inventor: Bin Huang
  • Patent number: 10862470
    Abstract: A comparator circuitry includes an input pair circuit, a load circuit, and a compensation circuit. The input pair circuit is configured to compare a first input signal with a second input signal, in order to control a first bias current. The load circuit is coupled to the input pair circuit, and is configured to output an output signal having a first level from a first output terminal of the load circuit in response to the first bias current. The compensation circuit is coupled to the input pair circuit and the load circuit, and is configured to drain a compensation current from the first output terminal to a voltage source during the load circuit generates the output signal having a first level, in which the voltage source is configured to provide a voltage having a second level.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: December 8, 2020
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ting-Hao Wang, Hao-Che Hsu, Pei-Ju Lin
  • Patent number: 10862475
    Abstract: Disclosed herein are switching or other active field-effect transistor (FET) configurations that implement independently controlled main-auxiliary branch designs. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FET devices in parallel with a plurality of auxiliary FET devices. The circuit assembly can include a plurality of gate bias networks where each controls one or more of the main FET devices. The circuit assembly includes a second plurality of gate bias networks that each controls one or more of the auxiliary FET devices.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: December 8, 2020
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, Jerod F. Mason, David Scott Whitefield, Paul T. DiCarlo
  • Patent number: 10862445
    Abstract: Disclosed herein is an amplification circuit that outputs an output signal formed by amplifying a differential signal between a first input terminal and a second input terminal using an operating amplifier and a plurality of resistors, the amplification circuit including an adjustment circuit configured to adjust a frequency property of the output signal for an in-phase alternating current signal input between the first input terminal and the second input terminal. The adjustment circuit is connected to one input terminal of the first input terminal and the second input terminal through one or more resistors, the adjustment circuit includes a capacitor part whose capacitance is set to be variable, and the adjustment is realized through variable setting of the capacitance of the capacitor part.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 8, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Hisashi Sugie
  • Patent number: 10855383
    Abstract: A system and a method for calibrating an antenna using trim bits and non-volatile memory is disclosed. In one aspect, an apparatus includes a power amplifier configured to at least amplify the output signal of the first antenna. The power amplifier includes multiple stages. The apparatus further includes a trim control circuit configured to adjust a bias of one of the stages of the power amplifier, using trim bits from non-volatile memory. The trim control circuit is further configured to scale the bias of one of the plurality of stages of the power amplifier by an integer between 0 and 2n?1 corresponding to a binary number formed by the first plurality of trim bits, wherein n corresponds to the number of trim bits.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: December 1, 2020
    Assignee: ANOKIWAVE, INC.
    Inventors: Robert McMorrow, Vipul Jain, Mikhail Shirokov, Kevin B. Greene, Susanne A. Paul, Shamsun Nahar
  • Patent number: 10855236
    Abstract: Systems, methods and apparatus for practical realization of an integrated circuit comprising a stack of transistors operating as an RF amplifier are described. As stack height is increased, capacitance values of gate capacitors used to provide a desired distribution of an RF voltage at the output of the amplifier across the stack may decrease to values approaching parasitic/stray capacitance values present in the integrated circuit which may render the practical realization of the integrated circuit difficult. Coupling of an RF gate voltage at the gate of one transistor of the stack to a gate of a different transistor of the stack can allow for an increase in the capacitance value of the gate capacitor of the different transistor for obtaining an RF voltage at the gate of the different transistor according to the desired distribution.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: December 1, 2020
    Assignee: pSemi Corporation
    Inventor: Jaroslaw Adamski
  • Patent number: 10855306
    Abstract: A digital-to-analog converter (DAC) capable of operating in radio frequency (RF) with linear output, low distortion, low power consumption, and input data independence. The DAC includes switch drivers and output switches driven by the switch drivers. The switch drivers include pairs of outputs, and positive feedback circuitries coupled between respective pairs of outputs. The output switches are arranged between a first current source configured to push current to the DAC's outputs and a second current source configured to pull current from the DAC's outputs. Different output switches are configured to push current to and pull current from the DAC's outputs in accordance with rising edges and falling edges, respectively.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: December 1, 2020
    Assignee: MEDIATEK Singapore Pte. Ltd.
    Inventor: Nathan Egan
  • Patent number: 10833641
    Abstract: Various embodiments of the present technology may comprise methods and apparatus for an amplifier circuit. Methods and apparatus for an amplifier circuit according to various aspects of the present invention may comprise a first cross-connect circuit configured to receive an input signal at an input terminal and transmit the input signal to an input stage circuit. The amplifier circuit may further comprise a second cross-connect circuit connected between the input stage circuit and an output stage circuit, and a voltage adjustment circuit connected to the input stage circuit. Each cross-connect circuit may comprise a plurality of switches.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 10, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Akinobu Onishi
  • Patent number: 10826463
    Abstract: An example of a signal switch includes a first transistor coupled between first and second nodes, a plurality of second transistors coupled in series between the first and second nodes, in parallel with the first transistor, a third transistor coupled between the first node and a third node, and a plurality of fourth transistors coupled in series between the first and third nodes, in parallel with the third transistor. The signal switch further includes a first shunt path including a first shunt transistor and a first inductor connected in series between a reference node and a first connection point between two of the plurality of second transistors, and a second shunt path including a second shunt transistor and a second inductor connected in series between the reference node and a second connection point between two of the plurality of fourth transistors.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: November 3, 2020
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Nuttapong Srirattana