Having Field Effect Transistor Patents (Class 330/253)
  • Patent number: 11990878
    Abstract: A differential amplifying unit includes a first input transistor and a second input transistor forming a differential pair, and a first tail current source and a second tail current source. An output stage includes a first output transistor and a second output transistor that can be driven by an output of the differential amplifying unit. A controller performs control such that during startup, a load is driven by the first tail current source and the first output transistor, and such that after startup, the load is driven by the first tail current source, the second tail current source, the first output transistor, and the second output transistor.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: May 21, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Tomokazu Kojima
  • Patent number: 11978499
    Abstract: The present disclosure provides a comparator and a decision feedback equalization circuit. The comparator includes: a first sampling circuit provided with an output terminal, and configured to generate, under the control of a first control signal and a clock signal, a first differential signal according to a signal to be compared and a first reference signal; a second sampling circuit provided with an output terminal connected to the output terminal of the first sampling circuit, and configured to generate, under the control of a second control signal and the clock signal, a second differential signal according to the signal to be compared and a second reference signal, where the first reference signal is larger than the second reference signal.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: May 7, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yinchuan Gu
  • Patent number: 11979979
    Abstract: Methods, systems, and devices for crosstalk cancellation for signal lines are described. In some examples, a device (e.g., a host device or a memory device) may generate a first signal and may invert the first signal to obtain an inverted first signal. The device may obtain a second signal based on attenuating a first range of frequencies of the inverted first signal and a second range of frequencies of the inverted first signal, where the first range of frequencies is below a first threshold frequency and the second range of frequencies is above a second threshold frequency that is greater than the first threshold frequency. The device may transmit the first signal via a first signal line of a set of signal lines and the second signal line via a second signal line of the set of signal lines.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: May 7, 2024
    Assignee: Micron Technology, Inc.
    Inventors: M. Ataul Karim, David K. Ovard, Aparna U. Limaye, Timothy M. Hollis
  • Patent number: 11977402
    Abstract: A semiconductor device includes a low power fast differential transconductor, which provides an output current as a function of a difference between a reference potential input and a feedback potential input. The transconductance increases as an absolute value of the difference between the reference potential and the feedback potential increases. The transconductor includes a reference input stage to receive the reference potential and a reference load coupled in series with the reference input stage. The transconductor includes a feedback input stage to receive the feedback potential and a feedback load coupled in series with the feedback input stage. The transconductor further includes a current limiting component that is configured to control a total current through the reference input stage and the feedback input stage.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: May 7, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Anmol Sharma
  • Patent number: 11942900
    Abstract: A compensated amplifier for use in a power converter controller. The compensated amplifier comprises a first amplifier, a second amplifier, an integrator, and an arithmetic operator. The first amplifier coupled to receive a sensed signal and a reference signal and configured to generate a first error signal in response to the sensed signal and the reference signal. The second amplifier coupled to the first amplifier and configured to generate a second error signal in response to the sensed signal and the reference signal. The integrator coupled to the first amplifier and configured to generate an integrated error signal in response to the first error signal. The arithmetic operator coupled to the integrator and to the second amplifier, wherein the arithmetic operator is configured to generate a control signal in response to the integrated error signal and the second error signal.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: March 26, 2024
    Assignee: POWER INTEGRATIONS, INC.
    Inventor: Arthur B. Odell
  • Patent number: 11923809
    Abstract: A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. An output passive network can further generate a flat-phase response between dual resonances of operation.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Jong Seok Park, Yanjie Wang, Stefano Pellerano, Christopher D. Hull
  • Patent number: 11916516
    Abstract: Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Nitin Agarwal, Kunal Karanjkar, Venkata Ramanan
  • Patent number: 11906992
    Abstract: A distributed power management circuit is provided. In embodiments disclosed herein, the distributed power management circuit can achieve multiple performance enhancing objectives simultaneously. More specifically, the distributed power management circuit can be configured to switch a modulated voltage from one voltage level to another within a very short switching window, reduce in-rush current required for switching the modulated voltage, and minimize a ripple in the modulated voltage, all at same time. As a result, the distributed power management circuit can be provided in a wireless device (e.g., smartphone) to enable very fast voltage switching across a wide modulation bandwidth (e.g., 400 MHz) with reduced power consumption and voltage distortion.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: February 20, 2024
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat
  • Patent number: 11894815
    Abstract: A power amplifier includes: a power amplification circuit and a linearity compensation circuit; and herein the linearity compensation circuit is connected between a transistor amplification circuit and a biasing circuit of the power amplification circuit, to linearly compensate a nonlinear distortion of the power amplification circuit.
    Type: Grant
    Filed: December 26, 2020
    Date of Patent: February 6, 2024
    Assignee: SMARTER MICROELECTRONICS (GUANG ZHOU) CO., LTD.
    Inventors: Qiang Su, Ping Li
  • Patent number: 11888447
    Abstract: A circuit includes an operational amplifier having: a positive input; a negative input; an operational amplifier output; a differential front end; a positive channel (PCH) input stage; a negative channel (NCH) input stage; and an output stage. The operational amplifier also includes a current limit circuit coupled to an output of the output stage and including: an output current sense voltage circuit having an output configured to provide an output current sense voltage; an indirect current feedback circuit coupled to the output of the output current sense voltage circuit, the indirect current feedback circuit having an output configured to provide an output current feedback sense voltage responsive to the output current sense voltage; and control circuitry coupled to the indirect current feedback circuit and configured vary a resistance between the output stage output and ground responsive to a difference between the output current feedback sense voltage and a reference voltage.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: January 30, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Munaf Hussain Shaik, Srinivas Kumar Pulijala, Vadim Valerievich Ivanov
  • Patent number: 11876496
    Abstract: Differential input circuits employ protection transistors and feedback paths to limit the differential voltage applied to input transistors. In an example arrangement, a differential input voltage is applied to terminals of the protection transistors, and current paths couple the respective protection transistors to control terminals of the input transistors, respectively. A control terminal drive voltage source is coupled to the control terminals of the input protection transistors to control the drive voltage applied to those terminals. Feedback paths, one for each of the input transistors, control voltages applied to the control terminals of the input transistors, maintaining the input differential voltage at a relatively low level and defined by the product of a specified current value and a specified resistance value.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: January 16, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vadim Valerievich Ivanov, Srinivas Kumar Pulijala
  • Patent number: 11862058
    Abstract: Provided is an output amplifier having: a push-pull output-stage formed by first and second output-stage transistors; and a detection circuit detecting an abnormal output current output by the output amplifier and including: a coupling circuit, generating first and second currents mirroring current flowing in the first output-stage transistor and third and fourth currents mirroring current flowing in the second output-stage transistor, coupling the first and third currents at a first output node, outputting a first voltage at the first output node, coupling the second and fourth currents at a second output node, and outputting a second voltage at the second output node; and a determination circuit, outputting a determination signal indicating normality of an output current based on the first and second voltages. The coupling circuit generates the first to fourth currents. In the reference state, the third current >the first current, the second current >the fourth current.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: January 2, 2024
    Assignee: LAPIS Technology Co., Ltd.
    Inventor: Hiroshi Tsuchi
  • Patent number: 11857328
    Abstract: An active electrode has an electrode for sensing an electric potential and generating an input signal, and a shield placed near the electrode but being electric insulated from the electrode. An integrated amplifier (10) has an input connected to the at least one electrode for receiving the input signal, and providing a buffered path outputting a buffered output signal. The shield being connected to the output of the integrated amplifier to actively drive the electrical potential of the shield, thereby providing an active shielding of the electrode. The buffered path includes a first mixer (11) in front of the integrated amplifier for frequency shifting the input signal from a basic frequency range to a higher frequency range, and a second mixer (12) on the output of the integrated amplifier for frequency shifting the amplified signal from the higher frequency range back to the basic frequency range. The active electrode may be used for recording EEG signals.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: January 2, 2024
    Assignee: T&W Engineering A/S
    Inventors: Preben Kidmose, Xiong Zhou, Soren Kilsgaard, Qiang Li
  • Patent number: 11848646
    Abstract: An amplifier circuit includes a voltage-to-current conversion circuit and a current-to-voltage conversion circuit. The voltage-to-current conversion circuit generates a current signal according to an input voltage signal, and includes an operational transconductance amplifier (OTA) used to output the current signal at an output port of the OTA. The current-to-voltage conversion circuit generates an output voltage signal according to the current signal, and includes a linear amplifier (LA), wherein an input port of the LA is coupled to the output port of the OTA, and the output voltage signal is derived from an output signal at an output port of the LA.
    Type: Grant
    Filed: July 5, 2021
    Date of Patent: December 19, 2023
    Assignee: MEDIATEK INC.
    Inventors: Shih-Hsiung Chien, Sung-Han Wen, Kuan-Ta Chen
  • Patent number: 11838000
    Abstract: Aspects of the present disclosure provide a method for regulating an integration current of a sensing amplifier. The sensing amplifier includes a first input transistor and a second input transistor, wherein a source of the first input transistor and a source of the second input transistor are coupled to a source node. The method includes pulling a current from or sourcing the current to the source node, measuring the integration current, comparing the measured integration current with a reference signal, and adjusting the current pulled from or sourced to the source node based on the comparison.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: December 5, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Todd Morgan Rasmus, Shih-Wei Chou
  • Patent number: 11838666
    Abstract: A compact ADC circuit can include one or more comparators, and a serial DAC (Digital-to-Analog) circuit that provides a signal to the comparator (or comparators). In addition, the ADC circuit can include a serial DAC redistribution sequencer that can provide a plurality of signals as input to the serial DAC circuit and is subject to a redistribution cycle and which receives as input a signal from a data multiplexer whose input connects electronically to an output of the comparator. The circuit can further include an ADC code register that provides an ADC output that connects electronically to the output of the comparator and the input to the data multiplexer. Shared logic circuitry for sharing common logic between pixels can be included, wherein the shared logic circuitry connects electronically to the data multiplexer and the ADC code register, wherein the shared logic circuitry promotes area and power savings for the pixel detector circuit.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: December 5, 2023
    Assignee: Fermi Research Alliance, LLC
    Inventors: Farah Fahim, Tom Zimmerman, Grzegorz Deptuch
  • Patent number: 11823486
    Abstract: A method of temperature compensation in an optical-fingerprint detection system includes acquiring a first reading associated with one or more pixels of an array. The first reading is a baseline reading. The method further includes acquiring a second reading associated with the one or more pixels of the array. The second reading includes the baseline plus a signal. Producing a temperature compensated signal reading by subtracting the first reading from the second reading. The array is an optical-fingerprint array, and each pixel of the array is coupled to a readout circuit via a pixel switch. The method includes row-based and frame-based schemes and a blind pixel scheme. Readout circuit improvements including multiplexed analog front-end (AFE), charge magnifier with column charge offset compensation and a low-noise gate driver circuit are provided.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: November 21, 2023
    Assignee: Apple Inc.
    Inventors: Christoph H. Krah, Mohammad Yeke Yazdandoost
  • Patent number: 11817838
    Abstract: An electronic amplification-interface circuit includes a differential-current reading circuit having a first input terminal and a second input terminal. The differential-current reading circuit includes a continuous-time sigma-delta conversion circuit formed by an integrator-and-adder module generating an output signal that is coupled to an input of a multilevel-quantizer circuit configured to output a multilevel quantized signal. The integrator-and-adder module includes a differential current-integrator circuit configured to output a voltage proportional to an integral of a difference between currents received at the first and second input terminals. A digital-to-analog converter, driven by a respective reference current, receives and converts the multilevel quantized signal into a differential analog feedback signal. The integrator-and-adder module adds the differential analog feedback signal to the differential signal formed at the first and second input terminals.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: November 14, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Calogero Marco Ippolito, Michele Vaiana
  • Patent number: 11811438
    Abstract: Systems and methods for magnitude and phase trimming are provided. In one aspect, a radio frequency (RF) trimmer circuit includes an input terminal configured to receive an RF signal, an output terminal configured to output the RF signal, a control input configured to receive a control signal, at least one impedance element, and at least one transistor configured to selectively connect the impedance element onto a path between the input and output terminals. The selectively connecting the impedance element controls at least one of a magnitude trim and a phase trim of the RF signal.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: November 7, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: John Jackson Nisbet, Hassan Sarbishaei, Guillaume Alexandre Blin
  • Patent number: 11811373
    Abstract: An active load stage converts a first input current and a second input current into a first voltage and a second voltage. A driver amplifier operates upon receiving the first voltage and the second voltage from the active load stage, and outputs a current to an output terminal. The driver amplifier has a first transistor and a second transistor connected in series between a first reference potential terminal and a second reference potential terminal. The first transistor receives the first voltage at a gate and passes a first current, and the second transistor receives the second voltage at a gate and passes a second current. A minimum selector provides feedback to the first voltage and the second voltage such that an absolute value of each of the first current and the second current becomes more than or equal to a quiescent current of the driver amplifier.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 7, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Takayuki Nakai
  • Patent number: 11791779
    Abstract: A method for use in an analog circuit having a plurality of differential pairs of elements, wherein for each pair of the plurality of differential pairs of elements, the elements of the pair are designed to match but may have mismatch that induces error. The method includes, for each pair of at least two pairs of the plurality of differential pairs of elements: spectrally separating the mismatch-induced error of the pair from mismatch-induced error of a remainder of the plurality of differential pairs of elements, monitoring, by an analog-to-digital converter (ADC), an output of the analog circuit, and analyzing the monitored output to measure the mismatch-induced error of the pair.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: October 17, 2023
    Assignee: Cirrus Logic, Inc.
    Inventors: Ramin Zanbaghi, John L. Melanson, Edmund M. Schneider
  • Patent number: 11791787
    Abstract: A differential amplifier circuit generates a first current and a second current having a current difference obtained by amplifying a voltage difference between an input voltage and a reference voltage. An output stage supplies current proportional to the first current to an output node. A current conversion circuit discharges current proportional to the second current from the output node. After connecting the output node to a ground node in response to a reset signal, a latch circuit disconnects the output node from the ground node after reset cancellation. Thereafter, when voltage at the output node rises from the ground voltage in a case where a level relationship between the input voltage and the reference voltage is reversed from a reset cancellation time point, the latch circuit fixes the voltage at the output node to a power supply voltage by a positive feedback latch operation.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: October 17, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tomokazu Kojima, Yuhei Morimoto
  • Patent number: 11791791
    Abstract: A receiver includes an amplifier that receives a transmission signal and amplifies a first voltage difference between the transmission signal and a reference signal to generate a first output signal and a second output signal at a first node and a second node. An equalizer is provided, which is connected to the first node and the second node and receives the transmission signal. The equalizer compensates a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: October 17, 2023
    Inventors: Seunghwan Hong, Yoo-Chang Sung, Wangsoo Kim, Indal Song
  • Patent number: 11784618
    Abstract: A circuit including an amplifier having an input and an output. The circuit also includes a current-to-voltage amplifier having an input. The circuit further includes a current mirror coupled between the output of the amplifier and the input of the current-to-voltage amplifier. The current mirror is configured to chop current flowing through the first current mirror.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: October 10, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Shang-Yuan Chuang
  • Patent number: 11784616
    Abstract: Power amplifier apparatuses and techniques for optimizing the design of power amplifiers are disclosed. In one aspect, a method for optimizing a power amplifier includes selecting a circuit topology for the power amplifier. The circuit topology includes one or more photoconductive switches and an impedance matching network including one or more parameter values representative of the impedance matching network or the photoconductive switches that can be adjusted. The method further includes selecting one or more optimization goals for the impedance matching network and the one or more photoconductive switches, and adjusting the one or more parameter values according to the one or more optimization goals. The one or more optimization goals include an efficiency at a particular power output.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: October 10, 2023
    Assignees: LAWRENCE LIVERMORE NATIONAL SECURITY, LLC, SOCAL SIMULATIONS, LLC
    Inventors: Tammy Chang, Adam Conway, Victor Valeryevich Khitrov, Lars Voss, Benjamin Fasenfest, Peter Asbeck
  • Patent number: 11777461
    Abstract: According to an embodiment of the disclosure, a series or source feedback is provided to a solid-state power amplifier to achieve improved amplifier output power, good impedance match, and low voltage standing wave ratio (VSWR). In an embodiment, an inductive element is coupled to the source of the power amplifier transistor to serve as a series or source feedback for the transistor. In an embodiment, a high-impedance microstrip is provided as an inductive element coupled to the source of the transistor. In an embodiment, a series or source feedback is provided to each amplifier in a multistage amplifier circuit. In an embodiment, a greater series or source feedback is provided at a later stage of a multistage amplifier circuit, whereas a smaller series or source feedback is provided at an earlier stage of the multistage amplifier circuit.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: October 3, 2023
    Assignee: ENGIN-IC, INC.
    Inventor: Stephen R. Nelson
  • Patent number: 11764759
    Abstract: An apparatus includes a comparator. The comparator includes first and second pregain stages, and a switch network coupled to the first and second pregain stages. A plurality of switches in the switch network are operable to provide a feedback path around at least one of the first and second pregain stages. The comparator further includes a latch coupled to the second pregain stage.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: September 19, 2023
    Assignee: Silicon Laboratories Inc.
    Inventors: Sheng Jue Peh, Obaida Mohammed Khaled Abu Hilal
  • Patent number: 11750160
    Abstract: A differential residue amplifier fits between Analog-to-Digital Converter (ADC) stages. Switched-Capacitor Common-Mode Feedback circuits determine voltage shifts. An AC-coupled input network uses switched capacitors to shift upward voltages of the differential inputs to the residue amplifier to apply to an upper pair of p-channel differential transistors with sources connected to the power supply. The AC-coupled input network also shifts downward in voltage the differential inputs to the residue amplifier to apply to a lower pair of n-channel differential transistors with grounded sources. The drains of the p-channel differential transistors connect to differential outputs through p-channel cascode transistors. N-channel cascode transistors connect the drains of the n-channel differential transistors to the differential outputs. The drains of differential transistors can be input to differential amplifiers to drive the gates of the cascode transistors for gain boosting.
    Type: Grant
    Filed: April 9, 2022
    Date of Patent: September 5, 2023
    Assignee: Caelus Technologies Limited
    Inventor: Chi Fung Lok
  • Patent number: 11736080
    Abstract: A voltage-to-current converter circuit comprises an amplifier, a resistor, first and second feedback circuits, and an output circuit. The amplifier is configured to receive a differential input voltage signal. The resistor is coupled between first and second nodes of the amplifier. The first feedback circuit is coupled to a third node of the amplifier, provides feedback to the first and second nodes when the value of the input voltage signal is in a first range, and is turned off otherwise. The second feedback circuit is coupled to a fourth node of the amplifier, provides feedback to the first and second nodes when the value of the input voltage signal is in a second range different from the first range, and is turned off otherwise. The output circuit produces a differential current output signal having a value according to the value of the input voltage signal.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: August 22, 2023
    Assignee: NEWRACOM, INC
    Inventor: Seong-Sik Myoung
  • Patent number: 11736071
    Abstract: Certain aspects of the present disclosure provide an amplifier. The amplifier generally includes an amplifier core circuit configured to amplify a radio frequency signal and having a first output and a second output; a transformer coupled to the amplifier core circuit, the transformer having a primary winding and a secondary winding, the primary winding being coupled to the first output and the second output of the amplifier core circuit, the secondary winding being coupled to an output node of the amplifier; and a variable resistance circuit coupled in parallel with the primary winding.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: August 22, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Ayush Mittal, Sreenivasa Mallia, Arpit Gupta, Krishnaswamy Thiagarajan, Bhushan Shanti Asuri
  • Patent number: 11722107
    Abstract: Class-D amplifier circuits provide operation with low-distortion zero crossings outside of a unipolar power supply voltage range. The amplifiers include a first H-bridge driver circuit and a second H-bridge driver circuit. The class-D amplifier circuits also include a control circuit having an input for receiving an input signal to be reproduced by the class-D amplifier circuit. The control circuit has outputs coupled to inputs of the first and second H-bridge drivers, and includes one or more modulators. The control circuit selects between actively operating a selected one of the driver circuits or both, according to the signal to be reproduced, while setting an unselected driver circuit to turn either a high-side switch or a low-side switch of the unselected one of the first driver circuit or the second driver circuit fully on for at least some cycles of the one or more modulators.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: August 8, 2023
    Assignee: CIRRUS LOGIC, INC.
    Inventors: John L. Melanson, Cory J. Peterson, Chandra Prakash, Ramin Zanbaghi, Eric Kimball
  • Patent number: 11722108
    Abstract: Described herein is a fully-differential preamplifier comprising an input differential pair, an output current load, and a current source. The current source is coupled between the input differential pair and a low voltage rail and configured to control whether the fully-differential preamplifier is operating in a first mode or a second mode, wherein the preamplifier draws more current when operating in the second mode compared to when operating in the first mode. The input differential pair is coupled between the output current load and the current source. The output current load is coupled between a high voltage rail and the input differential pair. The input differential pair comprise positive and negative inputs of the fully-differential preamplifier. Nodes where the input differential pair and the output current load are coupled to one another comprise positive and negative outputs of the fully-differential preamplifier.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: August 8, 2023
    Assignee: Pacesetter, Inc.
    Inventors: Eric C. Labbe, Benjamin T. Persson
  • Patent number: 11713998
    Abstract: According to one aspect, an ambient-light sensor includes a photodiode configured to generate an electrical signal according to an ambient light, a capacitive-feedback transimpedance amplifier connected at its input to the photodiode for receiving a signal generated by the photodiode and for generating as an output an amplified signal from the signal generated by the photodiode, and an auto-zero switch at the input of the capacitive-feedback transimpedance amplifier. The ambient-light sensor further includes a control circuit including a bootstrap circuit configured to receive an initial positive- or zero-voltage logic control signal, and then generate, from this initial logic control signal, an adapted logic control signal having a first positive voltage level and a second negative voltage control level for controlling the auto-zero switch.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: August 1, 2023
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Nicolas Moeneclaey, Sri Ram Gupta, Sarika Kushwaha
  • Patent number: 11705084
    Abstract: A high-speed buffer amplifier includes an input stage including a first channel coupled to receive differential inputs and a second channel coupled to receive the differential inputs; a middle stage including a first current source coupled to receive outputs of the second channel and electrically connected to power, a second current source coupled to receive outputs of the first channel and electrically connected to ground, and a floating current source electrically connected between the first current source and the second current source; and an output stage coupled to the middle stage to generate an output voltage. A shunt circuit is electrically connected between the first current source and the second current source, and configured to bypass the floating current source.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: July 18, 2023
    Assignee: Himax Technologies Limited
    Inventor: Chih-Wen Lu
  • Patent number: 11706060
    Abstract: A serial receiver combines continuous-time equalization, analog interleaving, and discrete-time gain for rapid, efficient data reception and quantization of a serial, continuous-time signal. A continuous-time equalizer equalizes a received signal. A number N of time-interleaved analog samplers sample the equalized continuous-time signal to provide N streams of analog samples transitioning at rate reduced by 1/N relative to the received signal. A set of N discrete-time variable-gain amplifiers amplify respective streams of analog samples. A quantizer then quantizes the amplified streams of analog samples to produce a digital signal.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: July 18, 2023
    Assignee: Rambus Inc.
    Inventors: Haidang Lin, Charles Walter Boecker, Masum Hossain
  • Patent number: 11677591
    Abstract: A bidirectional isolated communication circuit and method for a differential signal. The circuit comprises a first detection circuit used for receiving a first differential pair from a first direction, converting the first differential pair into a first level signal, and inhibiting common-mode interference; a second detection circuit used for receiving a second differential pair from a second direction, converting the second differential pair into a second level signal, and inhibiting common-mode interference; an isolation adjustment circuit used for being provided between the first detection circuit and the second detection circuit and performing communication isolation; and a watchdog circuit used for being awoken according to the first differential pair and/or the second differential pair, and enabling the bidirectional isolated communication circuit to enter from a small current working mode to a normal working mode to perform communication isolation.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: June 13, 2023
    Assignee: SAIC MOTOR CORPORATION LIMITED
    Inventors: Kewei Lu, Ji Li, Wendi Chen, Meiai Lin, Yang Li
  • Patent number: 11677359
    Abstract: A circuit which reuses current to synthesize a negative impedance includes a current source circuit, a differential circuit, and a negative impedance conversion circuit. The current source circuit is arranged to provide at least one predetermined current, wherein the current source circuit has a first connection port and a second connection port, and the first connection port of the current source is coupled to a first reference voltage. The differential circuit is coupled between the second connection port of the current source circuit and a second reference voltage, and is arranged to receive a differential input pair and generate a differential output pair, wherein the differential circuit has a differential output port. The negative impedance conversion circuit is coupled between the differential output port and a third reference voltage, wherein the third reference voltage is different from the first reference voltage.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: June 13, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventor: Kuan-Chang Tsung
  • Patent number: 11677370
    Abstract: A circuit (e.g., implemented as part of a controller area network (CAN) bus receiver includes a pre-amplifier stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output of the pre-amplifier stage, and the second input is coupled to the second output of the pre-amplifier stage. The comparator includes an input differential transistor pair, a second pair of transistors coupled to the input differential transistor pair in a cascode configuration, and a push-pull output stage coupled to the second pair of transistors.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: June 13, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Richard Sterling Broughton, Vijayalakshmi Devarajan, Richard Edwin Hubbard
  • Patent number: 11662447
    Abstract: A variable-current trans-impedance amplifier (TIA) for an ultrasound device is described. The TIA may be coupled to an ultrasonic transducer to amplify an output signal of the ultrasonic transducer representing an ultrasound signal received by the ultrasonic transducer. During acquisition of the ultrasound signal by the ultrasonic transducer, one or more current sources in the TIA may be varied. The variable-current trans-impedance amplifier may include multiple stages, including a first stage having N-P transistor pairs configured to receive an input signal and produce a single-ended amplified signal.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 30, 2023
    Assignee: BFLY OPERATIONS, INC.
    Inventors: Kailiang Chen, Chao Chen, Keith G. Fife
  • Patent number: 11658623
    Abstract: The present disclosure relates to Class D amplifier circuitry comprising a mode controller configured to dynamically adjust an operational switching mode of the Class D amplifier over a range between a Class AD mode and a Class BD mode.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: May 23, 2023
    Assignee: Cirrus Logic, Inc.
    Inventors: John Paul Lesso, Toru Ido
  • Patent number: 11658628
    Abstract: A semiconductor device includes an equalizer for receiving a first signal and outputting a second signal that has been adjusted to compensate for attenuation of the first signal. A filter is connected to the output terminal of the equalizer. A cancellation circuit operates to cancel a DC offset in the output of the equalizer. A processing circuit is configured to control the cancellation circuit to cancel the DC offset according to an output from the filter. The processing circuit sets a time constant for the filter to a first value to permit the cancellation circuit to cancel the DC offset when the equalizer is in a first state, and then sets the time constant to a second value when the equalizer is set to a second state to permit the cancellation circuit to cancel the DC offset when the equalizer is in the second state.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: May 23, 2023
    Assignee: Kioxia Corporation
    Inventor: Takaya Yamamoto
  • Patent number: 11658625
    Abstract: A preamplifier circuit comprises a first pair of transistors and a second pair of transistors having current flow paths therethrough coupled at first and second output nodes and providing first and second current flow lines intermediate a supply node and ground. The two pairs of transistors comprise: first and second input transistors located intermediate the outputs nodes and one of the supply node and ground providing respective input nodes, first and second load transistors intermediate the output nodes and the other of the supply node and ground. The load transistors have control terminals capacitively coupled to the other of the supply node and ground and a reset switch arrangement is provided periodically activatable to short the first output node, the second output node as well as the control terminals of the first load transistor and the second load transistor.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: May 23, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventor: Roberto Modaffari
  • Patent number: 11646706
    Abstract: A common-source differential power amplifier comprises a compensation circuit, which comprises a first and a second compensation transistors and two signal terminals, a source and a drain of the first compensation transistor are short-circuited and connected to a gate of the second compensation transistor and one signal terminal of the compensation circuit, the source and the drain of the second compensation transistor are short-circuited and connected to the gate of the first compensation transistor and the other signal terminal of the compensation circuit, the two signal terminals of the compensation circuit are further respectively connected to two differential signal input terminals of the common-source differential power amplifier directly or via a capacitor, where the first and second compensation transistors in the same compensation circuit are both NMOS transistors or both PMOS transistors. An electronic device including the power amplifier is also disclosed.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: May 9, 2023
    Assignee: Hangzhou Geo-chip Technology Co., Ltd.
    Inventor: Sy-Chyuan Hwu
  • Patent number: 11640799
    Abstract: A display apparatus includes a pixel portion in which a plurality of pixels are arranged, the plurality of pixels being connected to scan lines and data lines; a data driver configured to transmit a data signal to a source output line; a data distributer configured to selectively connect the source output line to the data lines; and a latch portion arranged between the data distributer and the pixel portion, wherein the latch portion includes a plurality of latches connected to at least one of data lines excluding a data line, from among the data lines, connected to the source output line by the data distributer at a timing at which a scan signal is transmitted to the scan lines.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: May 2, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventor: Sanghyun Lim
  • Patent number: 11626841
    Abstract: A circuit is provided. In some examples, the circuit includes a first transistor having a gate and a drain coupled together and a current source coupled to the drain of the first transistor. A second transistor has a drain coupled to a source of the first transistor. A third transistor has a gate coupled to the gate of the first transistor. A fourth transistor has a drain coupled to a source of the third transistor and a gate of the fourth transistor is coupled to a gate of the second transistor. In some examples, the third transistor is configured to limit a first current between the third transistor and the fourth transistor based on an output voltage.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: April 11, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nitin Agarwal, Aniruddha Roy
  • Patent number: 11619958
    Abstract: A front-end module comprises a bias network including a current mirror, a junction temperature sensor, an n-bit analog-to-digital converter, an n-bit current source bank configured to automatically set reference current levels for one or more operating temperature regions, and a power amplifier. The bias network, junction temperature sensor, n-bit analog-to-digital converter, n-bit current source bank, and power amplifier are integrated on a first semiconductor die.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: April 4, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventor: Bang Li Liang
  • Patent number: 11614760
    Abstract: A front-end module comprises a low-dropout (LDO) voltage regulator, a reference current generator, and a power amplifier. The LDO voltage regulator, reference current generator, and power amplifier are integrated on a first semiconductor die.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: March 28, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: Bang Li Liang, Yasser Khairat Soliman, Adrian John Bergsma, Haoran Yu, Hassan Sarbishaei
  • Patent number: 11611321
    Abstract: The present disclosure relates to an electronic device comprising a pair of first transistors, each first transistor being coupled to a first node by a conduction terminal, a pair of second transistors, each second transistor being coupled to a second node by a conduction terminal, and a third transistor coupling the first and second nodes, the control terminal of the third transistor being coupled to the output of an operational amplifier, the operational amplifier being coupled, at its input, to the first node and to a node of application of a reference voltage.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: March 21, 2023
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Philippe Pignolo, Vincent Rabary
  • Patent number: 11601309
    Abstract: A multi-stage continuous time linear equalizer (CTLE) with a reconfigurable inductor scheme is disclosed. The multi-stage CTLE comprises a first stage transformer-based inductive peaking and a second stage resistive load. The first stage transformer-based inductive peaking is configured to control high frequency peaking and set a peak frequency value to a desired value by using a coarse equalization mechanism. The stage resistive load configured to provide tuneable equalization and low frequency fine equalization by using a fine equalization mechanism.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: March 7, 2023
    Inventors: Suhas Rattan, Ivaylo Avramov
  • Patent number: 11581893
    Abstract: A high-frequency high-linear input buffer includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a signal panning unit. A gate terminal of the first MOS transistor is used as an input terminal of the buffer. A current input terminal of the first MOS transistor is connected to a current output terminal of the second MOS transistor. A current output terminal of the first MOS transistor is connected to a current input terminal of the third MOS transistor. A current input terminal of the second MOS transistor is connected to a gate terminal of the third MOS transistor. An input terminal of the signal panning unit is connected to an input terminal of the buffer. An output terminal of the signal panning unit is connected to a gate terminal of the second MOS transistor. An output terminal of the third MOS transistor is connected to ground.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: February 14, 2023
    Assignee: Chengdu Sino Microelectronics Technology Co., Ltd.
    Inventors: Jinda Yang, Yuanjun Cen, Jian Luo