Having Field Effect Transistor Patents (Class 330/253)
  • Patent number: 11611321
    Abstract: The present disclosure relates to an electronic device comprising a pair of first transistors, each first transistor being coupled to a first node by a conduction terminal, a pair of second transistors, each second transistor being coupled to a second node by a conduction terminal, and a third transistor coupling the first and second nodes, the control terminal of the third transistor being coupled to the output of an operational amplifier, the operational amplifier being coupled, at its input, to the first node and to a node of application of a reference voltage.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: March 21, 2023
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Philippe Pignolo, Vincent Rabary
  • Patent number: 11601309
    Abstract: A multi-stage continuous time linear equalizer (CTLE) with a reconfigurable inductor scheme is disclosed. The multi-stage CTLE comprises a first stage transformer-based inductive peaking and a second stage resistive load. The first stage transformer-based inductive peaking is configured to control high frequency peaking and set a peak frequency value to a desired value by using a coarse equalization mechanism. The stage resistive load configured to provide tuneable equalization and low frequency fine equalization by using a fine equalization mechanism.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: March 7, 2023
    Inventors: Suhas Rattan, Ivaylo Avramov
  • Patent number: 11581893
    Abstract: A high-frequency high-linear input buffer includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a signal panning unit. A gate terminal of the first MOS transistor is used as an input terminal of the buffer. A current input terminal of the first MOS transistor is connected to a current output terminal of the second MOS transistor. A current output terminal of the first MOS transistor is connected to a current input terminal of the third MOS transistor. A current input terminal of the second MOS transistor is connected to a gate terminal of the third MOS transistor. An input terminal of the signal panning unit is connected to an input terminal of the buffer. An output terminal of the signal panning unit is connected to a gate terminal of the second MOS transistor. An output terminal of the third MOS transistor is connected to ground.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: February 14, 2023
    Assignee: Chengdu Sino Microelectronics Technology Co., Ltd.
    Inventors: Jinda Yang, Yuanjun Cen, Jian Luo
  • Patent number: 11581644
    Abstract: An apparatus is disclosed for bidirectional amplification with phase-shifting. In example implementations, an apparatus includes a phase shifter with a bidirectional amplifier. The bidirectional amplifier includes a first transistor coupled between a first plus node and a second minus node, a second transistor coupled between a first minus node and a second plus node, a third transistor coupled between the first plus node and the second minus node, and a fourth transistor coupled between the first minus node and the second plus node. The bidirectional amplifier also includes a fifth transistor coupled between the first plus node and the second plus node, a sixth transistor coupled between the first minus node and the second minus node, a seventh transistor coupled between the first plus node and the second plus node, and an eighth transistor coupled between the first minus node and the second minus node.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: February 14, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Xinmin Yu, Lai Kan Leung
  • Patent number: 11575356
    Abstract: A fully-differential two-stage operational amplifier circuit is provided, and it includes a first-stage amplification circuit, a second-stage amplification circuit, a common-mode signal acquisition circuit, a common-mode feedback circuit and a bias circuit. The first-stage amplification circuit has a telescopic structure and receives differential input signals INP and INN. The second-stage amplification circuit has a common-source structure and outputs differential output signals OUTP and OUTN. The common-mode signal acquisition circuit receives differential output signals, and outputs an operational amplifier output common-mode signal VCMO. The common-mode feedback circuit outputs common-mode feedback signals VB1 and VB2 to the first-stage amplifier circuit and the second-stage amplifier circuit respectively; The bias circuit outputs a bias voltage VB3 to the first-stage amplifier circuit, and outputs bias voltages VB4 and VB5 to the first-stage amplifier circuit respectively.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: February 7, 2023
    Assignee: AMPLIPHY TECHNOLOGIES LIMITED
    Inventors: Tianlin Cao, Hehong Zou, Zhiyang Wang, Sheng Huang, Qi Chen
  • Patent number: 11539334
    Abstract: Methods and devices used in mobile receiver front end to support multiple paths and multiple frequency bands are described. The presented devices and methods provide benefits of scalability, frequency band agility, as well as size reduction by using one low noise amplifier per simultaneous outputs. Based on the disclosed teachings, variable gain amplification of multiband signals is also presented.
    Type: Grant
    Filed: March 14, 2021
    Date of Patent: December 27, 2022
    Assignee: pSemi Corporation
    Inventor: Jonathan James Klaren
  • Patent number: 11538432
    Abstract: An input stage configured to differentially amplify an input signal and an output signal, a first current mirror and a second current mirror configured to receive a differential current from the input stage, an output stage including first and second output transistors, respectively including a gate connected to the first and second current mirrors, and a slew rate compensation circuit configured to (i) mirror a comparison current generated by comparing a voltage of a first input signal with a voltage of a second input signal, and (ii) provide the mirrored comparison current to the gate of the first or second output transistor.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: December 27, 2022
    Assignee: DB HiTek, Co., Ltd.
    Inventors: Hak Jin Jung, Eun Ji Youn, Pyung Sik Ma
  • Patent number: 11514975
    Abstract: An amplifier with an input stage comprising: a first current mirror; a first input differential pair; a first current source; a second current source; a second input differential pair, wherein the first input differential pair and the second input differential pair receive a reference voltage; a second current mirror; and a voltage control transmission circuit. An extra current path in the first current mirror is formed and a current flowing through the extra current path flows through the second current mirror to a ground when the reference voltage is higher than a first predetermined value. Also, an extra current path in the second current mirror is formed and a current flowing through the extra current path in the second current mirror flows to the first current mirror when the reference voltage is lower than a second predetermined value.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: November 29, 2022
    Assignee: Elite Semiconductor Microelectronics Technology Inc.
    Inventor: Shu-Han Nien
  • Patent number: 11503239
    Abstract: An electronic circuit is provided. The electronic circuit includes a first current generating circuit configured to output a first operating current based on a first operating voltage; and an input circuit configured to: receive a first current corresponding to a first input voltage and a second current corresponding to a second input voltage, wherein the first current and the second current are based on the first operating current; receive a third current and a fourth current that are generated based on the first operating voltage; and generate a fifth current corresponding to the second input voltage based on a second operating current. The electronic circuit is configured to generate an output voltage that is associated with a difference between the first input voltage and the second input voltage based on the second current, the fourth current and the fifth current, and the fourth current corresponds to the third current.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: November 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunyool Kang, Yunhwan Jung, Heesung Chae, Sukki Yoon, Yongjun Cho
  • Patent number: 11502651
    Abstract: An overvoltage protection and gain bootstrap circuit of a power amplifier includes a power amplification transistor, and a diode reversely connected with a gate of the power amplification transistor. A negative electrode of the diode is connected with the gate of the power transistor, and a positive electrode of the diode is connected with a constant voltage source, such that a function of overvoltage protection and gain bootstrap of the circuit is realized by controlling a turn-on state of the diode. By adding a diode device to the circuit, gate-drain overvoltage protection for the power amplification transistor can be provided, and the gain of the amplifier can be improved before power compression, thereby improving linearity of the power amplifier. The structure of the circuit can be simple, with reduced occupied area hardware cost.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: November 15, 2022
    Assignee: SMARTER MICROELECTRONICS (GUANG ZHOU) CO., LTD.
    Inventors: Zhenfei Peng, Qiang Su, Kun Xiang
  • Patent number: 11489500
    Abstract: A differential amplifier of a memory controller may include: an amplification stage configured to amplify input differential signals to generate intermediate differential signals; a control circuit configured to control slew rates for the intermediate differential signals; and an output circuit configured to selectively perform one or more switching operations according to the intermediate differential signals to generate output differential signals.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: November 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Keun Jin Chang
  • Patent number: 11482976
    Abstract: A differential amplifier includes first and second MOS transistors of a first conductivity type which constitute a differential input circuit, a bias current source which supplies a bias current to the first and second MOS transistors, and a third MOS transistor of the first conductivity type provided between the bias current source and the first and second MOS transistors and constituted to limit a back-gate voltage of the first and second MOS transistors.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: October 25, 2022
    Assignee: ABLIC INC.
    Inventor: Yoshiomi Shiina
  • Patent number: 11469726
    Abstract: A dual-drive power amplifier (PA) where the PA core includes a differential pair of transistors M1 and M2 that are driven by a coupling network having two transmission-line couplers, where a first transmission line section of a coupler is configured to transmit an input signal Vin through to drive a gate of the opposite transistor, while the second transmission line section is grounded at one end and coupled with the first transmission line section such that a coupled portion ?Vin of the input signal Vin drives the source terminal of a corresponding transistor. The arrangement of the coupling network allows the source terminals to be driven below ground potential. Embodiments disclosed here further provide an input matching network, a driver, an inter-stage matching network, and an output network for practical implementation of the PA core.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: October 11, 2022
    Assignee: Georgia Tech Research Corporation
    Inventors: Edgar Felipe Garay, Hua Wang
  • Patent number: 11462991
    Abstract: Some aspects of the present disclosure provide for a circuit. In at least some examples, the circuit includes an integrator coupled between a first node and a second node and a filter coupled between the second node and a third node. The circuit further includes a buffer coupled between the third node and a fourth node and a first switch coupled between the fourth node and a fifth node. The circuit further includes a first capacitor coupled between the fifth node and a ground node, a first resistor comprising a first terminal coupled to the fifth node and a second terminal, a second switch coupled between the second terminal of the first resistor and the ground node.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: October 4, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jiancong Ruan, Runqin Tan, Zhicheng Hu
  • Patent number: 11456710
    Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: September 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: An-Hsun Lo, Wen-Sheng Chen, En-Hsiang Yeh, Tzu-Jin Yeh
  • Patent number: 11451194
    Abstract: A low noise amplifier that may include a first input port, a second input port, a first capacitor, a second capacitor, a first variable capacitor, a second variable capacitor, an inductor, a bias circuit, a tuning circuit, a first output circuit having a first output, a second output circuit having a second output; wherein the first input port is electrically coupled to a first end of the second variable capacitor, to a first end of the first capacitor, to an input of the first output circuit, and to a first port of the inductor; wherein the second input port is electrically coupled to a second end of the first variable capacitor, to a second end of the second capacitor, to an input of the second output circuit, and to a second port of the inductor; wherein a first port of the first varactor is electrically coupled to a second end of the first capacitor; wherein a second port of the second varactor is electrically coupled to a first end of the second capacitor; wherein the bias circuit is configured to supply
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: September 20, 2022
    Assignee: DSP Group Ltd.
    Inventor: Sergey Anderson
  • Patent number: 11451146
    Abstract: A DC-DC converter according to an embodiment is a DC-DC converter for generating an output voltage VOUT according to a reference voltage VREF, and includes a fully differential amplifier that outputs a first differential output signal and a second differential output signal according to a differential input using the reference voltage VREF and the output voltage VOUT, a pulse width modulation signal generation circuit that generates a pulse width modulation signal based on the first differential output signal Vout1 and the second differential output signal Vout2, and a driver that outputs a driving signal obtained by waveform-shaping the pulse width modulation signal.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: September 20, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Kenichi Wakasugi
  • Patent number: 11444631
    Abstract: Amplifiers can be found in pipelined ADCs and pipelined-SAR ADCs as inter-stage amplifiers. The amplifiers can in some cases implement and provide gains in high speed track and hold circuits. The amplifier structures can be open-loop amplifiers, and the amplifier structures can be used in MDACs and samplers of high speed ADCs. The amplifiers can be employed without resetting, and with incomplete settling, to maximize their speed and minimize their power consumption. The amplifiers can be calibrated to improve performance.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: September 13, 2022
    Assignee: Analog Devices, Inc.
    Inventor: Ahmed Mohamed Abdelatty Ali
  • Patent number: 11444612
    Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: September 13, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Nitin Agarwal, Venkat Ramakrishna Saripalli, Venkata Ramanan R
  • Patent number: 11437962
    Abstract: A differential amplifier circuit includes a first transistor, a second transistor, a field effect transistor (FET) connected between the first transistor and the second transistor, a first current source connected to the first transistor, a second current source connected to the second transistor, and a control circuit. The first transistor and the second transistor generate a differential output signal in accordance with an input signal and a reference signal. The control circuit includes a first resistor and a second resistor connected in series between the drain and the source of the FET, a center node between the first resistor and the second resistor, a third resistor connected between the gate of the FET and the center node, and a variable current source. The variable current source supplies a control current to the third resistor in accordance with a gain control signal. The control circuit controls on-resistance of the FET.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: September 6, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Naoki Itabashi, Keiji Tanaka
  • Patent number: 11430393
    Abstract: A display apparatus includes a pixel portion in which a plurality of pixels are arranged, the plurality of pixels being connected to scan lines and data lines; a data driver configured to transmit a data signal to a source output line; a data distributer configured to selectively connect the source output line to the data lines; and a latch portion arranged between the data distributer and the pixel portion, wherein the latch portion includes a plurality of latches connected to at least one of data lines excluding a data line, from among the data lines, connected to the source output line by the data distributer at a timing at which a scan signal is transmitted to the scan lines.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: August 30, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventor: Sanghyun Lim
  • Patent number: 11418159
    Abstract: The present invention provides a differential signal offset adjustment circuit, wherein first and second transistors are respectively coupled between a power supply line and a first current source, and between the power supply line and a second current source. First and second resistors are respectively coupled between the first transistor and a first variable current source, and between the second transistor and a second variable current source. Third and fourth transistors are respectively coupled between a third resistor and a third current source, and between a fourth resistor and a fourth current source, and have input terminals respectively coupled to the first and second resistors. Fifth and sixth transistors are respectively coupled between the power supply line and a fifth current source, and between the power supply line and a sixth current source, and have input terminals respectively coupled to the third and fourth transistors.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: August 16, 2022
    Assignee: GRACE CONNECTION MICROELECTRONICS LIMITED
    Inventors: Pei Wei Chen, Hsien-Ku Chen
  • Patent number: 11398805
    Abstract: Provided is a power amplification module that includes: an amplification transistor that has a constant power supply voltage supplied to a collector thereof, a bias current supplied to a base thereof and that amplifies an input signal input to the base thereof and outputs an amplified signal from the collector thereof; a first current source that outputs a first current that corresponds to a level control voltage that is for controlling a signal level of the amplified signal; and a bias transistor that has the first current supplied to a collector thereof, a bias control voltage connected to a base thereof and that outputs the bias current from an emitter thereof.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: July 26, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shota Ishihara, Yusuke Shimamune, Takashi Soga, Fuminori Morisawa, Seiko Ono, Tetsuaki Adachi
  • Patent number: 11392152
    Abstract: A voltage generation circuit may include: a first transistor coupled to an internal supply voltage terminal, and configured as a diode-connected transistor; a second transistor coupled to the first transistor and configured as a diode-connected transistor; and a third transistor coupled between the second transistor and a ground voltage terminal, and configured to operate according to a first reference voltage generated based on an external supply voltage. The voltage generation circuit may limit a variation in level of a second reference voltage which is generated through a drain terminal of the second transistor as a threshold voltage of the second transistor rises according to a rise in level of the internal supply voltage.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: July 19, 2022
    Assignee: SK hynix Inc.
    Inventors: Jin Ha Hwang, Soon Sung An
  • Patent number: 11394354
    Abstract: A digital power amplifier for a signal, the digital power amplifier comprising: a first activatable amplifier; a second activatable amplifier; and an output network, wherein an output of the first amplifier and an output of the second amplifier are coupled to the output network, and wherein the amplifiers and/or the output network are configured such that four output levels are obtainable at an output of the output network, and said output levels are configured to optimise a linearity of the digital power amplifier for said signal.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: July 19, 2022
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Gavin Tomas Watkins
  • Patent number: 11374800
    Abstract: Methods and systems are described for asynchronously measuring an equalized information signal to obtain amplitude information, modifying frequency dependent parameters of a continuous-time linear equalization (CTLE) component of the signal path, determining a correlation between CTLE parameters and signal amplitude, and adjusting, responsive to the correlation, a continuous-time linear equalization (CTLE) code of a CTLE to adjust equalization of the equalized information signal.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: June 28, 2022
    Assignee: KANDOU LABS SA
    Inventor: Ali Hormati
  • Patent number: 11353909
    Abstract: An operational amplifier comprises a front stage and an output stage. The front stage comprises a first input transistor, a second input transistor, a first node, a second node, and a first current mirror. A first voltage based on a first current through the first input transistor is generated on the first node. A second voltage based on a second current through the second input transistor is generated on the second node. The output stage is configured to output an output voltage based on at least one of the first voltage and the second voltage. The first current mirror comprises a first transistor having a drain connected to the first node, a second transistor having a drain connected to the second node, and a first offset canceling capacitor connected between gates of the first transistor and the second transistor.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 7, 2022
    Assignee: Synaptics Incorporated
    Inventor: Yutaka Saeki
  • Patent number: 11349442
    Abstract: The present invention provides a differential to single-ended converter including a first input node, a second input node, an operational amplifier and a feedback circuit. The operational amplifier has a first terminal and a second terminal, wherein the first terminal of the operational amplifier receives a first signal from the first input terminal, and the second terminal of the operational amplifier receives a second signal from the second input terminal. The feedback circuit is configured to receive an output signal of the operational amplifier and generate a first feedback signal to the first terminal of the operational amplifier to reduce a swing of the first signal, and generate a second feedback signal to the second terminal of the operational amplifier to balance noises induced by the feedback circuit and inputted to the first terminal and the second terminal.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: May 31, 2022
    Assignee: MEDIATEK INC.
    Inventors: Fong-Wen Lee, Yu-Hsin Lin
  • Patent number: 11342890
    Abstract: An apparatus to prevent supply-to-ground current in a comparator is disclosed. The apparatus includes circuitry to determine if first and second output nodes of the comparator have respectively reached first and second logic levels, and circuitry responsive to a determination that the voltage at the first and second output nodes of the comparator has reached the first and second logic levels, to generate a signal. In addition, the apparatus includes circuitry to supply the signal to a transistor, the signal to turn off the transistor and prevent the flow of supply-to-ground current through the comparator.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: May 24, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Meghna Agrawal
  • Patent number: 11340265
    Abstract: The present document describes a detection circuit to detect a condition of a flying capacitor which is charged during a charging phase and discharged during a subsequent discharging phase. The detection circuit has a timing circuit to set a detection trigger during a charging phase of the flying capacitor, and a measurement circuit to provide one or more differential measurement signals which are dependent on and/or indicative of a voltage across the flying capacitor at the detection trigger. Furthermore, the detection circuit has a comparator circuit to provide a digital output signal based on the one or more differential measurement signals, wherein the digital output signal is indicative of whether or not the flying capacitor is faulty.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: May 24, 2022
    Assignee: Silego Technology Inc.
    Inventor: Ibiyemi Omole
  • Patent number: 11329619
    Abstract: Disclosed herein is an operational amplifier including a non-inverting input terminal, an inverting input terminal, a P-type metal oxide semiconductor input differential pair, a first input tail current source, an N-type metal oxide semiconductor input differential pair, a second input tail current source, an output stage, a first correction circuit, and a second correction circuit. The first correction circuit and the second correction circuit operate over an operation region of the P-type metal oxide semiconductor input differential pair, an operation region of the N-type metal oxide semiconductor input differential pair, and a transition region in which both the P-type metal oxide semiconductor input differential pair and the N-type metal oxide semiconductor input differential pair operate.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: May 10, 2022
    Assignee: ROHM Co., LTD.
    Inventors: Naohiro Nomura, Takatoshi Manabe
  • Patent number: 11323084
    Abstract: A linear amplifier includes a pre-amplifier configured to amplify an input differential signal, a post-amplifier configured to amplify an output signal of the pre-amplifier, an amplitude detector configured to detect an amplitude of an output signal of the post-amplifier, and an output voltage corresponding to the detected amplitude, a comparator configured to control a tail current source of the pre-amplifier such that when the output voltage of the amplitude detector is less than or equal to a reference voltage, a tail current of the pre-amplifier is set to a constant value, and when the output voltage of the amplitude detector is larger than the reference voltage, the tail current is reduced to make the output voltage of the amplitude detector equal to the reference voltage.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: May 3, 2022
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Teruo Jo, Shinsuke Nakano, Munehiko Nagatani
  • Patent number: 11311728
    Abstract: Many embodiments of the invention provide a neuromodulation system that includes a digital control unit (DCU) that activates a stimulation engine during active stimulation, a current mirror that includes two feedback loops including a first feedback loop with positive feedback (PF) made of an error amplifier A1 and transistors M3 and M1 and a second feedback loop with a negative feedback (NF) made of the error amplifier A1 and transistor M3, and a high-voltage adaptive rail (Vdd/Vss) to accommodate voltage drops across high electrode impedances.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: April 26, 2022
    Assignee: The Regents of the University of California
    Inventors: Dejan Rozgic, Dejan Markovic
  • Patent number: 11316480
    Abstract: An operational amplifier includes a voltage terminal; a common terminal; a first amplification stage for receiving a differential signal pair to generate a single-end amplification signal; a first buffer for generating a first voltage according to the single-end amplification signal; a first diode for reducing the first voltage to generate a second voltage; a second amplification stage for amplifying the second voltage to generate a third voltage; a voltage stabilizing circuit for stabilizing the third voltage; a second diode coupled between the second amplification stage and the common terminal; a second buffer for generating an output voltage according to the third voltage; and a current mirror coupled to the common terminal, the first amplification stage, the first diode and the second amplification stage.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: April 26, 2022
    Assignee: RichWave Technology Corp.
    Inventor: Hwey-Ching Chien
  • Patent number: 11316504
    Abstract: To make it possible to use a transistor with relatively low gate withstand voltage at an output stage in an apparatus including a differential amplifier. An apparatus is provided. The apparatus includes: a differential amplifier having a first current path and a second current path that form a differential pair; a first output-stage transistor that has: a first main terminal connected on a power-supply potential side; a second main terminal connected on a reference-potential side; and a control terminal connected to the second current path; and a first voltage-clamp circuit connected between the control terminal and second main terminal of the first output-stage transistor.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: April 26, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tetsuya Kawashima
  • Patent number: 11309853
    Abstract: A class-D amplifier includes a first differential modulator circuit, a first driver circuit including a first high-side switch and a first low-side switch. An input of the first driver circuit may be coupled to a first output of the first differential modulator circuit so that the first differential modulator circuit controls the first driver circuit. The class-D amplifier may also include a second driver circuit including a second high-side switch and a second low-side switch coupling the second and control logic that selects between a single-ended operating state and a differential operating state of the class-D amplifier circuit. The control logic may selectively determine the input of the second driver circuit in conformity with a current operating state of the class-D amplifier circuit so that the first differential modulator circuit controls the second driver circuit when the differential operating state is selected.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: April 19, 2022
    Assignee: CIRRUS LOGIC, INC.
    Inventors: Cory J. Peterson, Chandra Prakash, Ramin Zanbaghi, Eric Kimball
  • Patent number: 11309843
    Abstract: An input receiver includes a first current source circuit, a second current source circuit, a first rail-to-rail amplifier circuit, a first inverter circuit, and a second inverter circuit. The first current source circuit adjusts an operating current flowing through a first node according to a first bias signal. The second current source circuit adjusts a ground current flowing through a second node according to a second bias signal. The first rail-to-rail amplifier circuit and the first inverter circuit are connected in parallel between the first node and the second node. The first rail-to-rail amplifier circuit receives an input signal and compares the input signal with a reference voltage and accordingly outputs an amplified signal. The second inverter circuit is coupled between an operating voltage and a ground voltage. The second inverter circuit generates an output signal according to an inverted signal outputted by the first inverter circuit.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: April 19, 2022
    Assignee: Winbond Electronics Corp.
    Inventor: Taihei Shido
  • Patent number: 11303480
    Abstract: An equalizer having a split folded cascode architecture includes a circuit having a differential pair with a single tail current source and split folded cascode branches. The single tail current source eliminates the input referred offset due to a mismatch in current sources. The folded cascode amplifier acts as the equalizer, which is split into a derivative path and a proportional path. The derivative path boosts the high frequency components of the received signal. The gain of the low frequency components of the received signal is adjusted by the proportional path. The derivative path includes variable capacitors and variable resistors which allow fixing a ‘zero’ frequency and peak gain frequency to a predetermined value, wherein frequencies greater than the ‘zero’ frequency are boosted. The proportional path includes variable resistors, which allow adjusting the low frequency gain without affecting the ‘zero’ frequency and peak gain frequency.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: April 12, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Subba Reddy Siddamurthy, Venkatasuryam Setty Issa, Aswani Aditya Kumar Tadinada
  • Patent number: 11290094
    Abstract: An input buffer using a frequency dependent impedance circuit to compensate for nonlinearity in low frequency is shown. In a pseudo-differential architecture, a frequency-dependent impedance circuit is coupled between the drain of a positive input transistor of the flipped voltage follower and the drain of a negative input transistor of the flipped voltage follower. In a single-ended architecture, the frequency-dependent impedance circuit is coupled between the drain of an input transistor of the flipped voltage follower and an alternating current ground. The frequency-dependent impedance circuit includes a capacitor.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: March 29, 2022
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Tao He, Chan-Hsiang Weng, Su-Hao Wu
  • Patent number: 11258414
    Abstract: Disclosed embodiments include a method for reducing amplifier offset drift comprised of receiving a first differential input signal at a first transistor base terminal and a second differential input signal at a second transistor base terminal, coupling the collector of the first transistor to the emitter of a third transistor and the emitter of the second transistor to the emitter of a fourth transistor, then coupling the base of the third transistor to the base of the fourth transistor. The method is also comprised of coupling the collector of the fourth transistor to an output terminal, generating a temperature dependent error correction current to minimize the difference in the amount of current flowing through the third transistor and the amount of current flowing through the fourth transistor, then injecting the error correction current into the emitter terminal of at least one of either the third transistor or the fourth transistor.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: February 22, 2022
    Assignee: Texas Instruments Incorporated
    Inventor: Viola Schaffer
  • Patent number: 11251760
    Abstract: Amplifiers with wide input range and low input capacitance are provided. In certain embodiments, an amplifier input stage includes a pair of input terminals, a pair of n-type input transistors, a first pair of isolation switches connected between the input terminals and the n-type input transistors, a pair of p-type input transistors, and a second pair of isolation switches connected between the input terminals and the p-type input transistors. The amplifier input stage further includes a control circuit that determines whether to use the n-type input transistors and/or the p-type input transistors for amplification based on a detected common-mode voltage of the input terminals. The control circuit opens the first pair of isolation switches to decouple the input terminals from the n-type input transistors when unused, and opens the second pair of isolation switches to decouple the input terminals from the p-type input transistors when unused.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: February 15, 2022
    Assignee: Analog Devices, Inc.
    Inventor: Yoshinori Kusuda
  • Patent number: 11239801
    Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: February 1, 2022
    Assignee: pSemi Corporation
    Inventors: Kashish Pal, Emre Ayranci, Miles Sanner
  • Patent number: 11223333
    Abstract: Provided is an amplification circuit for amplifying an input signal. The amplification circuit includes an input stage including an input matching circuit that receives the input signal and an input attenuation circuit that attenuates a gain for the input signal outside an operating frequency band of the amplification circuit, a transistor that amplifies the input signal provided from the input stage, and an output stage including an output matching circuit that receives a signal amplified by the transistor and an output attenuation circuit that attenuates the gain for the input signal outside the operating frequency band of the amplification circuit, and the input attenuation circuit includes a first resistor and a second resistor that are connected to a ground voltage, a first passive element connected between the input matching circuit and the second resistor, and a second passive element connected between the first passive element and the first resistor.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: January 11, 2022
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Woojin Chang, Seong-Il Kim, Sang-Heung Lee, Jongmin Lee
  • Patent number: 11190140
    Abstract: A wide voltage trans-impedance amplifier includes a first P-channel metal oxide semiconductor (PMOS) transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a first bias voltage VB1, a second bias voltage VB2, a third bias voltage VB3, a first N-channel metal oxide semiconductor (NMOS) transistor NM1, and a second NMOS transistor NM2. A common-gate amplifier detects a change of an input voltage, and a negative feedback is constructed by injecting a current into a current mirror to achieve a low input impedance. The trans-impedance amplifier uses a common-gate amplifier to monitor an input voltage and uses a current mirror to perform the transconductance enhancement on an input transistor, while ensuring a relatively high loop gain.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: November 30, 2021
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Chao Chen, Jun Yang, Xinning Liu
  • Patent number: 11183983
    Abstract: Methods and systems are described that include a differential amplifier driving an active load circuit, the active load circuit having a pair of load transistors and a high-frequency gain stage providing high frequency peaking for the active load circuit according to a frequency response characteristic determined in part by resistive values of a pair of active resistors connected, respectively, to gates of the pair of load transistors, and a bias circuit configured to stabilize the high frequency peaking of the high-frequency gain stage by generating a process-and-temperature variation (PVT)-dependent control voltage at gates of the active resistors to stabilize the resistive values of the pair of active resistors to account for PVT-dependent voltages at the gates of the pair of load transistors.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: November 23, 2021
    Assignee: KANDOU LABS, S.A.
    Inventors: Armin Tajalli, Christoph Walter
  • Patent number: 11183982
    Abstract: Methods and systems are described for receiving, at an input differential branch pair, a set of input signals, and responsively generating a first differential current, receiving, at an input of an offset voltage branch pair, an offset voltage control signal, and responsively generating a second differential current, supplementing a high-frequency component of the second differential current by injecting a high-pass filtered version of the set of input signals into the input of the offset voltage branch pair using a high-pass filter, and generating an output differential current based on the first and second differential currents using an amplifier stage connected to the input differential branch pair and the offset voltage branch pair.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: November 23, 2021
    Assignee: KANDOU LABS, S.A.
    Inventor: Armin Tajalli
  • Patent number: 11159086
    Abstract: A buck voltage converter is disclosed. The buck voltage generator includes a controller configured to generate one or more pulse width modulation (PWM) signals, and a plurality of serially connected switches configured to receive the PWM signals and to generate an output voltage signal at an output terminal based on the received PWM signals. The output voltage signal has an average voltage corresponding with a duty cycle of the PWM signals, a first switch of the plurality of serially connected switches has a first breakdown voltage and a second switch of the plurality of serially connected switches has a second breakdown voltage, and the first breakdown voltage is less than the second breakdown voltage.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: October 26, 2021
    Assignee: Empower Semiconductor, Inc.
    Inventor: Timothy Alan Phillips
  • Patent number: 11159135
    Abstract: A circuit (e.g., implemented as part of a controller area network (CAN) bus receiver includes a pre-amplifier stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output of the pre-amplifier stage, and the second input is coupled to the second output of the pre-amplifier stage. The comparator includes an input differential transistor pair, a second pair of transistors coupled to the input differential transistor pair in a cascode configuration, and a push-pull output stage coupled to the second pair of transistors.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: October 26, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Richard Sterling Broughton, Vijayalakshmi Devarajan, Richard Edwin Hubbard
  • Patent number: 11147973
    Abstract: A circuit for charge-balanced current-controlled stimulation. The circuit includes a transistor differential pair, a first current mirror, a second current mirror, and a third current mirror. The transistor differential pair includes a first differential input node, a second differential input node, a first differential output node, a second differential output node, and a common node. The transistor differential pair is configured to generate a first differential current that passes through the first differential output node and a second differential current that passes through the second differential output node. The first current mirror is configured to generate a first mirrored current based on the first differential current. The second current mirror is configured to generate a second mirrored current based on the second differential current. The third current mirror is configured to generate a third mirrored current based on the first mirrored current.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: October 19, 2021
    Assignees: AMIRKABIR UNIVERSITY OF TECHNOLOGY
    Inventor: Mohammad Mahdi Ahmadi
  • Patent number: 11128273
    Abstract: A variable-gain amplifier includes two amplification and attenuation branches, and first and a second resistive elements that are coupled between the two branches. Each branch includes a voltage follower stage and a configurable amplification stage. The voltage follower stages are intended to receive a differential signal and are configured to deliver, via the first resistive element, an intermediate differential current signal. The amplification stages are intended to receive the intermediate differential current signal and a digital control word, and are configured to deliver, via the second resistive element, an output differential voltage signal depending on the value of the digital control word.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: September 21, 2021
    Assignee: STMicroelectronics SA
    Inventor: Renald Boulestin