Having Field Effect Transistor Patents (Class 330/253)
  • Patent number: 10296026
    Abstract: A low-noise voltage reference generator that utilizes internal gain and feedback to generate an output signal having reduced sensitivity to power supply variations and loading conditions is described. A method includes generating a current based on a voltage drop across a resistor. The voltage drop is based on a second voltage drop across a gate terminal of a transistor and a source terminal of the transistor. The method includes the current using a reference voltage to generate a mirrored current through a node coupled to the drain terminal of the transistor. The method includes generating a level-shifted voltage using a voltage on the node. The method includes buffering the level-shifted voltage using a power supply voltage to generate the reference voltage.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: May 21, 2019
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Vaibhav Karkare
  • Patent number: 10298422
    Abstract: A multi-stage amplifier circuit equalizes an input signal through multiple signal amplification paths. DC gain is kept substantially constant over frequency, while adjustable high-frequency gain provides equalization (e.g., peaking). Various embodiments include a common source topology, a common gate topology, differential signaling topologies, and a topology suitable for stabilizing a voltage supply against high-frequency transient loads. A system may include one or more integrated circuits that may each include one or more instances of the multi-stage amplifier.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: May 21, 2019
    Assignee: NVIDIA Corporation
    Inventors: Sanquan Song, Nikola Nedovic, John Michael Wilson, John W. Poulton, Walker Joseph Turner
  • Patent number: 10277323
    Abstract: Embodiments of the disclosure relate to combining uplink radio frequency (RF) communications signals in a remote unit in a wireless distribution system (WDS) using a differential mixer. A remote unit in a WDS receives a first uplink RF communications signal(s) and a second uplink RF communications signal(s). A differential mixer, which is typically configured to combine a pair of differential input signals, is controlled to combine the first uplink RF communications signal(s) and second uplink RF communications signal(s) without requiring the first uplink RF communications signal(s) and second uplink RF communications signal(s) to be converted into the pair of differential input signals. As a result, it may be possible to eliminate a signal combiner and a BalUn circuit from the remote unit, thus helping to save component costs and board space, and to reduce insertion loss and ripple to improve uplink signal quality in the remote unit.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: April 30, 2019
    Assignee: Corning Optical Communications LLC
    Inventor: Dror Ben-Shlomo
  • Patent number: 10270392
    Abstract: A two-stage fully-differential amplifier achieves a relatively high unity gain frequency yet has the current consumption by a second stage limited by a bias transistor that supplies current to an internal power supply rail. The internal power supply rail supplies power to two pairs of transistors for the second stage.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: April 23, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Tony Lai, Mohammad Tabish Siddiqui
  • Patent number: 10270391
    Abstract: A differential input amplification-stage circuit comprises a voltage unit, first and second bulk-driven transistors, first and second mirror current sources, and a differential amplifier unit. The first and the second bulk-driven transistors respectively receive first and second input voltages, and converts the first and the second input voltages into first and second output currents. The differential amplifier unit separately outputs first and second adjustment currents under an action of voltages output by the first to the third voltage output ends. The first and the second mirror current sources respectively output first and second predetermined currents according to the first output current and the first adjustment current, and the second output current and the second adjustment current, so as to maintain transconductance constancy of the differential input amplification-stage circuit. Therefore, output stability is improved.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: April 23, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yangyang Tang, Chen-Xiong Zhang
  • Patent number: 10261369
    Abstract: An integrated circuit has a first pin, a voltage outputting circuit electrically connected to the first pin, a second pin, a current receiving circuit electrically connected to the second pin and a comparing circuit electrically connected to the current receiving circuit. The voltage outputting circuit outputs a first current which flow into the current receiving circuit through the second pin. After receiving the first current, the current receiving circuit outputs an output current to the comparing circuit and the comparing circuit compares the output current and a reference current to output an output signal.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: April 16, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Neng-Yi Lin, Chien-Chih Liu
  • Patent number: 10250198
    Abstract: A current feed-back instrumentation amplifier (CFIA) comprises a differential pair with degeneration for amplifying small differential voltages in the presence of large common-mode voltages. The CFIA includes input and feedback transconductors and a trimming circuit that trims the back-bias voltages of the transistors in each transconductor. The trimming circuit includes a plurality of selectable resistors disposed in the signal path of the tail current in each transconductor. Each of the plurality of selectable resistors has a switch coupled to it. When a switch is closed, only the resistors up to the respective switch are in the signal path of the bulk-to-source voltage of the differentially paired transistors. The resistor trimming circuit reduces the mismatch between transconductances of the respective differential pair transistors, in turn reducing mismatch of the overall transconductances of the transconductors, and thereby reducing the CFIA's gain error.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: April 2, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Serban Motoroiu, Jim Nolan
  • Patent number: 10236844
    Abstract: According to an embodiment, an active inductor has a first conductivity type MOS transistor with a source that is connected to an electrical power source supply line and a drain that is connected to an output terminal. It has a capacitance between a gate of the first conductivity type MOS transistor and the electrical power source supply line. It has a diode element that is connected between a drain and a gate of the first conductivity type transistor. It has an electric current source that supplies a bias electric current in a forward direction to the diode element.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: March 19, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yuta Tsubouchi, Junji Wadatsumi
  • Patent number: 10236843
    Abstract: A high gain differential amplifier includes first through eighth transistors, first through third degeneration resistors, and first through third current sources. The fourth and fifth transistors form a p-type metal-oxide-semiconductor (PMOS) transistor pair. Further, the second and eighth transistors form a current mirror circuit. The PMOS transistor pair and the current mirror circuit form a common mode feedback circuit. The high gain differential amplifier controls the common-mode output voltage with the common mode feedback circuit and a reference voltage.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: March 19, 2019
    Assignee: Synopsys, Inc.
    Inventors: Jayesh Wadekar, Ravi Mehta, Biman Chattopadhyay
  • Patent number: 10236851
    Abstract: A variable gain amplifier includes an input transistor, an auxiliary transistor, an active inductor and an input current replica circuit. The input transistor is arranged for receiving an input signal to generate an output signal at an output terminal. The auxiliary transistor is coupled to the output terminal of the input transistor, wherein a current of the output terminal flows into the input transistor and the auxiliary transistor. The active inductor is coupled to the output terminal of the input transistor. The input current replica circuit is coupled to the output terminal of the input transistor, wherein a current flowing through a portion of the input current replica circuit is equal to the current flowing through the input transistor, and both a current of the active inductor and the current of the portion of the input current replica circuit flow into the output terminal of the input transistor.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: March 19, 2019
    Assignee: MEDIATEK INC.
    Inventor: Hung-Chieh Tsai
  • Patent number: 10224886
    Abstract: An operational amplifier circuit is provided. The operational amplifier circuit includes a differential input stage circuit and a loading stage circuit. The differential input stage circuit includes a first current source, a first transistor, a second transistor, a third transistor, and a fourth transistor. The control terminal of the first transistor receives a first input signal. The control terminal of the second transistor receives a second input signal. The third transistor has a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the first current source, and a control terminal coupled to the control terminal of the second transistor. The fourth transistor has a first terminal coupled to the second terminal of the second transistor, a second terminal coupled to the first current source, and a control terminal coupled to the control terminal of the first transistor.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: March 5, 2019
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Chih-Wen Lu, Po-Yu Tseng, Jhih-Siou Cheng, Shang-I Liu, Chih-Hsien Chou
  • Patent number: 10218349
    Abstract: In one embodiment, an insulated gate bipolar transistor (IGBT) device may include an NMOS portion and a PNP portion, where the PNP portion is coupled to the NMOS portion. The PNP portion may include a base and a collector. The IGBT may further include a flyback clamp, where the flyback clamp is coupled between the base and the collector of the PNP portion.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: February 26, 2019
    Assignee: Littelfuse, Inc.
    Inventor: Justin Michael Yerger
  • Patent number: 10218185
    Abstract: A device for switching a semiconductor-based switch includes a terminal that is configured to be connected to a control terminal of the semiconductor-based switch. A controllable deactivation voltage source connected to the terminal is configured to provide, at least temporarily, a switching potential at a potential node. A control device is configured to control the controllable deactivation voltage source in a time-varying manner, such that the controllable deactivation voltage source provides the switching potential at the potential node during a switching interval. The switching potential is galvanically coupled to a supply node to which a supply potential of the control device is applied and has a lower potential value than a threshold voltage of the semiconductor-based switch. The control device is configured to control the controllable deactivation voltage source.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: February 26, 2019
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventor: René Hopperdietzel
  • Patent number: 10218323
    Abstract: A differential amplifier which does not have an effect of noise resistance deterioration, waveform distortion, and a lower bandwidth while having a wide input range is realized. The differential amplifier does not cause deterioration in a signal quality due to an increase in an input load, and it is not necessary to additionally provide a configuration for generating a reference voltage. The differential amplifier includes a differential amplification circuit and an output circuit for amplifying and outputting a differential output from the differential amplification circuit.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: February 26, 2019
    Assignee: SONY CORPORATION
    Inventors: Hiroshi Nakao, Yukihiro Yasui
  • Patent number: 10211782
    Abstract: A rail-to-rail sense amplifier includes a PMOS differential pair and an NMOS differential pair that are arranged in parallel with regard to a biasing network for driving a class AB output stage. The sense amplifier includes a first current differential amplifier and a second current differential amplifier for increasing the output swing while reducing power consumption.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: February 19, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Anirban Banerjee, Todd Morgan Rasmus
  • Patent number: 10211817
    Abstract: A LVDS device, comprising: a first pair of switches, operable to drive current from a first output to a second output through a differential signalling circuit; a second pair of switches, operable to drive current from the second output to the first output through the differential signalling circuit; a voltage limiter, connected in series with the first and second pair of switches, operable to receive a control voltage and, responsive to the control voltage, to limit a voltage at each of the first and second output to less than a clamping voltage when current is driven through the differential signalling circuit.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: February 19, 2019
    Assignee: NXP B.V.
    Inventors: Cristian Pavao Moreira, Birama Goumballa
  • Patent number: 10199987
    Abstract: A self-reconfigurable returnable mixer includes a self-reconfigurable transconductance stage. The input RF voltage signal is converted into RF current through the self-reconfigurable transconductance stage. The RF current is converted into an IF signal through down-conversion and low-pass filtering. The IF signal is fed back to the reconfigurable transconductance stage; the self-reconfigurable transconductance stage presents an open-loop structure to the input RF voltage signal, and the self-reconfigurable transconductance stage presents the topology structure of the negative feedback amplifier to the fed-back IF signal. The self-reconfigurable transconductance stage circuit achieves a high-linearity IF gain while providing a high bandwidth for the RF signal, effectively alleviating the contradiction between the conversion gain and the IF linearity in the conventional returnable structure.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: February 5, 2019
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Chao Chen, Jianhui Wu, Hong Li, Cheng Huang, Meng Zhang
  • Patent number: 10193501
    Abstract: An amplifier includes an amplifier input and an amplifier output. A compensation network is coupled to the amplifier output. The compensation network includes at least one RC network tuned to a frequency in which the amplifier operates. The compensation network provides at least one zero to compensate for at least one pole introduced by a load coupled to the amplifier output.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: January 29, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivas K. Pulijala, Steven G. Brantley
  • Patent number: 10187024
    Abstract: An amplifier includes an amplifying stage, a cascoded circuit, an input feed-forward circuit and an output stage. The amplifying stage is arranged receiving a differential input pair to generate an amplified differential input pair. The input feed-forward circuit is coupled to the cascoded circuit, and is arranged for feeding the differential input pair forward to the cascoded circuit. The output stage is coupled to the amplifying stage and the cascoded circuit, and is arranged for generating a differential output pair according to the amplified differential input pair and an output of the cascoded circuit.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: January 22, 2019
    Assignee: MEDIATEK INC.
    Inventors: Hung-Chieh Tsai, Yu-Hsin Lin
  • Patent number: 10187012
    Abstract: A class AB amplifier with improved DC gain. An amplifier includes an input stage and an output stage. The output stage is configured to amplify an output of the input stage. The output stage includes output transistors, class AB amplifier circuitry, minimum selector circuitry, and gain boost amplifier circuitry. The class AB amplifier circuitry includes a first transistor and a second transistor connected as a differential amplifier. The minimum selector circuitry is configured to control bias current in the output transistors by driving a control input of the first transistor. The gain boost amplifier circuitry is coupled to the class AB amplifier circuitry. The gain boost amplifier circuitry is configured to drive a common mode signal onto the control input of the first transistor and a control input of the second transistor, the common mode signal based on the output of the input stage.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: January 22, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Bhuvanesh Radhakrishnan Kulasekaran
  • Patent number: 10171052
    Abstract: An operational amplifier and a differential amplifying circuit thereof. The differential amplifying circuit receives a differential input signal and outputs a differential output signal. The differential amplifying circuit includes an output port that has a first terminal and a second terminal, the differential output signal being outputted via the first and second terminals; a first transistor pair receiving the differential input signal via two first ends and coupling to the first and second terminals respectively via two second ends; a second transistor pair receiving the differential input signal via two first ends and coupling to the first and second terminals respectively via two second ends; and a third transistor pair receiving a control signal via two first ends and coupling to the first and second terminals respectively via two second ends. The control signal controls the third transistor pair to switch on or off and/or controls the current flowing therethrough.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: January 1, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Kuan-Yu Shih
  • Patent number: 10164809
    Abstract: In a detection circuit, inputs correspond to received indications of vector signaling code words received by a first integrated circuit from a second integrated circuit. With four inputs, the circuit compares a first pair to obtain a first difference result and compares a second pair, disjoint from the first pair, to obtain a second difference result. The first and second difference results are then summed to form an output function. A system might use a plurality of such detection circuits to arrive at an input word. The circuit can include amplification, equalization, and input selection with efficient code word detection. The vector signaling code can be a Hadamard matrix code encoding for three input bits. The circuit might also have frequency-dependent gain, a selection function that directs one of the summation function result or the first difference result to the output function, variable gain, and/or a slicer.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: December 25, 2018
    Assignee: KANDOU LABS, S.A.
    Inventors: Roger Ulrich, Peter Hunt
  • Patent number: 10157585
    Abstract: The overdrive amplifier may include: a differential input circuit arranged by connecting, in a folded-cascode style, input transistors supplied with an input signal at gates, and feedback input transistors accepting the feedback of an output signal at respective gates; a current mirror load having mirror input current paths connected to current paths of the feedback input transistors, and mirror output current paths connected to current paths of the input transistors; an output circuit accepting the input of output control signals from the mirror output current paths of the current mirror load; and an overdrive circuit which causes bias currents of directions which boost an output of the output circuit, depending on the output control signals, to pass through the current mirror load based on the output control signals in an overdrive period.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: December 18, 2018
    Assignee: Synaptics Japan GK
    Inventor: Yutaka Saeki
  • Patent number: 10153743
    Abstract: The present invention is directed to electrical circuits and techniques thereof. More specifically, an embodiment of the present invention provides a variable gain amplifier that includes a first transistor and a second transistor whose gate terminals are coupled to a first input terminal. A first drain terminal of the first transistor and a first source terminal of the second transistor is coupled to a voltage gain control switch. There are other embodiments as well.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 11, 2018
    Assignee: INPHI CORPORATION
    Inventor: Guojun Ren
  • Patent number: 10152921
    Abstract: a display driver is provided which drives a display panel. The display driver includes first and second buffer amplifiers associated with first and second pixels positioned adjacent in a horizontal direction; first and second connection switches; and a controller. Each of the first and second buffer amplifiers includes: a differential input circuit including a MOS transistor pair, first and second drain interconnections; an active load circuit connected to the first and second drain interconnections; and an output stage. The first connection switch is connected between the output nodes of the first and second buffer amplifiers. The second connection switch is connected between the first drain interconnections of the first and second buffer amplifiers. The controller controls the first and second switches in response to image data associated with the first and second pixels.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: December 11, 2018
    Assignee: Synaptics Japan GK
    Inventors: Toshiyuki Hikichi, Shinobu Nohtomi
  • Patent number: 10135399
    Abstract: A common-mode feedback circuit includes a transconductor input stage with differential input terminals, and a frequency-compensated gain stage coupled to the transconductor input stage with differential output terminals. The common-mode feedback circuit also includes a feedback loop having a comparator configured to produce a feedback error signal for the transconductor input stage by comparing with a reference a common-mode sensing signal indicative of a common-mode voltage level sensed at the differential output terminals. In addition, the common-mode feedback loop includes a converter for converting the common-mode voltage level sensed at said differential output terminals into a current signal coupled to the comparator.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: November 20, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Francesco Carrara, Felice Alberto Torrisi, Francesco Clerici
  • Patent number: 10110184
    Abstract: Power amplification system is disclosed. A power amplification system can include a Class-E push-pull amplifier including a transformer balun. The power amplification can further include a reactance compensation circuit coupled to the transformer balun. In some embodiments, the reactance compensation circuit is configured to reduce variation over frequency of a fundamental load impedance of the power amplification system.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: October 23, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventors: Aleksey A. Lyalin, Taesong Hwang, Russ Alan Reisner, Nicholas Quinn Muhlmeyer
  • Patent number: 10075139
    Abstract: A low voltage to high voltage (LV2HV) conversion circuit has an input configured to receive an input signal (at a relatively low voltage) and an output configured to generate an output signal (at a relatively high voltage). The LV2HV conversion circuit includes a voltage to current conversion circuit referenced to the relatively low voltage and configured to convert a voltage of the input signal to a first current, wherein a magnitude of the first current is dependent on said voltage of the input signal and a gain setting value. A current mirroring circuit mirrors the first current and outputs a second current. A current to voltage conversion circuit converts the second current to a voltage of the output signal. The current mirroring circuit and current to voltage conversion circuit are referenced to the relatively high voltage.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: September 11, 2018
    Assignee: STMicroelectronics, Inc.
    Inventor: Pavan Nallamothu
  • Patent number: 10056871
    Abstract: A loop compensation circuit includes a differential difference amplifier having a first transconductance stage with a first input terminal and a second input terminal. The first input terminal is coupled to a voltage reference and the second input terminal is coupled to a feedback node. The amplifier also includes a second transconductance stage having a third input terminal and a fourth input terminal. The third input terminal is coupled to a virtually specified fixed voltage and the fourth input terminal is coupled to a fixed specified voltage. The loop compensation circuit also includes a feedback impedance coupled between an output of the differential difference amplifier and the third input terminal and a second impedance between the third input terminal and the fixed specified voltage.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: August 21, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Taewoo Kwak, Joseph Rutkowski
  • Patent number: 10051168
    Abstract: A method of automatically activating a camera application implemented in a mobile device in locked mode starts with the processor receiving a first signal from an accelerometer. The device's processor activates the camera application when the processor determines that the mobile device has remained in a stationary portrait or landscape position for a period of time based on the first signal. Activating the camera application includes signaling by the processor to the display device to display a camera screen from a locked screen. The processor may also receive a second signal from a proximity sensor that detects presence of a nearby object to the mobile device. When the processor determines that there is presence of the nearby object to the mobile device based on the second signal, the mobile device remains in locked mode and the processor does not activate the camera application.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: August 14, 2018
    Assignee: Apple Inc.
    Inventor: Conrad A. Shultz
  • Patent number: 10044327
    Abstract: A capacitive gain amplifier circuit includes two sets of Miller capacitors and two output stage differential amplifier circuits. A first set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit. The second set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a second phase that chops a signal being amplified. The second set of Miller capacitors is swapped from one polarity to an opposite polarity of the first output stage differential amplifier circuit during successive second phases. The second output stage differential amplifier circuit includes a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: August 7, 2018
    Assignee: Analog Devices Global
    Inventors: Hanqing Wang, Gerard Mora-Puchalt
  • Patent number: 10044346
    Abstract: A circuit for determining a slew rate of an input signal includes a first MOSFET, a second MOSFET, and a resistor coupled in series between a ground terminal and a power terminal. The resistor is coupled between the power terminal and the second MOSFET, and the first MOSFET is coupled between the second MOSFET and the ground. The second MOSFET is coupled to a bias circuit to provide a bias current. The circuit also includes a capacitor having a first terminal and a second terminal, the first terminal coupled to the input signal and the second terminal coupled to the gate terminal and the drain terminal of the first MOSFET. A current flowing through the MOSFET during changes in the input signal represents a slew rate of the input signal.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: August 7, 2018
    Assignee: Nuvoton Technology Corporation
    Inventor: Peter J. Holzmann
  • Patent number: 10044325
    Abstract: An amplifier circuit, a voltage sensing apparatus, and an amplification method are disclosed. The amplifier circuit comprises (1) an input stage comprising a first set of transistors to which an input signal to be amplified is applied, the transistors of the first set comprising a semiconductor body, and (2) a processing stage comprising a second set of transistors for processing the signal from the input stage and generating an output signal. The transistors of the first set have a thicker gate oxide than the transistors of the second set, and are therefore suitable for higher voltage operation. The first and second sets of transistors are supplied by the same voltage supply of the amplifier circuit. The semiconductor body of the first set of transistors is connected to a reference potential to lower the threshold voltage.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: August 7, 2018
    Assignee: IMEC VZW
    Inventors: Carolina Mora Lopez, Srinjoy Mitra
  • Patent number: 10038413
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to a fully depleted silicon on insulator power amplifier with unique biases and voltage standing wave ratio protection and methods of manufacture. The structure includes a pseudo-differential common source amplifier; first stage cascode devices connected to the pseudo-differential common source amplifier and protecting the pseudo-differential common source amplifier from an over stress; second stage cascode devices connected to the first stage cascode devices and providing differential outputs; and at least one loop receiving the differential outputs from the second stage cascode devices and feeding back the differential outputs to the second stage cascode devices.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: July 31, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: See Taur Lee, Abdellatif Bellaouar
  • Patent number: 10033339
    Abstract: A semiconductor device includes a differential amplification circuit that outputs differential output signals Vo1 and Vo2, external output terminals PD1 and PD2 to which one of the differential output signals Vo1 and Vo2 and single end signals Vo3 and Vo4 is selectively supplied, switch units SW1 and SW2 that control a conduction state between the external output terminal PD1 and the feedback line and a conduction state between the external output terminal PD2 and the feedback line, respectively, resistance elements R1 and R2 respectively provided in series with the switch units SW1 and SW2, a CMFB circuit that controls a common mode voltage of the differential amplification circuit according to a difference between an intermediate voltage Vcm of the external output terminals PD1 and PD2 in the feedback line and a reference voltage Vref, and a switch unit SW3 that controls to supply a clamp voltage to the feedback line.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: July 24, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroyuki Kuge
  • Patent number: 10027318
    Abstract: A transmission circuit includes: a first transistor, a first current source, a third transistor. The first transistor has a source terminal coupled to a first reference voltage terminal of the transmission circuit and a drain terminal coupled to a first output terminal of the transmission circuit. The first current source is coupled between a gate terminal of the first transistor and a second reference voltage terminal of the transmission circuit. The third transistor has a drain terminal coupled to the first output terminal of the transmission circuit, a source terminal coupled to the second reference voltage terminal of the transmission circuit, and a gate terminal for receiving a first input signal. The first transistor is of a first conducting type, and the second transistor is of a second conducting type different from the first conducting type.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: July 17, 2018
    Assignee: Realtek Semiconductor Corp.
    Inventor: Heng-Chia Hsu
  • Patent number: 10020739
    Abstract: An integrated current replicator includes a first current sense resistor configured to sense a first input current to a power converter during a primary portion of a duty cycle and a first transconductance amplifier configured produce a first voltage at a common circuit node proportional to the first input current during the primary portion of the duty cycle. The integrated current replicator includes a second current sense resistor configured to sense a second input current to the power converter during a complementary portion of the duty cycle and a second transconductance amplifier configured produce a second voltage at the common circuit node proportional to the second input current during the complementary portion of the duty cycle. The integrated current replicator includes an amplifier configured to produce a voltage replicating the first input current and the second input current from the first voltage and the second voltage.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: July 10, 2018
    Assignee: Altera Corporation
    Inventors: Douglas Dean Lopata, Jeffrey Demski, Jay Norton, Miguel Rojas-Gonzalez
  • Patent number: 10003315
    Abstract: Methods and systems are described for receiving, at an input differential branch pair, a set of input signals, and responsively generating a first differential current, receiving, at an input of an offset voltage branch pair, an offset voltage control signal, and responsively generating a second differential current, supplementing a high-frequency component of the second differential current by injecting a high-pass filtered version of the set of input signals into the input of the offset voltage branch pair using a high-pass filter, and generating an output differential current based on the first and second differential currents using an amplifier stage connected to the input differential branch pair and the offset voltage branch pair.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: June 19, 2018
    Assignee: KANDOU LABS S.A.
    Inventor: Armin Tajalli
  • Patent number: 10003314
    Abstract: An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: June 19, 2018
    Assignee: Ethertronics, Inc.
    Inventor: Farbod Aram
  • Patent number: 9998120
    Abstract: A circuit for shifting an input common mode voltage is described. The circuit comprises a first current path configured to generate a first current between a reference voltage and a ground potential, the first current path having a first output; a second current path configured to generate a second current between the reference voltage and the ground potential, the second current path having a second output; a first bias current control circuit coupled to the first current path and the second current path, wherein the first bias control circuit is configured to receive the input voltage to control the current in the first current path and the second current path; and a second bias current control circuit coupled to the first current path and the second current path, wherein the second bias control circuit is configured to receive the input voltage to control the current in the first current path and the second current path. A method of shifting an input common mode voltage is also described.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: June 12, 2018
    Assignee: XILINX, INC.
    Inventors: Sabarathnam Ekambaram, Hari Bilash Dubey
  • Patent number: 9998079
    Abstract: A chopper amplifier and method of operation are described. The chopper amplifier comprises a first chopper arranged to modulate an input signal using a first chopper signal having a chopper frequency. An amplification stage has an input arranged to receive the chopped signal and an output, and supplies an amplified signal at the output. An output chopper is arranged to integrate the amplified signal using a second chopper signal having the chopper frequency to generate an amplified output signal. The amplification stage is further configured to filter the chopped signal to attenuate signal components having frequencies lower than the chopper frequency.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: June 12, 2018
    Assignee: NXP B.V.
    Inventor: Mike Splithof
  • Patent number: 9991853
    Abstract: A dual operation mode power amplifier is disclosed. In the power amplifier in accordance with an embodiment of the present invention, a bias circuit part can be converted to decrease power consumption. Different from the prior art, performance of the present invention is not reduced in a high power mode, and no additional passive components like inductors or transformers with a large area are necessary to be further added. Furthermore, a tunable impedance matching circuit provides impedances respectively matching impedances of a fully differential amplifier and a single-ended amplifier, thereby improving the performance of the power amplifier.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: June 5, 2018
    Assignee: FCI INC
    Inventors: Min-Chul Kang, Myung-Woon Hwang
  • Patent number: 9979387
    Abstract: Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: May 22, 2018
    Assignee: pSemi Corporation
    Inventor: Gary Chunshien Wu
  • Patent number: 9979351
    Abstract: Provided is a differential amplifier circuit having a low current consumption and a small circuit area. The differential amplifier circuit is formed as a drain grounding circuit (source follower circuit), which includes two stages of output transistors that are connected to two stages of amplifier circuits in series, and is configured to control one of the two output transistors by output from the amplifier circuit in the first stage, and to control another of the two output transistors by output from the amplifier circuit in the second stage.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: May 22, 2018
    Assignee: ABLIC INC.
    Inventor: Yoshihisa Isobe
  • Patent number: 9973146
    Abstract: An amplifying circuit includes a reference voltage generating circuit, a common-mode voltage conversion circuit, a common-mode negative feedback circuit, and an amplifying sub-circuit. The reference voltage generating circuit generates a first reference voltage, a second reference voltage, and a reference common-mode voltage according to a post-stage common-mode voltage. The common-mode voltage conversion circuit converts the pre-stage output differential signal into a differential input signal according to the reference common-mode voltage. The common-mode negative feedback circuit generates a control voltage to quickly establish a common-mode negative feedback of the amplifying sub-circuit, wherein the first reference voltage and the second reference voltage are used to cancel a baseline signal of the pre-stage output differential signal. The amplifying circuit can eliminate the baseline signal, convert the common-mode voltage and quickly establish the common-mode negative feedback.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: May 15, 2018
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Mengwen Zhang
  • Patent number: 9970979
    Abstract: This application relates to a circuit for determining whether a first transistor device is in a predetermined operation mode. The circuit comprises comprising: a second transistor device, wherein control terminals of the first and second transistor devices are connected, and one of input and output terminals of the first transistor device is connected to the other one of input and output terminals of the second transistor device, a buffer amplifier connected between the one of input and output terminals of the first transistor device and the other one of input and output terminals of the second transistor device, and circuitry for determining whether the first transistor device is in the predetermined operation mode based on an indication of a current flowing through the second transistor device. The application further relates to a method of determining whether a first transistor device is in a predetermined operation mode.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: May 15, 2018
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Danilo Gerna, Enrico Pardi, John Kesterson
  • Patent number: 9966912
    Abstract: An amplifier circuit with a differential input and a differential output comprises a first and a second pair of matched transistors having a first threshold voltage and comprising control terminals connected to the differential input. A first and a second pair of triplets of transistors having a second threshold voltage being different from the first threshold voltage is connected to each one of the pairs of matched transistors such that respective current paths are formed with these transistors. The currents are split up to bias current sources and to an output stage such that the current is reused for implementing a class AB operation. Furthermore, a current through bias transistors connected in the current path of the first and the second pair of matched transistors is mirrored to output transistors being arranged in a differential current path of the output stage.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: May 8, 2018
    Assignee: ams AG
    Inventors: José Manuel García González, Andreas Fitzi
  • Patent number: 9966904
    Abstract: An RF amplifier to increase a gain using a transformer is provided. The amplifier includes: a first transistor configured to generate a current by amplifying and converting an input voltage; a second transistor configured to amplify the generated current; and a first transformer configured to feed an emitter current of the second transistor back to a gate. Accordingly, Gm of the transistor is boosted using the transformer, such that a high gain can be obtained with a low current. Therefore, a problem of a gain reduction caused by a parasitic capacitor at a high frequency can be solved.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 8, 2018
    Assignee: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
    Inventors: Ki Jin Kim, Kwang Ho Ahan
  • Patent number: 9954501
    Abstract: An amplifier includes a first input branch and a second input branch that form a differential input stage and a current mirror connected to the differential input. The current mirror is governed as a function of a common mode feedback signal applied to a control node of the current mirror. A second, amplification, stage includes a branch flowing through which is a current, which is a function of the current that flows in the first input branch, and is in turn connected to a first output branch. A capacitive element is coupled between the control node and the second stage. The circuit is symmetrical with respect to the input stage.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: April 24, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Marco Garbarino, Roberto Modaffari, Germano Nicollini
  • Patent number: 9941850
    Abstract: A fully differential operational amplifier is provided. The amplifier has input nodes and includes a differential input stage for receiving input signals over the input nodes and providing output signals on first and second intermediary nodes. The amplifier includes a fully differential amplification stage having positive and negative inputs coupled to the first and second intermediary nodes, respectively. The amplifier includes a first compensation transistor having conduction terminals coupled to the first intermediary node and a first node, and a control terminal coupled to a negative output of the fully differential amplification stage. The amplifier includes a second compensation transistor having conduction terminals coupled to the second intermediary node and a second node, and a control terminal coupled to a positive output of the fully differential amplification stage.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: April 10, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Luca Giuffredi, Andrea Boni, Marco Ronchi