Having Field Effect Transistor Patents (Class 330/253)
  • Patent number: 10833641
    Abstract: Various embodiments of the present technology may comprise methods and apparatus for an amplifier circuit. Methods and apparatus for an amplifier circuit according to various aspects of the present invention may comprise a first cross-connect circuit configured to receive an input signal at an input terminal and transmit the input signal to an input stage circuit. The amplifier circuit may further comprise a second cross-connect circuit connected between the input stage circuit and an output stage circuit, and a voltage adjustment circuit connected to the input stage circuit. Each cross-connect circuit may comprise a plurality of switches.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 10, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Akinobu Onishi
  • Patent number: 10826463
    Abstract: An example of a signal switch includes a first transistor coupled between first and second nodes, a plurality of second transistors coupled in series between the first and second nodes, in parallel with the first transistor, a third transistor coupled between the first node and a third node, and a plurality of fourth transistors coupled in series between the first and third nodes, in parallel with the third transistor. The signal switch further includes a first shunt path including a first shunt transistor and a first inductor connected in series between a reference node and a first connection point between two of the plurality of second transistors, and a second shunt path including a second shunt transistor and a second inductor connected in series between the reference node and a second connection point between two of the plurality of fourth transistors.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: November 3, 2020
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Nuttapong Srirattana
  • Patent number: 10824768
    Abstract: Disclosed is a security device for preventing leakage of data information in solid-state drive. The present invention provides the security device for preventing leakage of data information in solid-state drive (SSD), the device enabling a user to electrically destroy flash memory personally to prevent leakage of data stored in the SSD, which is used and is to be waste-processed.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: November 3, 2020
    Inventor: Dong Beom Kim
  • Patent number: 10811542
    Abstract: A pseudo-resistor structure, comprises: a first and a second PMOS transistor or PN diode configured as two-terminal devices, wherein the positive terminal of the first PMOS transistor or PN diode is connected to the positive terminal of the second PMOS transistor or PN diode, and wherein the negative terminal of the first PMOS transistor or PN diode is connected to an input (A) of the pseudo-resistor structure and wherein the negative terminal of the second PMOS transistor or PN diode is connected to an output (C) of the pseudo-resistor structure, and a dummy transistor or dummy diode connected to the input (A), wherein the dummy transistor or dummy diode is further connected to a bias voltage for compensating a leakage current through the first and the second PMOS transistors or PN diodes. A closed-loop operational amplifier circuit comprising the pseudo-resistor structure is provided. Also, a bio-potential sensor comprising the closed-loop operational amplifier circuit is provided.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: October 20, 2020
    Assignee: IMEC VZW
    Inventor: Carolina Mora Lopez
  • Patent number: 10810040
    Abstract: Embodiments of the present invention provide a system for real-time transmission of data associated with trigger events. The system is configured for identifying one or more priorities associated with a user, extract one or more triggers associated with the one or more priorities of the user, receiving an indication that at least one condition associated with at least one of the one or more triggers is met, determining that the user is performing one or more actions associated with at least one priority of the one or more priorities based receiving the indication, in response to determining that the user is performing the one or more actions associated with the at least one priority, dynamically extracting information associated with the user, and transmitting, in real-time, the extracted information associated with the user to at least one third party entity.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: October 20, 2020
    Assignee: BANK OF AMERICA CORPORATION
    Inventors: Katherine Dintenfass, Paul Adam Keifer, Ashwin Borges
  • Patent number: 10803277
    Abstract: A fingerprint sensing circuit and a fingerprint sensing apparatus are provided. The fingerprint sensing circuit includes a sensing electrode; a first converting circuit connected to the sensing electrode and configured to convert a coupling capacitance sensed by the sensing electrode into a drive voltage, where the drive voltage is equal to a sum of a voltage variation converted from the coupling capacitance and a reference voltage; and a second converting circuit configured to generate a sensing current based on the drive voltage, and send the sensing current to a fingerprint signal processor, where the sensing current is equal to a product of a transconductance gain of the second converting circuit and the voltage variation, and the fingerprint signal processor performs fingerprint sensing based on the sensing current. With the fingerprint sensing circuit and the fingerprint sensing apparatus, the detection accuracy can be improved.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: October 13, 2020
    Assignee: FOCALTECH ELECTRONICS, LTD.
    Inventor: Che-Wei Wu
  • Patent number: 10797695
    Abstract: An electronic device may include a sensing circuit and a current subtraction circuit. The sensing circuit may output first and second current signals. The current subtraction circuit may mirror the first and second current signals onto first and second current branches. The second current branch may be split into a first sub-path and a second sub-path. An amplifier may control the amount of current flowing through the second sub-path by forcing the current flowing through the first current branch and the current flowing through the first sub-path to be identical. Configured in this way, the current flowing through the second sub-path will be equal to the difference between the first and second current signals. The current flowing through the second sub-path may be optionally amplified using another current mirror.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: October 6, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Kyle Thomas
  • Patent number: 10795397
    Abstract: A stable reference voltage that can be supplied in a layout area smaller than prior art is provided. A current-voltage convertor includes a first current mirror circuit including a first MOS transistor, a second MOS transistor in a pair, and an output resistor; and a depletion type N-channel MOS transistor, inserted between a first voltage to be input and the first MOS transistor and the second MOS transistor, and having a gate to which an output voltage from the output resistor is fed back. When a reference current is input to the first MOS transistor, the output voltage is generated by a current corresponding to the reference current flowing into the second MOS transistor and the output resistor. In addition, a reference voltage generator including the current-voltage convertor is provided to output a reference voltage based on the output voltage of the current-voltage convertor.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: October 6, 2020
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Tomofumi Kitani
  • Patent number: 10797665
    Abstract: Systems and methods for amplifying an input signal include amplifier circuitry, an itail connection coupled between a positive voltage circuitry and the negative voltage circuitry and operable to generate an itail voltage corresponding to a greater of the positive voltage input signal (Vp) and the negative voltage input signal (Vn), a first resistor rgp disposed to receive the itail voltage and a first voltage corresponding to Vp, and a second resistor rgn disposed to receive the itail voltage and a second voltage corresponding to Vn. A first current output node is coupled to the output of rgp and operable to output a positive output current (Ioutp) corresponding to the current flowing through rgp, and a second current output is coupled to the output of rgn and operable to output a negative output current (Ioutn) corresponding to the current flowing through rgn.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: October 6, 2020
    Assignee: SYNAPTICS INCORPORATED
    Inventor: Brian Friend
  • Patent number: 10789895
    Abstract: The differential difference amplifier circuit includes a differential input stage circuit, a loading stage circuit coupled to the differential input stage circuit, and an output stage circuit coupled to the loading stage circuit. The output stage circuit is configured to generate an output signal. The differential input stage circuit includes a first differential pair having a first transconductance and a second differential pair having a second transconductance. The first differential pair is biased by a first current source and receives a first input signal and the output signal. The second differential pair is biased by a second current source and receives a second input signal and the output signal. At least one of the first transconductance and the second transconductance is adjusted according to the image data.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: September 29, 2020
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Chih-Hsien Chou, Po-Yu Tseng, Jhih-Siou Cheng
  • Patent number: 10790785
    Abstract: Embodiments of the present disclosure provide a circuit structure. An error amplifier of the structure includes an input terminal coupled to a voltage source, a reference terminal, and an output terminal coupled to a back-gate terminal of a power amplifier. A voltage at the output terminal of the error amplifier indicates a voltage difference between the input terminal and the reference terminal. A logarithmic current source may be coupled to the reference terminal of the error amplifier, the logarithmic current being configured to generate a reference current logarithmically proportionate to a voltage level of the voltage source. A plurality of serially coupled transistor cells, having a shared substrate and coupled between the reference terminal of the error amplifier and ground, each may include a back-gate terminal coupled to the output terminal of the error amplifier.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: September 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yiching Chen, Thomas G. Mckay
  • Patent number: 10784828
    Abstract: Various embodiments of the present technology comprise a method and apparatus for an operational amplifier with a variable gain-bandwidth product. According to various embodiments, an amplifier circuit comprising the operational amplifier operates in multiple stages and provides a low gain-bandwidth and a high gain-bandwidth.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: September 22, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Tsutomu Murata
  • Patent number: 10778145
    Abstract: A voltage controlled oscillator includes a first inductor, a second inductor, a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, and an inductor-capacitor (LC) tank circuit. A first end of the first inductor and a first end of the second inductor are coupled to a first power rail. A drain node of the first MOS transistor is coupled to a second end of the first inductor. A drain node of the second MOS transistor is coupled to a second end of the second inductor. Source nodes of the first MOS transistor and the second MOS transistor are coupled to a second power rail. The LC tank circuit is coupled to gate nodes of the first MOS transistor and the second MOS transistor, wherein energy is magnetically pumped into the LC tank circuit through the first inductor and the second inductor.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: September 15, 2020
    Assignee: MEDIATEK INC.
    Inventors: Yu-Li Hsueh, Po-Chun Huang, Ang-Sheng Lin, Wei-Hao Chiu
  • Patent number: 10763810
    Abstract: The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 1, 2020
    Assignee: INPHI CORPORATION
    Inventors: Simon Forey, Rajasekhar Nagulapalli, Parmanand Mishra
  • Patent number: 10764524
    Abstract: Provided is an imaging apparatus, including: a photoelectric conversion element; an amplifier transistor configured to output a voltage corresponding to electric charges generated by the photoelectric conversion element; a load transistor configured to supply a bias current to the amplifier transistor; and a voltage supply unit configured to input one of a first voltage and a second voltage, which have different voltage values, to a control node of the load transistor via an input capacitor. In the imaging apparatus, a current value of the bias current to be supplied by the load transistor at a time when the second voltage is input to the control node via the input capacitor is larger than a current value of the bias current to be supplied by the load transistor at a time when the first voltage is input to the control node via the input capacitor.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: September 1, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takamasa Sakuragi
  • Patent number: 10734953
    Abstract: A power amplifier system is disclosed that includes a power amplifier having a first signal input, a first signal output, second signal input, and a second signal output. The power amplifier system further includes cross-coupled bias circuitry having a first transistor with a first collector coupled to the first signal input, a first base coupled to the second signal input, and a first emitter coupled to a fixed voltage node, a second transistor with a second collector coupled to the second signal input, a second base coupled to the first signal input, and a second emitter coupled to the fixed voltage node.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 4, 2020
    Assignee: Qorvo US, Inc.
    Inventors: George Maxim, Stephen James Franck, Michael F. Zybura, Baker Scott
  • Patent number: 10732714
    Abstract: An integrated haptic system may include a digital signal processor and an amplifier communicatively coupled to the digital signal processor and integrated with the digital signal processor into the integrated haptic system. The digital signal processor may be configured to receive a force sensor signal indicative of a force applied to a force sensor and generate a haptic playback signal responsive to the force. The amplifier may be configured to amplify the haptic playback signal and drive a vibrational actuator communicatively coupled to the amplifier with the haptic playback signal as amplified by the amplifier.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: August 4, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Harsha Rao, Rong Hu, Carl Lennart Ståhl, Jie Su, Vadim Konradi, Teemu Ramo, Anthony Stephen Doy
  • Patent number: 10728058
    Abstract: A decision feedback equalizer includes: a comparison circuit; a latch circuit configured to latch a result of comparison by the comparison circuit; a setting circuit configured to set a decision threshold of the comparison circuit in accordance with a control signal; and a switch circuit configured to be controlled to be turned on and off by an output signal from the latch circuit, wherein the setting circuit is configured to be connected in parallel with an input stage of the comparison circuit through the switch circuit and operate in synchronization with a clock signal for driving the comparison circuit.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: July 28, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Yasufumi Sakai
  • Patent number: 10727796
    Abstract: The invention provides a Low-voltage Differential Signaling (LVDS) receiver circuit that comprises a folded-cascode operational transconductance amplifier (OTA) that includes a pair of input branches and a pair of output branches. The pair of input branches of the folded-cascode OTA includes a p-channel metal-oxide semiconductor (PMOS) input transistor pair connected to a first supply voltage domain. The pair of output branches includes an output circuit connected to a second supply voltage domain. The LVDS receiver circuit further includes a common-mode feedback circuit connected to the pair of output branches of the folded-cascode OTA that controls the second supply voltage domain. The LVDS receiver circuit further includes a regenerative buffer circuit connected to the pair of output branches of the folded-cascode OTA and an output generated from the pair of output branches of the folded-cascode OTA directly operates the regenerative buffer circuit to produce a distortion-free output signal.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: July 28, 2020
    Assignee: THE KING ABDULAZIZ CITY FOR SCIENCE AND TECHNOLOGY (KACST)
    Inventors: Mohammed Sulaiman BenSaleh, Syed Arsalan Jawed, Yasir Mehmood Siddiqi, Waqas Siddiqi, Shahab Ahmed Najmi
  • Patent number: 10691152
    Abstract: A low-dropout regulator comprises an output current branch (100) in which a first output driver (110) and a second output driver (120) is arranged. An input amplifier stage (200) provides a first control current (I1) to control the operating state of the first and the second output driver (110, 120). A current generator unit (300) provides a second control current (12) to operate the first output driver (110) in the second operating state and provides a third control current (13) to operate the second output driver (120) in the second operating state, when the first control current (I1) of the input amplifier stage (200) is below a threshold level.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: June 23, 2020
    Assignee: ams International AG
    Inventors: Carlo Fiocchi, Marco Cerchi
  • Patent number: 10666212
    Abstract: A positive-side power supply terminal (1-1a) of a differential amplifier (1-1) is connected to a positive-side power supply line (L1). A negative-side power supply terminal (1-2b) of a differential amplifier (1-2) is connected to a negative-side power supply line (L2). A negative-side power supply terminal (1-1b) of the differential amplifier (1-1) and a positive-side power supply terminal (1-2a) of the differential amplifier (1-2) are connected to each other. A final-stage amplifier (2) is connected between the positive-side power supply line (L1) and the negative-side power supply line (L2).
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: May 26, 2020
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka
  • Patent number: 10666248
    Abstract: A circuit biases an input transistor by using a voltage on a reference transistor having open gate connection and operating at the same current density as the input transistor to null current leakage at the gate of the input transistor. The input transistor is biased based on the voltage on the zero-gate-current reference transistor. The bias condition for the input transistor to operate at a zero gate current is determined by leaving the gate terminal of the reference transistor open-circuited, thus zero gate current, forcing a desired current through the reference transistor, and measuring a drain-source voltage of the reference transistor. When the input terminal of the input transistor has an ancillary circuitry that may contribute gate leakage current, the same ancillary circuitry can be coupled to the gate of the reference transistor.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: May 26, 2020
    Assignee: HRL Laboratories, LLC
    Inventor: Albert E. Cosand
  • Patent number: 10658985
    Abstract: The present disclosure provides a trans-impedance amplifier, comprising: an inverting amplifier circuit, having an input end and an output end. The input end is coupled to an optical diode and is used for accessing an input voltage signal, and the output end is used for outputting an amplified voltage signal. The inverting amplifier circuit comprises at least three sequentially-connected amplifier units. Each of the amplifier units comprises two mutually-coupled N-type transistors, wherein one N-type transistor is used for receiving an input voltage, and the other N-type transistor is used for receiving a DC voltage signal. A common connection end of the two N-type transistors is used for outputting an amplified voltage signal, and the N-type transistor used for receiving the DC voltage signal adopts a native NFET. The trans-impedance amplifier further comprises a feedback resistor coupled to the input end and the output end of the inverting amplifier circuit.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: May 19, 2020
    Assignee: HANGZHOU HONGXIN MICROELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Hehong Zou
  • Patent number: 10658992
    Abstract: A circuit for implementing an operational transconductance amplifier (OTA) based on telescopic topology, wherein cascode transistors of the operational transconductance amplifier (OTA) are self-biased without using additional biasing circuitry, which not only reduces power consumption but also achieves high gain without extra current, and each cascode stage of the OTA has a pair of transistors so that the swing of the output differential signals of the OTA can be completely symmetrical so as to benefit second-order harmonic rejection, CMRR and PSRR.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 19, 2020
    Assignee: Rafael Microelectronics, Inc.
    Inventor: Tzu-Yun Wang
  • Patent number: 10651856
    Abstract: A four-phase oscillator includes, a first oscillator configured to output a first differential signal, a second oscillator configured to output a second differential signal shifted in phase with respect to the first differential signal by 90 or ?90 degrees, and a control circuit. The first oscillator includes a first tail current source and a second tail current source. The second oscillator includes a third tail current source and a fourth tail current source. The control circuit changes the frequency of the first and second differential signals by controlling at least one of a difference between a first current value supplied from the first tail current source and a third current value supplied from the third tail current source and a difference between a second current value supplied from the second tail current source and a fourth current value supplied from the fourth tail current source.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: May 12, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Takashi Shiraishi
  • Patent number: 10644652
    Abstract: In optical receivers, extending the transimpedance amplifier's (TIA) dynamic range is a key to increasing the receiver's dynamic range, and therefore increase the channel capacity. Ideally, the TIA requires controllable gain, whereby the receiver can modify the characteristics of the TIA and/or the VGA to process high power incoming signals with a defined maximum distortion, and low power incoming signals with a defined maximum noise. A solution to the problem is to provide TIA's with reconfigurable feedback resistors, which are adjustable based on the level of power, e.g. current, generated by the photodetector, and variable load resistors, which are adjustable based on the change in impedance caused by the change in the feedback resistor.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 5, 2020
    Assignee: Elenion Technologies, LLC
    Inventors: Ariel Leonardo Vera Villarroel, Abdelrahman Ahmed, Alexander Rylyakov
  • Patent number: 10636470
    Abstract: Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: April 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hyun Yoo Lee, Suryanarayana B. Tatapudi, Huy T. Vo, Ferdinando Bedeschi, Umberto Di Vincenzo, Riccardo Muzzetto
  • Patent number: 10630283
    Abstract: Disclosed herein are switching or other active FET configurations that implement a segmented main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a plurality of main-auxiliary pairs coupled in series, wherein each main-auxiliary pair includes a main field-effect transistor (FET) in parallel with an auxiliary FET. The circuit assembly also includes a gate bias network connected to the main FETs and configured to bias the main FETs in a strong inversion region. The circuit assembly also includes an auxiliary bias network connected to the auxiliary FETs and configured to bias the auxiliary FETs in a weak inversion region.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: April 21, 2020
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, Jerod F. Mason, David Scott Whitefield, Paul T. DiCarlo
  • Patent number: 10627847
    Abstract: A bias current circuit which includes: a main unit including first PMOS and NMOS transistors constituting a first current path, and second PMOS and NMOS transistors constituting a second current path together with a first resistor; an output unit; and a supply voltage adapting unit including a third MOS transistor, a pull-up current source and a pull-down current source. The third MOS transistor is connected between a first node to which gates of the first and second PMOS transistors are connected and a second node to which drains of the second NMOS and PMOS transistors are connected. The pull-up current source is mirrored to the first PMOS transistor and configured to provide a current equal to a current provided by the pull-down current source. The bias current circuit has an operating voltage range encompassing low-voltage band such that it is operable at high and low voltages.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: April 21, 2020
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Chengwei Tang, Xin Wang
  • Patent number: 10608592
    Abstract: A linear amplifier is provided to have higher efficiency for an envelope tracking modulator. In one embodiment, a first stage amplifier circuit can be simply operated in a high gain mode or a high bandwidth mode for different applications, without using large chip area. In another embodiment, an output stage has a cascode structure whose dynamic range is controlled according to a voltage level of a supply voltage, to make a core device within the output stage have better protection and suitable dynamic range.
    Type: Grant
    Filed: January 14, 2018
    Date of Patent: March 31, 2020
    Assignee: MEDIATEK INC.
    Inventors: Chen-Yen Ho, Yu-Hsin Lin
  • Patent number: 10607560
    Abstract: A semiconductor device for driving a load of an object includes a differential circuit receiving an input signal and outputting differential output signals, first to fourth output circuits receiving the differential output signals, and a control circuit configured to respectively connect or disconnect the differential circuit to each of the first to fourth output circuits. The first output circuit is connected between high-level and mid-level power supply terminals and outputs a first output signal to the differential circuit, the second output circuit is connected between the high-level and mid-level power supply terminals, and outputs a second output signal to the load, a third output circuit is connected between mid-level and low-level power supply terminals, and outputs a third output signal to the differential circuit, and a fourth output circuit is connected between the mid-level low-level power supply terminals, and outputs a fourth output signal to the load.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: March 31, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hiroshi Tsuchi, Kenichi Shiibayashi
  • Patent number: 10608605
    Abstract: According to an embodiment, a circuit includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first control terminal to receive a first input signal, a first current terminal to output an inverted output signal, and a second current terminal. The second transistor includes a second control terminal to receive a second input signal, a third current terminal to output a non-inverted output signal, and a fourth current terminal connected to the second current terminal. The third transistor includes a third control terminal to receive the inverted output signal, a fifth current terminal electrically connected to the second and fourth current terminals, and a sixth current terminal electrically connected to a first power supply.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: March 31, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Uemura
  • Patent number: 10601437
    Abstract: CDAC (Capacitive DAC (Digital-to-Analog Converter) unit cells and RFDACs (Radio Frequency DACs) employing such CDAC unit cells are disclosed that can be employed for mmWave (millimeter wave) communication are disclosed. One example CDAC unit cell comprises: four capacitors connected in pairs to two differential outputs of the CDAC unit cell; and four logic gates, wherein each logic gate of the four logic gates is configured to receive an associated clock signal of four different clock signals and an associated enable signal of four different enable signals, and wherein each logic gate of the four logic gates is configured to trigger an associated pulse from an associated capacitor of the four capacitors based on the associated clock signal and the associated enable signal of that logic gate.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventor: Franz Kuttner
  • Patent number: 10587236
    Abstract: A driver circuit includes a first operational amplifier circuit, a second operational amplifier circuit, and at least one power switching circuit is provided. The first operational amplifier circuit receives a first input signal and generates a first output signal according to the first input signal. The second operational amplifier circuit receives a second input signal and generates a second output signal according to the second input signal. The at least one power switching circuit is coupled to the first operational amplifier circuit and the second operational amplifier circuit, and configured to switch at least one power supply for both the first operational amplifier circuit and the second operational amplifier circuit.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: March 10, 2020
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: De-Shiou Tseng, Wei-Ta Chiu
  • Patent number: 10587228
    Abstract: An amplifier circuit can have a differential input. A common-mode signal present at the differential input can induce an offset voltage at an output of the amplifier circuit. A compensation can be performed to reduce or eliminate such an offset, such as at a first temperature. Circuits and techniques for drift correction can be performed, such as to correct for residual offset error across an entirety of a specified operation temperature range. In an example, first and second drift correction signal generator circuits can be used, such as to provide signals proportional to a common mode voltage, but having different temperature coefficients.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: March 10, 2020
    Assignee: Analog Devices, Inc.
    Inventor: Quan Wan
  • Patent number: 10581420
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a difference-expanding device and a receiver. The difference-expanding device receives an input signal having voltage levels representing logical states, and converts the input signal to a processed signal by changing, based on the voltage levels, degrees in conduction of the difference-expanding device. The receiver receives the processed signal from the difference-expanding device, and determines the logical states of the input signal based on the processed signal.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: March 3, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chuan-Jen Chang
  • Patent number: 10580192
    Abstract: Regions 150 and 152 on a texture image plane 140 that correspond individually to pixels 146 and 148 representing an image on a texture image mapping target surface 144 in a screen plane 142 on which to define a display image are determined using predetermined transformation equations. The number of sampling points and their distribution are determined for the determined region in accordance with its shape and its size. Texel values in the determined region are then sampled. An average of the sampled values is acquired as the value of each of the original pixels 146 and 148.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: March 3, 2020
    Assignee: SONY INTERACTIVE ENTERTAINMENT INC.
    Inventor: Akio Ohba
  • Patent number: 10574200
    Abstract: Provided is a transconductance amplifier including a common-mode feedback circuit that does not affect an operation of the transconductance amplifier. The transconductance amplifier has a transconductance amplifier circuit configured to generate an output current based on an input voltage and a common-mode feedback circuit configured to determine a DC operating point of an output of the transconductance amplifier circuit. The common-mode feedback circuit has a plurality of level shift circuits configured to shift levels of input voltages to output the voltages, and are connected to control terminals of a plurality of transistors.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: February 25, 2020
    Assignee: ABLIC INC.
    Inventor: Masakazu Sugiura
  • Patent number: 10566933
    Abstract: A class AB amplifier with improved DC gain. An amplifier includes an input stage and an output stage. The output stage is configured to amplify an output of the input stage. The output stage includes output transistors, class AB amplifier circuitry, minimum selector circuitry, and gain boost amplifier circuitry. The class AB amplifier circuitry includes a first transistor and a second transistor connected as a differential amplifier. The minimum selector circuitry is configured to control bias current in the output transistors by driving a control input of the first transistor. The gain boost amplifier circuitry is coupled to the class AB amplifier circuitry. The gain boost amplifier circuitry is configured to drive a common mode signal onto the control input of the first transistor and a control input of the second transistor, the common mode signal based on the output of the input stage.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: February 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Bhuvanesh Radhakrishnan Kulasekaran
  • Patent number: 10554179
    Abstract: A differential circuit includes a differential pair and a back gate bias circuit. The differential circuit includes a first MOS transistor and a second MOS transistor provided between a first power supply line, to which a first power supply voltage is applied, and a second power supply line, to which a second power supply voltage is applied. The back gate bias circuit applies a bias voltage closer to the first power supply voltage than source potentials of the first MOS transistor and the second MOS transistor to back gates of the first MOS transistor and the second MOS transistor.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: February 4, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Naohiro Nomura, Sachito Horiuchi, Kunihiko Iwamoto, Takatoshi Manabe
  • Patent number: 10554453
    Abstract: A decision feedback equalizer (DFE) comprises four charge-steering (CS) primary latches and four primary taps. Two of the four CS primary latches are driven by complementary in-phase quarter-rate clocks and the other two of the four CS primary latches are driven by complementary quadrature quarter-rate clocks. No element of the DFE is driven by any half-rate clocks. In some implementations, each of the primary latches including a respective differential pair of n-channel output transistors and each primary tap includes a respective differential pair of p-channel input transistors connected via their gate nodes to a respective one of the four CS primary latches. In other implementations, each of the primary latches including a respective differential pair of p-channel input transistors and each primary tap includes a respective differential pair of n-channel output transistors connected via their gate nodes to a respective one of the four CS primary latches.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: February 4, 2020
    Assignee: Ciena Corporation
    Inventors: Mahdi Parvizi, Jacob Pike, Naim Ben-Hamida, Sadok Aouini, Calvin Plett
  • Patent number: 10552563
    Abstract: Aspects of the disclosure are directed to a digital design with bundled data asynchronous logic and body-biasing tuning. In one aspect, implementation includes establishing a control path between a first controller and a second controller using a handshaking protocol; establishing a data path between a first latch and a second latch using a bundled data technique; executing a first dynamic body biasing tuning by applying a first body bias signal to the control path; executing a second dynamic body biasing tuning by applying a second body bias signal to the data path. The digital design includes a first controller with a control path to connect to a second controller, wherein a first body bias tuning signal tunes body bias in the control path, a first latch with a data path to connect to a second latch, wherein a second body bias tuning signal tunes body bias in the data path.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: February 4, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Mark Lin, Yu Pu, Giby Samson
  • Patent number: 10547291
    Abstract: A circuit includes a transistor circuit including a first node, a second node, and a plurality of transistors coupled in parallel between the first node and the second node. The circuit further includes a drive circuit configured to switch on a first group of the plurality of transistors, the first group including a first subgroup and a second subgroup and each of the first subgroup and the second subgroup including one or more of the transistors. The drive circuit is further configured to switch off the first subgroup at the end of a first time period and switch off the second subgroup at a time instant before the end of the first time period.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: January 28, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Anton Mauder, Frank Pfirsch
  • Patent number: 10536118
    Abstract: A circuit containing a first cascode circuit and a second cascode circuit is proposed. The first circuit and the second cascode circuit are stacked between two power supply terminals. An output signal terminal of the circuit is coupled to a node connecting the first cascode circuit and the second cascode circuit. A first signal path is provided between the first cascode circuit and a common ground terminal and a second signal path is provided between the second cascode circuit and the common ground terminal.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: January 14, 2020
    Assignee: Intel IP Corporation
    Inventor: Benjamin Jann
  • Patent number: 10536122
    Abstract: A circuit for amplifying signals from a Micro Electro-Mechanical System (MEMS) capacitive sensor is provided. First and second input nodes receive a sensing signal applied differentially between the input nodes. A first amplifier stage and a second amplifier stage, respectively, produce a differential output signal between first and second output nodes. A common mode signal is detected at the output nodes. A voltage divider having an intermediate tap node is coupled between the first output node and the second output node. A feedback stage is coupled between the intermediate tap node of the voltage divider and the inputs of the first amplifier stage and the second amplifier stage, where the feedback line is sensitive to the common mode signal at the output nodes.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: January 14, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventor: Edoardo Marino
  • Patent number: 10502768
    Abstract: A current detection circuit has a differential amplification circuit that outputs a differential output current dependent on a voltage difference between input terminals and first and second feedback circuits that output a detection current in response to the differential output current and form a feedback path to each input terminal of the differential amplification circuit. First and second MOS transistors that generate voltages dependent on respective source-drain voltages at a time when drain currents in a forward direction and a backward direction flow through an output MOS transistor are connected to respective input terminals of the differential amplification circuit.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: December 10, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Hiroshi Yoshino
  • Patent number: 10498301
    Abstract: The present disclosure describes exemplary line drivers for use in an exemplary wireline transmission device. In some situations, the exemplary line drivers are electrically connected to a wireline communication channel to transmit information. The exemplary line drivers prevent charge sharing with the wireline communication channel. The exemplary line drivers disclosed herein charge various circuit nodes to various logical values, such as a logical zero or a logical one, to prevent charge sharing with the wireline communication channel.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Xin Jie Wang, Dirk Pfaff
  • Patent number: 10490975
    Abstract: A damping circuit having an input terminal and an output terminal is described. The damping circuit comprises a driver having an input and an output; an RC circuit coupled between the input terminal and the output; and a resistor coupled between the output and the output terminal, wherein the RC circuit delays passing a signal from the output terminal to the input terminal and a low impedance associated with the driver generally reduces ringing.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: November 26, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Douglas Warren Dean, Craig Matthew Brannon
  • Patent number: 10483916
    Abstract: An area efficient amplifier that amplifies a continuous-time continuous-amplitude signal and converts it to a discrete-time discrete-amplitude signal. The amplifier includes a first oscillator having an input and a plurality of N outputs and a second oscillator having an input and N outputs. The amplifier includes N phase detectors, each phase detector has a first input, a second input, a first output, and a second output, where each first input of each phase detector is coupled to respective one of the N outputs of the first oscillator, where each second input of each phase detector is coupled to respective one of the N outputs of the second oscillator. The amplifier includes N quantizers, each quantizer has a data input, a clock input, and an output, where each data input of each quantizer is coupled to respective one first output or one second output of the N phase detectors.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: November 19, 2019
    Assignee: SEAMLESS MICROSYSTEMS, INC.
    Inventor: Jayanth Kuppambatti
  • Patent number: 10476458
    Abstract: It is often desirable to distinguish between an open circuit condition and a no signal condition. In both cases an input signal may be absent, but only one of these events represents a failure of the equipment. The present disclosure provides a way to use a difference amplifier to check for open circuit events, without requiring additional circuitry at the input of the amplifier.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: November 12, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Jonathan Ephraim David Hurwitz, Jesus Bonache, Robert Sythes, Eamonn J. Byrne