Abstract: A fully-differential two-stage operational amplifier circuit is provided, and it includes a first-stage amplification circuit, a second-stage amplification circuit, a common-mode signal acquisition circuit, a common-mode feedback circuit and a bias circuit. The first-stage amplification circuit has a telescopic structure and receives differential input signals INP and INN. The second-stage amplification circuit has a common-source structure and outputs differential output signals OUTP and OUTN. The common-mode signal acquisition circuit receives differential output signals, and outputs an operational amplifier output common-mode signal VCMO. The common-mode feedback circuit outputs common-mode feedback signals VB1 and VB2 to the first-stage amplifier circuit and the second-stage amplifier circuit respectively; The bias circuit outputs a bias voltage VB3 to the first-stage amplifier circuit, and outputs bias voltages VB4 and VB5 to the first-stage amplifier circuit respectively.

Abstract: Methods and devices used in mobile receiver front end to support multiple paths and multiple frequency bands are described. The presented devices and methods provide benefits of scalability, frequency band agility, as well as size reduction by using one low noise amplifier per simultaneous outputs. Based on the disclosed teachings, variable gain amplification of multiband signals is also presented.

Abstract: An input stage configured to differentially amplify an input signal and an output signal, a first current mirror and a second current mirror configured to receive a differential current from the input stage, an output stage including first and second output transistors, respectively including a gate connected to the first and second current mirrors, and a slew rate compensation circuit configured to (i) mirror a comparison current generated by comparing a voltage of a first input signal with a voltage of a second input signal, and (ii) provide the mirrored comparison current to the gate of the first or second output transistor.

Abstract: An amplifier with an input stage comprising: a first current mirror; a first input differential pair; a first current source; a second current source; a second input differential pair, wherein the first input differential pair and the second input differential pair receive a reference voltage; a second current mirror; and a voltage control transmission circuit. An extra current path in the first current mirror is formed and a current flowing through the extra current path flows through the second current mirror to a ground when the reference voltage is higher than a first predetermined value. Also, an extra current path in the second current mirror is formed and a current flowing through the extra current path in the second current mirror flows to the first current mirror when the reference voltage is lower than a second predetermined value.

Abstract: An electronic circuit is provided. The electronic circuit includes a first current generating circuit configured to output a first operating current based on a first operating voltage; and an input circuit configured to: receive a first current corresponding to a first input voltage and a second current corresponding to a second input voltage, wherein the first current and the second current are based on the first operating current; receive a third current and a fourth current that are generated based on the first operating voltage; and generate a fifth current corresponding to the second input voltage based on a second operating current. The electronic circuit is configured to generate an output voltage that is associated with a difference between the first input voltage and the second input voltage based on the second current, the fourth current and the fifth current, and the fourth current corresponds to the third current.

Abstract: An overvoltage protection and gain bootstrap circuit of a power amplifier includes a power amplification transistor, and a diode reversely connected with a gate of the power amplification transistor. A negative electrode of the diode is connected with the gate of the power transistor, and a positive electrode of the diode is connected with a constant voltage source, such that a function of overvoltage protection and gain bootstrap of the circuit is realized by controlling a turn-on state of the diode. By adding a diode device to the circuit, gate-drain overvoltage protection for the power amplification transistor can be provided, and the gain of the amplifier can be improved before power compression, thereby improving linearity of the power amplifier. The structure of the circuit can be simple, with reduced occupied area hardware cost.

Abstract: A differential amplifier of a memory controller may include: an amplification stage configured to amplify input differential signals to generate intermediate differential signals; a control circuit configured to control slew rates for the intermediate differential signals; and an output circuit configured to selectively perform one or more switching operations according to the intermediate differential signals to generate output differential signals.

Abstract: A differential amplifier includes first and second MOS transistors of a first conductivity type which constitute a differential input circuit, a bias current source which supplies a bias current to the first and second MOS transistors, and a third MOS transistor of the first conductivity type provided between the bias current source and the first and second MOS transistors and constituted to limit a back-gate voltage of the first and second MOS transistors.

Abstract: A dual-drive power amplifier (PA) where the PA core includes a differential pair of transistors M1 and M2 that are driven by a coupling network having two transmission-line couplers, where a first transmission line section of a coupler is configured to transmit an input signal Vin through to drive a gate of the opposite transistor, while the second transmission line section is grounded at one end and coupled with the first transmission line section such that a coupled portion ?Vin of the input signal Vin drives the source terminal of a corresponding transistor. The arrangement of the coupling network allows the source terminals to be driven below ground potential. Embodiments disclosed here further provide an input matching network, a driver, an inter-stage matching network, and an output network for practical implementation of the PA core.

Abstract: Some aspects of the present disclosure provide for a circuit. In at least some examples, the circuit includes an integrator coupled between a first node and a second node and a filter coupled between the second node and a third node. The circuit further includes a buffer coupled between the third node and a fourth node and a first switch coupled between the fourth node and a fifth node. The circuit further includes a first capacitor coupled between the fifth node and a ground node, a first resistor comprising a first terminal coupled to the fifth node and a second terminal, a second switch coupled between the second terminal of the first resistor and the ground node.

Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.

Abstract: A DC-DC converter according to an embodiment is a DC-DC converter for generating an output voltage VOUT according to a reference voltage VREF, and includes a fully differential amplifier that outputs a first differential output signal and a second differential output signal according to a differential input using the reference voltage VREF and the output voltage VOUT, a pulse width modulation signal generation circuit that generates a pulse width modulation signal based on the first differential output signal Vout1 and the second differential output signal Vout2, and a driver that outputs a driving signal obtained by waveform-shaping the pulse width modulation signal.

Abstract: A low noise amplifier that may include a first input port, a second input port, a first capacitor, a second capacitor, a first variable capacitor, a second variable capacitor, an inductor, a bias circuit, a tuning circuit, a first output circuit having a first output, a second output circuit having a second output; wherein the first input port is electrically coupled to a first end of the second variable capacitor, to a first end of the first capacitor, to an input of the first output circuit, and to a first port of the inductor; wherein the second input port is electrically coupled to a second end of the first variable capacitor, to a second end of the second capacitor, to an input of the second output circuit, and to a second port of the inductor; wherein a first port of the first varactor is electrically coupled to a second end of the first capacitor; wherein a second port of the second varactor is electrically coupled to a first end of the second capacitor; wherein the bias circuit is configured to supply

Abstract: Amplifiers can be found in pipelined ADCs and pipelined-SAR ADCs as inter-stage amplifiers. The amplifiers can in some cases implement and provide gains in high speed track and hold circuits. The amplifier structures can be open-loop amplifiers, and the amplifier structures can be used in MDACs and samplers of high speed ADCs. The amplifiers can be employed without resetting, and with incomplete settling, to maximize their speed and minimize their power consumption. The amplifiers can be calibrated to improve performance.

Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.

Abstract: A differential amplifier circuit includes a first transistor, a second transistor, a field effect transistor (FET) connected between the first transistor and the second transistor, a first current source connected to the first transistor, a second current source connected to the second transistor, and a control circuit. The first transistor and the second transistor generate a differential output signal in accordance with an input signal and a reference signal. The control circuit includes a first resistor and a second resistor connected in series between the drain and the source of the FET, a center node between the first resistor and the second resistor, a third resistor connected between the gate of the FET and the center node, and a variable current source. The variable current source supplies a control current to the third resistor in accordance with a gain control signal. The control circuit controls on-resistance of the FET.

Abstract: A display apparatus includes a pixel portion in which a plurality of pixels are arranged, the plurality of pixels being connected to scan lines and data lines; a data driver configured to transmit a data signal to a source output line; a data distributer configured to selectively connect the source output line to the data lines; and a latch portion arranged between the data distributer and the pixel portion, wherein the latch portion includes a plurality of latches connected to at least one of data lines excluding a data line, from among the data lines, connected to the source output line by the data distributer at a timing at which a scan signal is transmitted to the scan lines.

Abstract: The present invention provides a differential signal offset adjustment circuit, wherein first and second transistors are respectively coupled between a power supply line and a first current source, and between the power supply line and a second current source. First and second resistors are respectively coupled between the first transistor and a first variable current source, and between the second transistor and a second variable current source. Third and fourth transistors are respectively coupled between a third resistor and a third current source, and between a fourth resistor and a fourth current source, and have input terminals respectively coupled to the first and second resistors. Fifth and sixth transistors are respectively coupled between the power supply line and a fifth current source, and between the power supply line and a sixth current source, and have input terminals respectively coupled to the third and fourth transistors.

Abstract: Provided is a power amplification module that includes: an amplification transistor that has a constant power supply voltage supplied to a collector thereof, a bias current supplied to a base thereof and that amplifies an input signal input to the base thereof and outputs an amplified signal from the collector thereof; a first current source that outputs a first current that corresponds to a level control voltage that is for controlling a signal level of the amplified signal; and a bias transistor that has the first current supplied to a collector thereof, a bias control voltage connected to a base thereof and that outputs the bias current from an emitter thereof.

Abstract: A digital power amplifier for a signal, the digital power amplifier comprising: a first activatable amplifier; a second activatable amplifier; and an output network, wherein an output of the first amplifier and an output of the second amplifier are coupled to the output network, and wherein the amplifiers and/or the output network are configured such that four output levels are obtainable at an output of the output network, and said output levels are configured to optimise a linearity of the digital power amplifier for said signal.

Abstract: A voltage generation circuit may include: a first transistor coupled to an internal supply voltage terminal, and configured as a diode-connected transistor; a second transistor coupled to the first transistor and configured as a diode-connected transistor; and a third transistor coupled between the second transistor and a ground voltage terminal, and configured to operate according to a first reference voltage generated based on an external supply voltage. The voltage generation circuit may limit a variation in level of a second reference voltage which is generated through a drain terminal of the second transistor as a threshold voltage of the second transistor rises according to a rise in level of the internal supply voltage.

Abstract: Methods and systems are described for asynchronously measuring an equalized information signal to obtain amplitude information, modifying frequency dependent parameters of a continuous-time linear equalization (CTLE) component of the signal path, determining a correlation between CTLE parameters and signal amplitude, and adjusting, responsive to the correlation, a continuous-time linear equalization (CTLE) code of a CTLE to adjust equalization of the equalized information signal.

Abstract: An operational amplifier comprises a front stage and an output stage. The front stage comprises a first input transistor, a second input transistor, a first node, a second node, and a first current mirror. A first voltage based on a first current through the first input transistor is generated on the first node. A second voltage based on a second current through the second input transistor is generated on the second node. The output stage is configured to output an output voltage based on at least one of the first voltage and the second voltage. The first current mirror comprises a first transistor having a drain connected to the first node, a second transistor having a drain connected to the second node, and a first offset canceling capacitor connected between gates of the first transistor and the second transistor.

Abstract: The present invention provides a differential to single-ended converter including a first input node, a second input node, an operational amplifier and a feedback circuit. The operational amplifier has a first terminal and a second terminal, wherein the first terminal of the operational amplifier receives a first signal from the first input terminal, and the second terminal of the operational amplifier receives a second signal from the second input terminal. The feedback circuit is configured to receive an output signal of the operational amplifier and generate a first feedback signal to the first terminal of the operational amplifier to reduce a swing of the first signal, and generate a second feedback signal to the second terminal of the operational amplifier to balance noises induced by the feedback circuit and inputted to the first terminal and the second terminal.

Abstract: An apparatus to prevent supply-to-ground current in a comparator is disclosed. The apparatus includes circuitry to determine if first and second output nodes of the comparator have respectively reached first and second logic levels, and circuitry responsive to a determination that the voltage at the first and second output nodes of the comparator has reached the first and second logic levels, to generate a signal. In addition, the apparatus includes circuitry to supply the signal to a transistor, the signal to turn off the transistor and prevent the flow of supply-to-ground current through the comparator.

Abstract: The present document describes a detection circuit to detect a condition of a flying capacitor which is charged during a charging phase and discharged during a subsequent discharging phase. The detection circuit has a timing circuit to set a detection trigger during a charging phase of the flying capacitor, and a measurement circuit to provide one or more differential measurement signals which are dependent on and/or indicative of a voltage across the flying capacitor at the detection trigger. Furthermore, the detection circuit has a comparator circuit to provide a digital output signal based on the one or more differential measurement signals, wherein the digital output signal is indicative of whether or not the flying capacitor is faulty.

Abstract: Disclosed herein is an operational amplifier including a non-inverting input terminal, an inverting input terminal, a P-type metal oxide semiconductor input differential pair, a first input tail current source, an N-type metal oxide semiconductor input differential pair, a second input tail current source, an output stage, a first correction circuit, and a second correction circuit. The first correction circuit and the second correction circuit operate over an operation region of the P-type metal oxide semiconductor input differential pair, an operation region of the N-type metal oxide semiconductor input differential pair, and a transition region in which both the P-type metal oxide semiconductor input differential pair and the N-type metal oxide semiconductor input differential pair operate.

Abstract: A linear amplifier includes a pre-amplifier configured to amplify an input differential signal, a post-amplifier configured to amplify an output signal of the pre-amplifier, an amplitude detector configured to detect an amplitude of an output signal of the post-amplifier, and an output voltage corresponding to the detected amplitude, a comparator configured to control a tail current source of the pre-amplifier such that when the output voltage of the amplitude detector is less than or equal to a reference voltage, a tail current of the pre-amplifier is set to a constant value, and when the output voltage of the amplitude detector is larger than the reference voltage, the tail current is reduced to make the output voltage of the amplitude detector equal to the reference voltage.

Abstract: Many embodiments of the invention provide a neuromodulation system that includes a digital control unit (DCU) that activates a stimulation engine during active stimulation, a current mirror that includes two feedback loops including a first feedback loop with positive feedback (PF) made of an error amplifier A1 and transistors M3 and M1 and a second feedback loop with a negative feedback (NF) made of the error amplifier A1 and transistor M3, and a high-voltage adaptive rail (Vdd/Vss) to accommodate voltage drops across high electrode impedances.

Abstract: To make it possible to use a transistor with relatively low gate withstand voltage at an output stage in an apparatus including a differential amplifier. An apparatus is provided. The apparatus includes: a differential amplifier having a first current path and a second current path that form a differential pair; a first output-stage transistor that has: a first main terminal connected on a power-supply potential side; a second main terminal connected on a reference-potential side; and a control terminal connected to the second current path; and a first voltage-clamp circuit connected between the control terminal and second main terminal of the first output-stage transistor.

Abstract: An operational amplifier includes a voltage terminal; a common terminal; a first amplification stage for receiving a differential signal pair to generate a single-end amplification signal; a first buffer for generating a first voltage according to the single-end amplification signal; a first diode for reducing the first voltage to generate a second voltage; a second amplification stage for amplifying the second voltage to generate a third voltage; a voltage stabilizing circuit for stabilizing the third voltage; a second diode coupled between the second amplification stage and the common terminal; a second buffer for generating an output voltage according to the third voltage; and a current mirror coupled to the common terminal, the first amplification stage, the first diode and the second amplification stage.

Abstract: A class-D amplifier includes a first differential modulator circuit, a first driver circuit including a first high-side switch and a first low-side switch. An input of the first driver circuit may be coupled to a first output of the first differential modulator circuit so that the first differential modulator circuit controls the first driver circuit. The class-D amplifier may also include a second driver circuit including a second high-side switch and a second low-side switch coupling the second and control logic that selects between a single-ended operating state and a differential operating state of the class-D amplifier circuit. The control logic may selectively determine the input of the second driver circuit in conformity with a current operating state of the class-D amplifier circuit so that the first differential modulator circuit controls the second driver circuit when the differential operating state is selected.

Abstract: An input receiver includes a first current source circuit, a second current source circuit, a first rail-to-rail amplifier circuit, a first inverter circuit, and a second inverter circuit. The first current source circuit adjusts an operating current flowing through a first node according to a first bias signal. The second current source circuit adjusts a ground current flowing through a second node according to a second bias signal. The first rail-to-rail amplifier circuit and the first inverter circuit are connected in parallel between the first node and the second node. The first rail-to-rail amplifier circuit receives an input signal and compares the input signal with a reference voltage and accordingly outputs an amplified signal. The second inverter circuit is coupled between an operating voltage and a ground voltage. The second inverter circuit generates an output signal according to an inverted signal outputted by the first inverter circuit.

Abstract: An equalizer having a split folded cascode architecture includes a circuit having a differential pair with a single tail current source and split folded cascode branches. The single tail current source eliminates the input referred offset due to a mismatch in current sources. The folded cascode amplifier acts as the equalizer, which is split into a derivative path and a proportional path. The derivative path boosts the high frequency components of the received signal. The gain of the low frequency components of the received signal is adjusted by the proportional path. The derivative path includes variable capacitors and variable resistors which allow fixing a ‘zero’ frequency and peak gain frequency to a predetermined value, wherein frequencies greater than the ‘zero’ frequency are boosted. The proportional path includes variable resistors, which allow adjusting the low frequency gain without affecting the ‘zero’ frequency and peak gain frequency.

Abstract: An input buffer using a frequency dependent impedance circuit to compensate for nonlinearity in low frequency is shown. In a pseudo-differential architecture, a frequency-dependent impedance circuit is coupled between the drain of a positive input transistor of the flipped voltage follower and the drain of a negative input transistor of the flipped voltage follower. In a single-ended architecture, the frequency-dependent impedance circuit is coupled between the drain of an input transistor of the flipped voltage follower and an alternating current ground. The frequency-dependent impedance circuit includes a capacitor.

Abstract: Disclosed embodiments include a method for reducing amplifier offset drift comprised of receiving a first differential input signal at a first transistor base terminal and a second differential input signal at a second transistor base terminal, coupling the collector of the first transistor to the emitter of a third transistor and the emitter of the second transistor to the emitter of a fourth transistor, then coupling the base of the third transistor to the base of the fourth transistor. The method is also comprised of coupling the collector of the fourth transistor to an output terminal, generating a temperature dependent error correction current to minimize the difference in the amount of current flowing through the third transistor and the amount of current flowing through the fourth transistor, then injecting the error correction current into the emitter terminal of at least one of either the third transistor or the fourth transistor.

Abstract: Amplifiers with wide input range and low input capacitance are provided. In certain embodiments, an amplifier input stage includes a pair of input terminals, a pair of n-type input transistors, a first pair of isolation switches connected between the input terminals and the n-type input transistors, a pair of p-type input transistors, and a second pair of isolation switches connected between the input terminals and the p-type input transistors. The amplifier input stage further includes a control circuit that determines whether to use the n-type input transistors and/or the p-type input transistors for amplification based on a detected common-mode voltage of the input terminals. The control circuit opens the first pair of isolation switches to decouple the input terminals from the n-type input transistors when unused, and opens the second pair of isolation switches to decouple the input terminals from the p-type input transistors when unused.

Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration.

Abstract: Provided is an amplification circuit for amplifying an input signal. The amplification circuit includes an input stage including an input matching circuit that receives the input signal and an input attenuation circuit that attenuates a gain for the input signal outside an operating frequency band of the amplification circuit, a transistor that amplifies the input signal provided from the input stage, and an output stage including an output matching circuit that receives a signal amplified by the transistor and an output attenuation circuit that attenuates the gain for the input signal outside the operating frequency band of the amplification circuit, and the input attenuation circuit includes a first resistor and a second resistor that are connected to a ground voltage, a first passive element connected between the input matching circuit and the second resistor, and a second passive element connected between the first passive element and the first resistor.

Abstract: A wide voltage trans-impedance amplifier includes a first P-channel metal oxide semiconductor (PMOS) transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a first bias voltage VB1, a second bias voltage VB2, a third bias voltage VB3, a first N-channel metal oxide semiconductor (NMOS) transistor NM1, and a second NMOS transistor NM2. A common-gate amplifier detects a change of an input voltage, and a negative feedback is constructed by injecting a current into a current mirror to achieve a low input impedance. The trans-impedance amplifier uses a common-gate amplifier to monitor an input voltage and uses a current mirror to perform the transconductance enhancement on an input transistor, while ensuring a relatively high loop gain.

Abstract: Methods and systems are described that include a differential amplifier driving an active load circuit, the active load circuit having a pair of load transistors and a high-frequency gain stage providing high frequency peaking for the active load circuit according to a frequency response characteristic determined in part by resistive values of a pair of active resistors connected, respectively, to gates of the pair of load transistors, and a bias circuit configured to stabilize the high frequency peaking of the high-frequency gain stage by generating a process-and-temperature variation (PVT)-dependent control voltage at gates of the active resistors to stabilize the resistive values of the pair of active resistors to account for PVT-dependent voltages at the gates of the pair of load transistors.

Abstract: Methods and systems are described for receiving, at an input differential branch pair, a set of input signals, and responsively generating a first differential current, receiving, at an input of an offset voltage branch pair, an offset voltage control signal, and responsively generating a second differential current, supplementing a high-frequency component of the second differential current by injecting a high-pass filtered version of the set of input signals into the input of the offset voltage branch pair using a high-pass filter, and generating an output differential current based on the first and second differential currents using an amplifier stage connected to the input differential branch pair and the offset voltage branch pair.

Abstract: A buck voltage converter is disclosed. The buck voltage generator includes a controller configured to generate one or more pulse width modulation (PWM) signals, and a plurality of serially connected switches configured to receive the PWM signals and to generate an output voltage signal at an output terminal based on the received PWM signals. The output voltage signal has an average voltage corresponding with a duty cycle of the PWM signals, a first switch of the plurality of serially connected switches has a first breakdown voltage and a second switch of the plurality of serially connected switches has a second breakdown voltage, and the first breakdown voltage is less than the second breakdown voltage.

Abstract: A circuit (e.g., implemented as part of a controller area network (CAN) bus receiver includes a pre-amplifier stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output of the pre-amplifier stage, and the second input is coupled to the second output of the pre-amplifier stage. The comparator includes an input differential transistor pair, a second pair of transistors coupled to the input differential transistor pair in a cascode configuration, and a push-pull output stage coupled to the second pair of transistors.

Abstract: A circuit for charge-balanced current-controlled stimulation. The circuit includes a transistor differential pair, a first current mirror, a second current mirror, and a third current mirror. The transistor differential pair includes a first differential input node, a second differential input node, a first differential output node, a second differential output node, and a common node. The transistor differential pair is configured to generate a first differential current that passes through the first differential output node and a second differential current that passes through the second differential output node. The first current mirror is configured to generate a first mirrored current based on the first differential current. The second current mirror is configured to generate a second mirrored current based on the second differential current. The third current mirror is configured to generate a third mirrored current based on the first mirrored current.

Abstract: A variable-gain amplifier includes two amplification and attenuation branches, and first and a second resistive elements that are coupled between the two branches. Each branch includes a voltage follower stage and a configurable amplification stage. The voltage follower stages are intended to receive a differential signal and are configured to deliver, via the first resistive element, an intermediate differential current signal. The amplification stages are intended to receive the intermediate differential current signal and a digital control word, and are configured to deliver, via the second resistive element, an output differential voltage signal depending on the value of the digital control word.

Abstract: A scan driver includes a plurality of circuit stages, each circuit stage including a first input part configured to transfer a carry signal to a first node in response to a first clock signal, a second input part configured to transfer the first clock signal to a second node in response to a signal of the first node, a first output part configured to transfer a third clock signal to an output terminal in response to a signal of the second node, a holding part configured to maintain a signal of a third node response to a second clock signal, and a second output part configured to transfer a signal of the third node to the output terminal in response to the second clock signal.

Abstract: A compact ADC circuit can include one or more comparators, and a serial DAC (Digital-to-Analog) circuit that provides a signal to the comparator (or comparators). In addition, the ADC circuit can include a serial DAC redistribution sequencer that can provide a plurality of signals as input to the serial DAC circuit and is subject to a redistribution cycle and which receives as input a signal from a data multiplexer whose input connects electronically to an output of the comparator. The circuit can further include an ADC code register that provides an ADC output that connects electronically to the output of the comparator and the input to the data multiplexer. Shared logic circuitry for sharing common logic between pixels can be included, wherein the shared logic circuitry connects electronically to the data multiplexer and the ADC code register, wherein the shared logic circuitry promotes area and power savings for the pixel detector circuit.

Abstract: An amplification interface includes a drain of a first FET connected to a first node, a drain of a second FET connected to a second node, and sources of the first and second FETs connected to a third node. First and second bias-current generators are connected to the first and second nodes. A third FET is connected between the third node and a reference voltage. A regulation circuit drives the gate of the third FET to regulate the common mode of the voltage at the first node and the voltage at the second node to a desired value. A current generator applies a correction current to the first and/or second node. A differential current integrator has a first and second inputs connected to the second and first nodes. The integrator supplies a voltage representing the integral of the difference between the currents received at the second and first inputs.

Abstract: Various embodiments of the present technology comprise a method and apparatus for a dual mode operational amplifier. According to various embodiments, the operational amplifier functions as both a fully-differential amplifier and a single-ended amplifier. The operational amplifier may comprise additional transistors that function as switches, which can be selectively operated according to a desired mode.