Abstract: An amplifier includes input transconductors that receive an input signal, the input signal having a voltage swing. A supply side current mirror generates a gate voltage as a function of input signal voltage and current sources that provide a bias current of the input transconductors as a function of the gate voltage to maintain a constant bias current across the voltage swing of the input signal. Resistors average source voltages of the transconductance-cancelling transconductors to provide an average source voltage and apply the average source voltage to wells of input devices of the transconductance-cancelling transconductors to reduce back bias effect. The input devices are laid out in a same well and have a common centroid to cancel out process mismatches. A first I-DAC trims an offset of first transconductors, and a second I-DAC trims an offset of second transconductors to attain low offsets across a rail-to-rail input common mode range.

Abstract: Embodiments described herein present a new LDO design that eliminates the need for the sleep bias circuitry included in other systems. Further, the new LDO design can be biased with a small fraction of the operating current enabling the LDO to wake up substantially faster than previous LDO designs that include separate sleep circuitry. In some cases, the LDO can instantly (or faster than other LDOs) transition from a sleep mode to an operating mode enabling improved operation compared to prior LDOs. Furthermore, the new LDO design maintains a non-breakdown voltage across the transistors reducing the need to enter sleep mode to prevent transistors of the LDO from entering a breakdown region.

Abstract: A receiver includes an amplifier that receives a transmission signal and amplifies a first voltage difference between the transmission signal and a reference signal to generate a first output signal and a second output signal at a first node and a second node. An equalizer is provided, which is connected to the first node and the second node and receives the transmission signal. The equalizer compensates a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal.

Abstract: A device includes a first inductor and a second inductor. The first inductor has a first inductive coupling profile. A first circuit component is coupled to the first inductor. A second inductor has a second inductive coupling profile. A second circuit component coupled to the second inductor.

Abstract: An inverse pseudo fully-differential amplifier having a common-mode feedback control circuit and a method for maintaining a stable output common-mode level are provided. The inverse pseudo fully-differential amplifier includes the pseudo fully-differential operation circuit and a common-mode feedback control circuit. The pseudo fully-differential operation circuit includes inverter amplifiers (2) and (3). The inverter amplifiers (2) and (3) respectively have a first feedback control terminal and a second feedback control terminal. Input terminals of the common-mode feedback control circuit are respectively connected with output terminals of the inverter amplifier (2) and (3), and are configured to detect common-mode output voltages of the inverter amplifier (2) and (3).

Abstract: A bandwidth enhanced amplifier for high frequency CML To CMOS conversion is disclosed. In some implementations, an improved CML to CMOS converter includes a differential amplifier having a first and a second input transistors, and a first and a second load transistors. The first input transistor is coupled in series with the first load transistor, and the second input transistor is coupled in series with the second load transistor. The improved CML to CMOS converter further includes a first capacitor and a second capacitor. The first capacitor is coupled directly between a gate of the first input transistor and a gate of the first load transistor.

Abstract: A circuit includes a first common mode amplifier including a first input, a second input, and a first output. The first common mode amplifier comprises a first plurality of self-biased differential amplifiers. The circuit also includes a second common mode amplifier including a third input, a fourth input, and a second output, The third input is connected to the second input and the fourth input is connected to the first input. The second common amplifier comprises a second plurality of self-biased differential amplifiers. The circuit further includes a first gain amplifier including a fifth input and a sixth input and a second gain amplifier including a seventh input and an eighth input. The first output is connected to the fifth and eight inputs and the second output is connected to the sixth and seventh inputs.

Abstract: Described is high-current drive class AB operational trans-conductance amplifier (OTA) output that can operate under low supply voltages (e.g., below 0.9 V) while maintaining desired functionality (e.g., reliable startup behavior, well-defined biasing currents, phase margins for improved stability) over a broad range of process, voltage, and temperature variations. The class AB OTA comprises a pre-amplifier stage, and a differential OTA output stage coupled to the pre-amplifier stage, wherein the differential OTA output stage comprises at least four folded cascode transistors.

Abstract: An output stage circuit of an operational amplifier, the operational amplifier, and a signal amplifying method applied to the operational amplifier are provided. The output stage circuit includes an inverting circuit and a compensation module. The inverting circuit is electrically connected to a gain stage circuit of the operational amplifier. The inverting circuit generates an output signal of the operational amplifier. The compensation module includes a first compensation circuit, including a first current providing path and a first suppression activation circuit. The first current providing path provides a first compensation current. The first suppression activation circuit conducts the first compensation current to the inverting circuit if a first compensation condition related to a first gain stage signal generated by the gain stage circuit is satisfied. Variation of the output signal is suppressed because of the first compensation current.

Abstract: A circuit that includes an input stage circuit and an output stage circuit is provided. The input stage circuit includes a differential pair circuit and two output current mirror circuits. The differential pair circuit operates according to a first voltage source to receive a first and a second input voltages and generate a first and a second output currents. The two output current mirror circuits operate according to a second voltage source to generate a first current mirror output current fed to an input stage output node according to the first output current and generate a second current mirror output current flowed from the input stage output node according to the second output current. The output stage circuit operates according to the second voltage source to receive an input voltage from the input stage output node to generate an output voltage.

Abstract: An integrated circuit includes at least one differential pair of transistors, a bias current generator that is configured to generate a bias current on a bias node that is coupled to a source terminal of each transistor of said differential pair by a respective resistive element. A compensation current generator is configured to generate a compensation current in one of the two resistive elements so as to compensate for a difference between actual values of the threshold voltages of the transistors of said differential pair.

Abstract: The differential difference amplifier circuit includes a differential input stage circuit, a loading stage circuit coupled to the differential input stage circuit, and an output stage circuit coupled to the loading stage circuit. The output stage circuit is configured to generate an output signal. The differential input stage circuit includes a first differential pair having a first transconductance and a second differential pair having a second transconductance. The first differential pair is biased by a first current source and receives a first input signal and the output signal. The second differential pair is biased by a second current source and receives a second input signal and the output signal. At least one of the first transconductance and the second transconductance is adjusted according to the image data.

Abstract: Modern modulator drivers must be capable of delivering a large output voltage into a tens of ohms modulator, while minimizing the amount of distortion added by the driver. The driver should deliver the output voltage without exceeding a maximum distortion while minimizing the DC power consumption. Accordingly, a modulator driver includes a final stage amplifier with auxiliary transistors that turn on when the conventional differential pair of transistors approaches their maximum voltage of the linear region of their transfer function, thereby providing a more linear transfer function, in particular at large input voltages.

Abstract: An amplifier circuit includes a first input unit, a second input unit, a first current supply unit, and a second current supply unit. The first input unit changes a voltage level of a first output node based on a first input signal. The second input unit changes a voltage level of a second output node based on a second input signal. The first current supply unit supplies a first current to the first output node based on a voltage level of the first output node and boosts the voltage level of the first output node for a predetermined time when the voltage level of the first output node is changed. The second current supply unit supplies a second current to the second output node based on the voltage level of the first output node.

Abstract: A differential amplifier circuit has a first current circuit comprising a first transistor and a second transistor, and to flow a current depending on a voltage of a first input signal, a second current circuit comprising a third transistor and a fourth transistor, and to flow a current depending on a voltage of a second input signal, a fifth transistor comprising a gate connected to a gate and the drain of the second transistor, and to flow a current that is M times greater than the current flowing between the drain and the source of the second transistor, and a sixth transistor comprising a gate connected to a gate and the drain of the fourth transistor and cascode-connected to the first transistor, and to flow a current that is N times greater than the current flowing between the drain and the source of the fourth transistor.

Abstract: Methods and devices addressing design of reconfigurable wideband LNAs to meet stringent gain, noise figure, and linearity requirements with multiple gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements, such as 5G NR radios. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed.

Abstract: Provided are an external compensation circuit and method, and display device in the field of display techniques. The external compensation circuit includes a regulation sub-circuit that may collect a driving current loaded to a light-emitting unit and a reference current from a reference current source, and regulate potentials at two nodes connected to a compensation sub-circuit according to the collected current, to enable the compensation sub-circuit to calibrate a data signal to be input to a pixel circuit according to a potential difference between the two nodes.

Abstract: A vacuum tube subwoofer extraction circuit system includes: a front-end circuit; and a vacuum tube subwoofer extraction circuit connected to the front-end circuit, the vacuum tube subwoofer extraction circuit including: a small signal amplification vacuum tube for receiving an input signal from the front-end circuit and outputting an audio signal; and a passive filtering circuit connected to the small signal amplification vacuum tube and adapted to perform a filtering process on the audio signal so as to output a filtered signal, wherein the front-end circuit includes a switch power circuit for providing low voltage to the vacuum tube subwoofer extraction circuit, wherein the small signal amplification vacuum tube does not have gain effect on the input signal.

Abstract: An amplifier circuit can be configured to receive a differential input signal having a common mode component that can extend to at least one power supply rail for the amplifier circuit. The amplifier circuit can include an input stage, such as having a first differential transistor pair, and the input stage can receive the differential input signal and in response conduct a differential first current to a cascode output stage. The cascode output stage can include or use a cascode control signal that is adjusted in response to the differential input signal. The cascode control signal can be independent of a transconductance of the first differential transistor pair. In an example, the amplifier circuit includes a slew boost circuit configured to source or sink current at an output of the amplifier based on a magnitude and polarity of the differential input signal.

Abstract: An operational amplifier is disclosed. The operational amplifier activates/couples either a first or a second differential pair of transistors to an input based on the input voltage. The first and second pair of transistors are each biased with a current having a first portion that is constant with temperature and a second portion that is proportional to temperature. By adjusting the ratios of the first and second portions, the transconductance of each differential pair may be made relatively constant with temperature. Each differential pair is coupled to a trim current source that is adjusted to reduce the voltage offset at each output. The resulting voltage offset for the operational amplifier is relatively constant over a range of input voltages and has temperature coefficient unaffected by the trimming process.

Abstract: Provided is an electronic circuit including a resonant circuit configured to output a resonance voltage having a resonance frequency to a first node, and an oscillation circuit configured to output an oscillation voltage having a level changed according to a first current and a second current based on the resonance voltage received from the first node, wherein the first current is delivered between a first voltage supply terminal and a second node in a first time period, the second current is delivered between the second node and a second voltage supply terminal in a second time period, and a sum of a length of the first time period and a length of the second time period corresponds to the resonance frequency.

Abstract: A servo-amplifier includes a first bipolar transistor, a second bipolar transistor, a cascode transistor, and a bias transistor. The second bipolar transistor includes an emitter terminal that is connected to an emitter terminal of the first bipolar transistor to form a differential amplifier. The cascode transistor includes a source terminal that is connected to a collector terminal of the first bipolar transistor. The bias transistor is coupled to the first bipolar transistor, the second bipolar transistor and the cascode transistor. The bias transistor is configured to generate a bias voltage to drive a gate terminal of the cascode transistor based on a voltage at a base terminal of the first bipolar transistor and a voltage at a base terminal of the second bipolar transistor. As a result, neither of the bipolar transistors enters a saturation region during transient or steady state operation.

Abstract: Disclosed examples include differential amplifier circuits and variable neutralization circuits for providing an adjustable neutralization impedance between an amplifier input node and an amplifier output node, including neutralization impedance T circuits with first and second impedance elements in series between the amplifier input and output, and a third impedance element, including a first terminal connected to a node between the first and second impedance elements, and a second terminal connected to a transistor. The transistor operates according to a control signal to control the neutralization impedance between the amplifier input node and the amplifier output node.

Abstract: Wideband signal buffers that can be employed for mmWave (millimeter wave) communication are disclosed. One example signal buffer comprises a variable gain amplifier (VGA) that receives two control words and outputs a feedback signal, wherein both an amplitude and a phase of the feedback signal are based on the two control words and on a bias voltage; and a matching network comprising a first inductor that outputs the bias voltage, a second inductor, and a third inductor that receives the feedback signal from the VGA, and wherein the first, second, and third inductors are magnetically coupled to each other, wherein the signal buffer is configured to receive a RF (Radio Frequency) input and to generate a RF output from the RF input based on a transfer function of the signal buffer, wherein the transfer function is based at least in part on the feedback signal.

Abstract: Systems and methods for mitigating occurrences of dynamic avalanche events are presented. An electrical system may include a gate-drive unit electrically coupled to a semiconductor switching device and used to drive the switching device by applying a voltage to a gate terminal of the switching device. The electrical system may also include a controller that indicates the switching device to turn off and determines system parameters in response to the switching device turning-off. The controller may determine an intermediate gate voltage based at least in part on the system parameters and may modify the gate-drive unit configuration to apply the appropriate intermediate gate voltage to the gate terminal. The controller may additionally modify the gate-drive unit configuration to apply a turn-off voltage at the gate terminal subsequent to the application of the intermediate gate voltage.

Abstract: A circuit includes a first common-source amplifier configured to receive a first voltage at a first gate node and output a first current to a first drain node in accordance with a first source voltage at a first source node; a second common-source amplifier configured to receive a second voltage at a second gate node and output a second current to a second drain node in accordance with a second source voltage at a second source node; a first diode-connected device configured to couple the first source node to a DC (direct current) node; a second diode-connected device configured to couple the second source node to the DC node; and a source-degenerating resistor inserted between the first source node and the second source node.

Abstract: An amplifier comprises eight transistors: the first coupled to a linked node and to a positive output node, the second coupled to the linked node and to a negative output node, the third coupled to the positive output node and a common potential, the fourth coupled to the negative output node and the common potential, the fifth coupled to a battery node, the sixth coupled to the fifth transistor and to the positive output node, the seventh coupled to the battery node, and the eighth coupled to the seventh transistor and to the negative output node. The amplifier also includes a charge pump to convert the battery voltage to an increased voltage on the linked node. The charge pump includes capacitors and operates at a lower frequency in lower power mode and a higher frequency in higher power mode to increase power provided to the linked node.

Abstract: An amplifier includes an input stage. The input stage includes a differential pair and a load circuit. The differential pair includes a first transistor and a second transistor. The first transistor and the second transistor are configured to amplify a received differential signal. The load circuit connects the differential pair to a reference voltage. The load circuit is configured to vary in resistance in inverse proportion to the transconductance of the first transistor and the second transistor.

Abstract: The present disclosure describes exemplary line drivers for use in an exemplary wireline transmission device. In some situations, the exemplary line drivers are electrically connected to a wireline communication channel to transmit information. The exemplary line drivers prevent charge sharing with the wireline communication channel. The exemplary line drivers disclosed herein charge various circuit nodes to various logical values, such as a logical zero or a logical one, to prevent charge sharing with the wireline communication channel.

Abstract: Disclosed herein are switching or other active field-effect transistor (FET) configurations that implement independently controlled main-auxiliary branch designs. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FET devices in parallel with a plurality of auxiliary FET devices. The circuit assembly can include a plurality of gate bias networks where each controls one or more of the main FET devices. The circuit assembly includes a second plurality of gate bias networks that each controls one or more of the auxiliary FET devices.

Abstract: A comparator circuitry includes an input pair circuit, a load circuit, and a compensation circuit. The input pair circuit is configured to compare a first input signal with a second input signal, in order to control a first bias current. The load circuit is coupled to the input pair circuit, and is configured to output an output signal having a first level from a first output terminal of the load circuit in response to the first bias current. The compensation circuit is coupled to the input pair circuit and the load circuit, and is configured to drain a compensation current from the first output terminal to a voltage source during the load circuit generates the output signal having a first level, in which the voltage source is configured to provide a voltage having a second level.

Abstract: Disclosed herein is an amplification circuit that outputs an output signal formed by amplifying a differential signal between a first input terminal and a second input terminal using an operating amplifier and a plurality of resistors, the amplification circuit including an adjustment circuit configured to adjust a frequency property of the output signal for an in-phase alternating current signal input between the first input terminal and the second input terminal. The adjustment circuit is connected to one input terminal of the first input terminal and the second input terminal through one or more resistors, the adjustment circuit includes a capacitor part whose capacitance is set to be variable, and the adjustment is realized through variable setting of the capacitance of the capacitor part.

Abstract: A voltage regulator having a buffer circuit and method for operating the same is disclosed. A voltage regulator having a buffer circuit includes an input stage coupled to receive an input voltage and an output stage configured to provide an output signal on an output node. The output stage includes first and second output transistors coupled to the output node. The circuit further includes a buffer stage coupled between the input and output stages. The buffer stage includes a first buffer transistor having a gate terminal coupled to the input stage and a source terminal coupled to a gate terminal of the first output transistor. The circuit further includes a first current mirror coupled to the first buffer transistor, and a second current mirror coupled to the first current mirror, the second current mirror including the second output transistor.

Abstract: Systems, methods and apparatus for practical realization of an integrated circuit comprising a stack of transistors operating as an RF amplifier are described. As stack height is increased, capacitance values of gate capacitors used to provide a desired distribution of an RF voltage at the output of the amplifier across the stack may decrease to values approaching parasitic/stray capacitance values present in the integrated circuit which may render the practical realization of the integrated circuit difficult. Coupling of an RF gate voltage at the gate of one transistor of the stack to a gate of a different transistor of the stack can allow for an increase in the capacitance value of the gate capacitor of the different transistor for obtaining an RF voltage at the gate of the different transistor according to the desired distribution.

Abstract: A digital-to-analog converter (DAC) capable of operating in radio frequency (RF) with linear output, low distortion, low power consumption, and input data independence. The DAC includes switch drivers and output switches driven by the switch drivers. The switch drivers include pairs of outputs, and positive feedback circuitries coupled between respective pairs of outputs. The output switches are arranged between a first current source configured to push current to the DAC's outputs and a second current source configured to pull current from the DAC's outputs. Different output switches are configured to push current to and pull current from the DAC's outputs in accordance with rising edges and falling edges, respectively.

Abstract: A system and a method for calibrating an antenna using trim bits and non-volatile memory is disclosed. In one aspect, an apparatus includes a power amplifier configured to at least amplify the output signal of the first antenna. The power amplifier includes multiple stages. The apparatus further includes a trim control circuit configured to adjust a bias of one of the stages of the power amplifier, using trim bits from non-volatile memory. The trim control circuit is further configured to scale the bias of one of the plurality of stages of the power amplifier by an integer between 0 and 2n?1 corresponding to a binary number formed by the first plurality of trim bits, wherein n corresponds to the number of trim bits.

Abstract: Various embodiments of the present technology may comprise methods and apparatus for an amplifier circuit. Methods and apparatus for an amplifier circuit according to various aspects of the present invention may comprise a first cross-connect circuit configured to receive an input signal at an input terminal and transmit the input signal to an input stage circuit. The amplifier circuit may further comprise a second cross-connect circuit connected between the input stage circuit and an output stage circuit, and a voltage adjustment circuit connected to the input stage circuit. Each cross-connect circuit may comprise a plurality of switches.

Abstract: Disclosed is a security device for preventing leakage of data information in solid-state drive. The present invention provides the security device for preventing leakage of data information in solid-state drive (SSD), the device enabling a user to electrically destroy flash memory personally to prevent leakage of data stored in the SSD, which is used and is to be waste-processed.

Abstract: An example of a signal switch includes a first transistor coupled between first and second nodes, a plurality of second transistors coupled in series between the first and second nodes, in parallel with the first transistor, a third transistor coupled between the first node and a third node, and a plurality of fourth transistors coupled in series between the first and third nodes, in parallel with the third transistor. The signal switch further includes a first shunt path including a first shunt transistor and a first inductor connected in series between a reference node and a first connection point between two of the plurality of second transistors, and a second shunt path including a second shunt transistor and a second inductor connected in series between the reference node and a second connection point between two of the plurality of fourth transistors.

Abstract: A pseudo-resistor structure, comprises: a first and a second PMOS transistor or PN diode configured as two-terminal devices, wherein the positive terminal of the first PMOS transistor or PN diode is connected to the positive terminal of the second PMOS transistor or PN diode, and wherein the negative terminal of the first PMOS transistor or PN diode is connected to an input (A) of the pseudo-resistor structure and wherein the negative terminal of the second PMOS transistor or PN diode is connected to an output (C) of the pseudo-resistor structure, and a dummy transistor or dummy diode connected to the input (A), wherein the dummy transistor or dummy diode is further connected to a bias voltage for compensating a leakage current through the first and the second PMOS transistors or PN diodes. A closed-loop operational amplifier circuit comprising the pseudo-resistor structure is provided. Also, a bio-potential sensor comprising the closed-loop operational amplifier circuit is provided.

Abstract: Embodiments of the present invention provide a system for real-time transmission of data associated with trigger events. The system is configured for identifying one or more priorities associated with a user, extract one or more triggers associated with the one or more priorities of the user, receiving an indication that at least one condition associated with at least one of the one or more triggers is met, determining that the user is performing one or more actions associated with at least one priority of the one or more priorities based receiving the indication, in response to determining that the user is performing the one or more actions associated with the at least one priority, dynamically extracting information associated with the user, and transmitting, in real-time, the extracted information associated with the user to at least one third party entity.

Abstract: A fingerprint sensing circuit and a fingerprint sensing apparatus are provided. The fingerprint sensing circuit includes a sensing electrode; a first converting circuit connected to the sensing electrode and configured to convert a coupling capacitance sensed by the sensing electrode into a drive voltage, where the drive voltage is equal to a sum of a voltage variation converted from the coupling capacitance and a reference voltage; and a second converting circuit configured to generate a sensing current based on the drive voltage, and send the sensing current to a fingerprint signal processor, where the sensing current is equal to a product of a transconductance gain of the second converting circuit and the voltage variation, and the fingerprint signal processor performs fingerprint sensing based on the sensing current. With the fingerprint sensing circuit and the fingerprint sensing apparatus, the detection accuracy can be improved.

Abstract: An electronic device may include a sensing circuit and a current subtraction circuit. The sensing circuit may output first and second current signals. The current subtraction circuit may mirror the first and second current signals onto first and second current branches. The second current branch may be split into a first sub-path and a second sub-path. An amplifier may control the amount of current flowing through the second sub-path by forcing the current flowing through the first current branch and the current flowing through the first sub-path to be identical. Configured in this way, the current flowing through the second sub-path will be equal to the difference between the first and second current signals. The current flowing through the second sub-path may be optionally amplified using another current mirror.

Abstract: Systems and methods for amplifying an input signal include amplifier circuitry, an itail connection coupled between a positive voltage circuitry and the negative voltage circuitry and operable to generate an itail voltage corresponding to a greater of the positive voltage input signal (Vp) and the negative voltage input signal (Vn), a first resistor rgp disposed to receive the itail voltage and a first voltage corresponding to Vp, and a second resistor rgn disposed to receive the itail voltage and a second voltage corresponding to Vn. A first current output node is coupled to the output of rgp and operable to output a positive output current (Ioutp) corresponding to the current flowing through rgp, and a second current output is coupled to the output of rgn and operable to output a negative output current (Ioutn) corresponding to the current flowing through rgn.

Abstract: A stable reference voltage that can be supplied in a layout area smaller than prior art is provided. A current-voltage convertor includes a first current mirror circuit including a first MOS transistor, a second MOS transistor in a pair, and an output resistor; and a depletion type N-channel MOS transistor, inserted between a first voltage to be input and the first MOS transistor and the second MOS transistor, and having a gate to which an output voltage from the output resistor is fed back. When a reference current is input to the first MOS transistor, the output voltage is generated by a current corresponding to the reference current flowing into the second MOS transistor and the output resistor. In addition, a reference voltage generator including the current-voltage convertor is provided to output a reference voltage based on the output voltage of the current-voltage convertor.

Abstract: The differential difference amplifier circuit includes a differential input stage circuit, a loading stage circuit coupled to the differential input stage circuit, and an output stage circuit coupled to the loading stage circuit. The output stage circuit is configured to generate an output signal. The differential input stage circuit includes a first differential pair having a first transconductance and a second differential pair having a second transconductance. The first differential pair is biased by a first current source and receives a first input signal and the output signal. The second differential pair is biased by a second current source and receives a second input signal and the output signal. At least one of the first transconductance and the second transconductance is adjusted according to the image data.

Abstract: Embodiments of the present disclosure provide a circuit structure. An error amplifier of the structure includes an input terminal coupled to a voltage source, a reference terminal, and an output terminal coupled to a back-gate terminal of a power amplifier. A voltage at the output terminal of the error amplifier indicates a voltage difference between the input terminal and the reference terminal. A logarithmic current source may be coupled to the reference terminal of the error amplifier, the logarithmic current being configured to generate a reference current logarithmically proportionate to a voltage level of the voltage source. A plurality of serially coupled transistor cells, having a shared substrate and coupled between the reference terminal of the error amplifier and ground, each may include a back-gate terminal coupled to the output terminal of the error amplifier.

Abstract: Various embodiments of the present technology comprise a method and apparatus for an operational amplifier with a variable gain-bandwidth product. According to various embodiments, an amplifier circuit comprising the operational amplifier operates in multiple stages and provides a low gain-bandwidth and a high gain-bandwidth.

Abstract: A voltage controlled oscillator includes a first inductor, a second inductor, a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, and an inductor-capacitor (LC) tank circuit. A first end of the first inductor and a first end of the second inductor are coupled to a first power rail. A drain node of the first MOS transistor is coupled to a second end of the first inductor. A drain node of the second MOS transistor is coupled to a second end of the second inductor. Source nodes of the first MOS transistor and the second MOS transistor are coupled to a second power rail. The LC tank circuit is coupled to gate nodes of the first MOS transistor and the second MOS transistor, wherein energy is magnetically pumped into the LC tank circuit through the first inductor and the second inductor.

Abstract: The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.