Having Gain Control Means Patents (Class 330/254)
  • Patent number: 10288674
    Abstract: A electrochemical or other sensor interface circuit architecture can deliver substantial DC offset bias to an electrochemical or other sensor separately or independently from delivering a time-varying AC excitation signal, which can then be provided with higher resolution, which, in turn, can allow better resolution of the measured response signal providing the impedance characteristic of sensor condition. For example, a differential time-varying AC excitation signal for the sensor condition characteristic can be delivered separately and independently from a differential stable (e.g., DC or other) bias signal, such as by using separate digital-to-analog converters (DACs), so that providing the more stable signal does not limit the resolution and accuracy of the time-varying signal, such as by using up the dynamic range of a single DAC.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: May 14, 2019
    Assignee: Analog Devices Global
    Inventors: GuangYang Qu, Junbiao Ding, Tony Yincai Liu, Shurong Gu, Yimiao Zhao, Hanqing Wang, Leicheng Chen
  • Patent number: 10263583
    Abstract: A variable gain amplifier capable of stabilizing an average output potential of a differential output signal, improving power efficiency over a wide range of an amplitude of the differential input signal, and suppressing deterioration of a distortion rate is provided. The variable gain amplifier includes an amplifying circuit configured to amplify a differential input signal with a gain according to a gain control signal, and a current control circuit. The amplifying circuit has a first current source supplying a source current. The current control circuit adjusts a magnitude of the source current of the first current source according to a magnitude of the gain control signal.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: April 16, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Naoki Itabashi
  • Patent number: 10250217
    Abstract: Each of a first high frequency power supply and a second high frequency power supply of a plasma processing apparatus is configured to selectively output a continuous wave, a modulated wave and a double-modulated wave. A first average value which determines an impedance at a load side of the first high frequency power supply and a second average value which determines an impedance at a load side of the second high frequency power supply are obtained by using any one of two averaging methods depending on a first high frequency power output from the first high frequency power supply and a second high frequency power output from the second high frequency power supply. An impedance matching of each of a first matching device and a second matching device is performed based on the first average value and the second average value.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: April 2, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koichi Nagami, Norikazu Yamada
  • Patent number: 10243531
    Abstract: A differential signal processing circuit includes a local common mode voltage control circuit for controlling a common mode voltage of an output differential signal generated by the differential signal processing circuit based on an external common mode control current generated by an external common mode voltage control circuit. The differential signal processing circuit, which may be configured as a variable gain amplifier (VGA) or a continuous time linear equalizer (CTLE), includes a pair of load devices, a pair of input transistors, and a pair of current source transistors coupled via separate paths between upper and lower voltage rails. The external control circuit includes a replica circuit including a replica load device, a replica input transistor, and a replica current source transistor. The external control circuit sets the replica common mode voltage to a target using a current, wherein the external common mode control current is based on that current.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: March 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Pradeep Thiagarajan, Xiaobin Yuan, Todd Morgan Rasmus
  • Patent number: 10243575
    Abstract: Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each input line to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2x where x ranges from 0 to m?1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than VADC_fs/128+VADC_fs/256+VADC_fs/512+VADC_fs/1024 when m equals 4 and where VADC_fs is the full-scale voltage of the ADC.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 26, 2019
    Assignee: Maxlinear, Inc.
    Inventors: Yongjian Tang, Hao Liu
  • Patent number: 10243664
    Abstract: An optical modulator driver circuit (1) includes an amplifier (50, Q10, Q11, R10-R13), and a current amount adjustment circuit (51) capable of adjusting a current amount of the amplifier (50) in accordance with a desired operation mode. The current amount adjustment circuit (51) includes at least two current sources (IS10) that are individually ON/OFF-controllable in accordance with a binary control signal representing the desired operation mode.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: March 26, 2019
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Munehiko Nagatani, Hideyuki Nosaka, Toshihiro Itoh, Koichi Murata, Hiroyuki Fukuyama, Takashi Saida, Shin Kamei, Hiroshi Yamazaki, Nobuhiro Kikuchi, Hiroshi Koizumi, Masafumi Nogawa, Hiroaki Katsurai, Hiroyuki Uzawa, Tomoyoshi Kataoka, Naoki Fujiwara, Hiroto Kawakami, Kengo Horikoshi, Yves Bouvier, Mikio Yoneyama, Shigeki Aisawa, Masahiro Suzuki
  • Patent number: 10218314
    Abstract: A power amplifier includes a common source amplifier and a common gate amplifier circuit. The common source amplifier circuit has a terminal connected to a radio frequency (RF) input terminal and uses a source terminal commonly as an input terminal and an output terminal of the power amplifier. The common gate amplifier circuit has a terminal connected to the common source amplifier circuit and another terminal connected to an RF output terminal, and uses a gate terminal commonly as the input terminal and the output terminal of the power amplifier. The common gate amplifier circuit includes a Doherty amplifier including a main power amplifier and an auxiliary power amplifier that is connected to the main power amplifier in parallel.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: February 26, 2019
    Assignees: Samsung Electro-Mechanics Co., Ltd., Korea Advanced Institute of Science and Technology
    Inventors: Yun Su Jin, Gyu Suck Kim, Song Cheol Hong
  • Patent number: 10193515
    Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the presentation provide a CTLE module that includes a two compensation sections. A high-frequency zero RC section is in the source of the differential pair and close to the bias current source. A low-frequency zero section is coupled to an output terminal and configured outside the input signal path. A DC gain tuning section is coupled to the low-frequency zero section. There are other embodiments as well.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: January 29, 2019
    Assignee: INPHI CORPORATION
    Inventors: Rajasekhar Nagulapalli, Simon Forey, Parmanand Mishra
  • Patent number: 10193507
    Abstract: A wide range differential current switching circuit can operate across a wide range of input currents and across a broad range of frequencies. A first differential current source can include a first transistor and a second transistor. The first transistor receives a switching signal and provides an output current and at output node. The second transistor receives an inverted switching signal, the first transistor and the second transistor coupled to each other at a tail node. A current source provides an input current to the tail node. A third transistor can provide a boost current to the tail node while the first transistor is off.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: January 29, 2019
    Assignee: Analog Devices Global
    Inventors: Celal Avci, Bilal Tarik Cavus
  • Patent number: 10084516
    Abstract: Methods for transmitting over a wireless channel from a plurality of transmit chains are provided, as well as apparatuses for performing the methods. Each transmit chain has a variable gain power amplifier coupled to an antenna element. A subset of at least two transmit chains is selected from the plurality of transmit chains. A gain of at least one of the variable gain power amplifiers is set in accordance with the modulation scheme. Respective beams are transmitted with each transmit chain in the subset. Each respective beam represents a component of a modulated signal according to a modulation scheme, so that the beams combine over the wireless channel to form the modulated signal.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: September 25, 2018
    Assignee: HUAWEI TECHNOLOGIES CANADA CO., LTD.
    Inventor: Tho Le-Ngoc
  • Patent number: 10084421
    Abstract: An instrumentation amplifier configured for providing high common mode rejection is described and includes an input differential stage configured to receive a differential input voltage and a folded cascode amplifying stage configured to receive output current mode signals provided from the input differential pair. A plurality of feedback networks is provided to improve the input stage. The amplifier may operate to provide an enhanced common mode rejection ratio of a single gain block in the instrumentation amplifier. In some examples, the circuitry may have a differential folded cascode amplifying stage which permits high precision and low distortion of amplified signals without degrading the common mode rejection ratio.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: September 25, 2018
    Assignee: Harman International Industries, Incorporated
    Inventors: Dimitri Danyuk, Todd A. Eichenbaum
  • Patent number: 10084419
    Abstract: An amplifier of an embodiment includes: a plurality of input transistors of a plurality of differential pairs; a plurality of first resistance circuits mutually connecting respective sources of the input transistors corresponding to the differential pairs and mutually connecting the respective sources and reference potential points; a plurality of second resistance circuits being connected between the respective sources of the plurality of input transistors and the reference potential points, respectively; and a control circuit configured to generate a control signal controlling whether or not to electrically connect the plurality of first resistance circuits and the plurality of second resistance circuits to the respective sources of the input transistors.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: September 25, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Shirane, Rui Ito, Toshiya Mitomo
  • Patent number: 10084422
    Abstract: An integrated circuit and method for providing a variable gain amplifier are disclosed. One embodiment of the a variable gain amplifier comprises at least one load, a cascode circuit coupled to the load, a folded-gilbert stage, coupled to the cascode circuit, the folded-gilbert stage comprising a main differential pair of transistors and an internal pair of transistors, and a digital to analog converter, coupled to the folded-gilbert stage, for steering currents between the main differential pair of transistors and the internal pair of transistors to change a gain of the variable gain amplifier.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: September 25, 2018
    Assignee: XILINX, INC.
    Inventor: Mohamed N. Elzeftawi
  • Patent number: 10075307
    Abstract: An adjustable signal equalization device includes an equalizer circuitry, an analog-to-digital converter (ADC), a calculation circuitry, and a comparator circuitry. The equalizer circuitry has a transfer function, and processes an input signal based on the transfer function to generate an output signal. The ADC generates a digital signal according to the output signal. The calculation circuitry performs an accumulation according to the first digital signal to generate a first accumulated value and a second accumulated value, and generates a first detection signal and a second detection signal according to the first accumulated value and the second accumulated value. The comparator circuitry compares the first detection signal with the second detection signal to output a control signal to the equalizer circuit if the first detection signal is different from the second detection signal, in order to adjust the transfer function.
    Type: Grant
    Filed: January 1, 2018
    Date of Patent: September 11, 2018
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Juh Kang, Yu-Chu Chen, Chen-Yang Pan
  • Patent number: 10024818
    Abstract: An ionic current sensor array includes a master bias generator and a plurality of sensing cells. The master bias generator is configured to generate a bias voltage. Each sensing cell includes an ionic current sensor, an integrating capacitor, a sense transistor coupled between the integrating capacitor and the ionic current sensor, and an amplifier coupled to provide a reference voltage to bias the ionic current sensor. The amplifier includes a first transistor and a second transistor. The first transistor is coupled to receive the bias voltage, and the second transistor is coupled to the first transistor to provide the reference voltage to the ionic current sensor. The second transistor is also coupled between a source of the sense transistor and the gate of the sense transistor.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: July 17, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Vladimir Aparin, Bo Sun, Joung Won Park
  • Patent number: 10027297
    Abstract: One aspect of the present disclosure relates to a method for operating an amplifier, the amplifier including a variable resistor coupled between a source of a first input transistor and a source of a second input transistors, and a variable capacitor coupled between the source of the first input transistor and the source of the second input transistor. The method includes adjusting a resistance of the variable resistor to adjust a low-frequency gain of the amplifier, and adjusting a capacitance of the variable capacitor in an opposite direction as the adjustment to the resistance of the variable resistor.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: July 17, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaobin Yuan, Jacob Lee Dahle, Mangal Prasad, Joseph Natonio
  • Patent number: 10014834
    Abstract: An embodiment circuit includes a first voltage divider coupled between a first voltage level and a ground potential. The circuit further includes an error amplifier having a first input terminal coupled to a node between a first resistive element and a second resistive element of the first voltage divider. The circuit further includes a second voltage divider coupled between a second voltage level and a reference voltage, wherein a second input terminal of the error amplifier is coupled to a node between a third resistive element and a fourth resistive element of the second voltage divider, and wherein an output voltage of the error amplifier is configured to control a potential difference between the first voltage level and the second voltage level.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: July 3, 2018
    Assignee: STMICROELECTRONICS (ALPS) SAS
    Inventors: Vratislav Michal, Denis Cottin, Patrik Arno, Nicolas Marty
  • Patent number: 10009034
    Abstract: Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each of two input lines to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2x where x ranges from 0 to m?1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than VADC_fs/128+VADC_fs/256+VADC_fs/512+VADC_fs/1024 when m equals 4 and where VADC_fs is the full-scale voltage of the ADC.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: June 26, 2018
    Assignee: Maxlinear, Inc.
    Inventors: Yongjian Tang, Hao Liu
  • Patent number: 9966907
    Abstract: A method and apparatus for high-speed clipping and recovery in an amplifier circuit is disclosed. In one embodiment, a circuit includes an amplifier configured to amplify an incoming signal. The amplifier includes inverting and non-inverting inputs, and is configured to provide a differential output. An output limiting circuit is coupled across the differential output, and is configured to limit an amplitude of an output signal provided on the differential output responsive to an input signal exceeding a first amplitude threshold. An input limiting circuit is coupled between the inverting input and the non-inverting input of the amplifier. Responsive to the input signal exceeding a second amplitude threshold (greater than the first), the input limiting circuit is configured to limit the amplitude of the output signal.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: May 8, 2018
    Assignee: Apple Inc.
    Inventors: Vahid Majidzadeh Bafar, Ashkan Borna, Mansour Keramat
  • Patent number: 9966908
    Abstract: A circuit for implementing a differential input receiver is described. The circuit comprises an input circuit having a first input node and a second input node configured to receive a differential input signal; a first output circuit having a first capacitor coupled between the first input node and a first output node and a second capacitor coupled between the second input node and a second output node, wherein the first output circuit generates an output signal at the first output and the second output when the input signal is in a first frequency range; and a second output circuit comprising an amplifier having a first amplifier input coupled to the first input node and a second amplifier input coupled to the second input node, wherein the second output circuit generates an output signal when the input signal is in a second frequency range which extends lower than the first frequency range. A method of implementing a differential input receiver is also described.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: May 8, 2018
    Assignee: XILINX, INC.
    Inventor: Declan Carey
  • Patent number: 9954503
    Abstract: A differential amplification circuit includes: a first transistor and a second transistor of a differential pair; first and second loads; current sources; and a resistor circuit, wherein the resistor circuit includes: a coarse adjustment part and a fine adjustment part, one of the coarse adjustment part and the fine adjustment part includes a first lateral adjustment part and a second lateral adjustment part which have the same configuration, the first lateral adjustment part and the second lateral adjustment part are connected symmetrically to both sides of a central adjustment part, and the central adjustment part has a circuit configuration symmetrical with respect to two connection nodes with the first lateral adjustment part and the second lateral adjustment part.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: April 24, 2018
    Assignee: SOCIONEXT INC.
    Inventor: Tomoyuki Arai
  • Patent number: 9948255
    Abstract: Provided is an amplification circuit that amplifies an input signal and outputs an amplified signal. The amplification circuit includes: an amplification element that outputs the amplified signal from an output terminal thereof; an inductor having one end to which a power supply voltage is supplied and another end that is connected to the output terminal of the amplification element; a variable resistor that is connected in parallel with the inductor; and a resistance value adjusting circuit that adjusts a resistance value of the variable resistor in accordance with the temperature.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: April 17, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Makoto Tabei, Daisuke Watanabe
  • Patent number: 9948244
    Abstract: An amplifier with adjustable gain including a plurality of differential amplifiers and an output stage circuit is provided. Each of the differential amplifiers has at least one differential pair, two current terminals of each of the differential pairs are coupled by a connection structure, and the connection structure provides a negative feedback resistance. The differential amplifiers commonly receive a differential input signal pair, and output terminals of the differential amplifiers are coupled together. The output stage circuit inverts a voltage on the output terminals of the differential amplifiers to generate an output voltage. A direct current gain of the amplifier with adjustable gain is determined by adjusting at least one of working numbers of the differential amplifiers and the differential pairs.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: April 17, 2018
    Assignee: Faraday Technology Corp.
    Inventor: Chih-Huang Lin
  • Patent number: 9893693
    Abstract: A mobile device comprising an antenna, a receiver coupled to the antenna, and a transmitter coupled to the antenna, wherein the receiver, the transmitter, or both comprise a low noise amplifier comprising an adjustable gain and a variable impedance controller, and wherein the low noise amplifier is configured to sink current and to adjust a shunt resistance substantially simultaneously. Included is a method comprising receiving an electrical signal, substantially simultaneously adjusting an input impedance and a gain factor, amplifying the electrical signal, thereby producing an amplified signal, and outputting the amplified signal.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: February 13, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Ping Yin, Robert Grant Irvine, Chengfang Liao, Zhihang Zhang
  • Patent number: 9882532
    Abstract: The present disclosure provides a detailed description of techniques for implementing a linear amplifier with extended linear output range. More specifically, the present disclosure discloses techniques for extending the output signal range of a linear amplifier with a minimum increase in power consumption and die area consumption. Some embodiments facilitate coupling boost amplifiers with adjustable independent biasing to a main amplifier to boost the output signal near the non-linear regions of the transfer curve to extend the linear range. Certain embodiments comprise a first boost amplifier biased to contribute to the output signal when the input signal is near a negative threshold voltage, and a second boost amplifier biased to contribute to the output signal when the input signal is near a positive threshold voltage. In certain embodiments, the threshold voltages and/or the bias currents can be controlled to adjust certain amplifier attributes.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: January 30, 2018
    Assignee: INPHI CORPORATION
    Inventors: Ariel Leonardo Vera Villarroel, Subramaniam Shankar, Steffen O. Nielsen, Carl Pobanz
  • Patent number: 9866179
    Abstract: The present disclosure relates to methods and systems for LNAs with high linearity and low noise for wideband receivers that receive high dynamic range signals. A multi-stage multipath LNA is disclosed in which outputs from various stages are amplified with variable gains and combined in parallel. A smart gain control unit evaluates the noise and non-linearity characteristics associated with each gain stage to configure the variable gains for the various stages to generate an overall LNA gain that minimizes the overall noise and/or non-linearity characteristics of the LNA while ensuring that the overall gain for the LNA satisfies the desired gain. The variable gains may be configured to change smoothly over the dynamic range of the input signal. Noise is minimized by reducing additional gain stages and by the smooth change in gain when switching between stages. High linearity performance is maintained by minimizing the number of gain stages combined.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: January 9, 2018
    Assignee: SiTune Corporation
    Inventors: Saeid Mehrmanesh, Vahid M. Toosi, Marzieh Veyseh
  • Patent number: 9847758
    Abstract: A low noise amplifier includes: first and seventh transistors configured to respectively receive first and second input signals; second, third, and fifth transistors connected to the first transistor; eighth, ninth, and eleventh transistors connected to the seventh transistor; a third resistive element; fourth and tenth transistors respectively connected to the third and ninth transistors; sixth and twelfth transistors respectively connected to second and first output terminals; and first and second resistive elements.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: December 19, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Takahiro Bokui, Hiroshi Kimura
  • Patent number: 9785177
    Abstract: In an embodiment, an electronic device includes a first amplifier having a non-inverting input configured to receive a reference voltage and an inverting input coupled to a first output node, where the first amplifier is configured to produce a first output voltage at the first output node. The electronic device also includes a second amplifier having a non-inverting input coupled to a ground reference level, and an inverting input coupled to the first output node via a first resistor and to a second output node via a second resistor, where the second amplifier is configured to produce a second output voltage at the second output node.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: October 10, 2017
    Assignee: NXP USA, Inc.
    Inventors: Ricardo Coimbra, Javier Mauricio Olarte Gonzalez
  • Patent number: 9787263
    Abstract: An analog differential amplifier circuit, such as an operational transconductance amplifier (OTA), with input offset correction capability. First and second analog floating gate (AFG) devices each include a trim transistor connected in parallel with a series transistor in first and second input legs, respectively, of the amplifier. Floating gate electrodes in the AFG devices are differentially programmed to correct for error in the output signal in response to zero input differential voltage at its inputs. Temperature stability is attained by programming the floating gate electrodes to gate voltages above the floating gate transistors. In one embodiment, the AFG devices each include a second trim transistor sharing the same floating gate electrode; the sum of the currents conducted by the second trim transistors is added, by way of a current mirror, to the tail current applied to the first and second input legs.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: October 10, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ujas Natvarlal Patel, Andrew Marshall, Harvey J. Stiegler, Keith M. Jarreau
  • Patent number: 9780799
    Abstract: Methods and systems for an analog-to-digital converter (ADC) with constant common mode voltage may include in an ADC comprising a sampling switch on a first input line to the ADC, a sampling switch on a second input line to the ADC, N switched capacitor pairs and M single switched capacitors on the first input line, and N switched capacitor pairs and M single switched capacitors on the second input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the switched capacitor pairs between a reference voltage (Vref) and ground based on the compared voltage levels, and iteratively switching the single switched capacitors between ground and voltages that are a fraction of Vref, which may equal Vref/2x where x ranges from 0 to m?1 and m is a number of single switched capacitors per input line.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: October 3, 2017
    Assignee: Maxlinear, Inc.
    Inventors: Yongjian Tang, Hao Liu
  • Patent number: 9755597
    Abstract: An instrumentation amplifier includes first and second resistors for gain setting. The operational amplifiers within the instrumentation amplifier include selectively enabled current drive sources coupled to the amplifier output. The first and second resistors have variable resistances. A control circuit is configured to select the variable resistances of the first and second resistors to implement a fixed gain for the instrumentation amplifier and further selectively enable the current drive sources. The control circuit receives an indication of a downstream programmable gain (for example, from a downstream programmable gain amplifier). The variable resistances of the first and second resistors are selected to be scaled inversely with respect to the downstream programmable gain and the current drive sources are enabled proportionately with respect to the downstream programmable gain.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: September 5, 2017
    Assignee: STMicroelectronics, Inc.
    Inventor: Davy Choi
  • Patent number: 9755603
    Abstract: Some embodiments relate to a method and circuit for gain compensation. The method includes detecting a strength of an output signal generated by a power amplifier of a transmitter in response to a commanded transmission signal. The method also includes comparing the detected strength of the output signal to a delayed version of a detected strength of the commanded transmission signal to obtain an error signal. The method further includes compensating for gain drop of the output signal by adjusting a gain of the transmitter based on the error signal.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: September 5, 2017
    Assignee: MediaTek Inc.
    Inventors: Keng Leong Fong, YuenHui Chee
  • Patent number: 9755602
    Abstract: A system has a baseband gain stage to receive incoming in-phase and quadrature voltage signals and output in-phase and quadrature current signals, a mixer core arranged to receive the in-phase and quadrature current signals and output radio frequency signals, and a variable gain amplifier to receive the radio frequency signals and produce a broadband radio signal.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: September 5, 2017
    Assignees: ANALOG DEVICES TECHNOLOGY, ANALOG DEVICES, INC.
    Inventors: Eberhard Brunner, Jeff Venuti
  • Patent number: 9729117
    Abstract: A system that utilizes an amplified signal is disclosed that includes a plurality of first switches coupled to a plurality of first impedances. A plurality of second switches coupled to a plurality of second impedances. An amplifier having a first input coupled to the plurality of first switches and a second input coupled to the plurality of second switches. A leakage current offset source coupled to the first input of the amplifier, wherein the leakage current offset source cancels a leakage current component of a first current provided from the plurality of first switches to the first input.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: August 8, 2017
    Assignee: Conexant Systems, LLC
    Inventor: Chandrashekar Reddy
  • Patent number: 9722545
    Abstract: Provided is an emphasis circuit capable of obtaining a desired emphasis amount with which waveform deterioration of an output signal in a high frequency band (high frequency band deterioration) is suppressed without increasing power consumption (current consumption). In the emphasis circuit, a baseband amplifier section and a peaking amplifier section are connected in parallel to each other, and respective drive current setting sections are adjusted to adjust respective drive current values thereof so that the sum of the drive current value of the baseband amplifier section and the drive current value of the peaking amplifier section may be constant.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: August 1, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Satoshi Yoshima, Masaki Noda, Masamichi Nogami
  • Patent number: 9722849
    Abstract: Gain variations during a packet can lead to significant performance degradation in communications systems that use high order quadrature amplitude modulation (QAM). A method and the associated apparatus track such variations in an OFDM system and completely eliminate any performance degradation. Gain estimation and compensation is employed with the use of pilot subcarriers in the payload of an OFDM data packet. Estimated pilot magnitude ratios are averaged, throughout the processing life of a packet, to yield accurate gain estimations. A gain compensation factor is used to adjust data carriers. An exclusion method is also employed to eliminate pilot carriers which contribute to noise.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: August 1, 2017
    Assignee: Edgewater Wireless Systems Inc.
    Inventors: Manish Bhardwaj, Garret Shih
  • Patent number: 9719860
    Abstract: A power device temperature monitor is provided. The power device temperature monitor includes a power device having a control terminal and an output terminal, where the output terminal is configured to output a current as directed by a voltage of the control terminal. The power device temperature monitor includes an inductor coupled to the output terminal of the power device and an amplifier coupled to the inductor. The power device temperature monitor includes a computing device that receives an output of the amplifier, the computing device is configured to derive a temperature of the power device based upon the output of the amplifier.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: August 1, 2017
    Assignee: Atieva, Inc.
    Inventor: Yifan Tang
  • Patent number: 9712123
    Abstract: Provided is a power amplifier installed in wireless communication terminals and systems. According to one aspect of the present invention, a reconfigurable power amplifier capable of selecting a wide band frequency is provided. The reconfigurable power amplifier includes input transistors receiving a radio frequency (RF) signal and a reconfigurable adaptive power cell configured to select the wide band frequency by applying a common-gate bias voltage to a plurality of common-gate transistors with a plurality of separate common gates to amplify the RF signal.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: July 18, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Min Park, Baek-Hyun Kim, Cheon-Soo Kim, Song-Cheol Hong, Dong-Woo Kang, Jang-Hong Choi
  • Patent number: 9685914
    Abstract: A differential signal is input to a pair of gates of a differential pair, a differential signal generated by a load circuit connected to drains of the differential pair is amplified by a differential amplifier stage, and the amplified differential signal is fed back to a pair of sources of the differential pair via a feedback circuit. It is possible to maintain a high input impedance in the pair of gates of the differential pair while not being influenced by a gain of negative feedback of an amplifier circuit, and it is possible to perform amplification in an input stage by using a pair of a first transistor and a second transistor of the differential pair. Therefore, compared with the related art, it is possible to decrease the number of transistors in the input stage and to reduce a flicker noise.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: June 20, 2017
    Assignee: ALPS ELECTRIC CO., LTD.
    Inventors: Kiyoshi Sasai, Akira Asao
  • Patent number: 9685920
    Abstract: A reconfigurable operational amplifier includes: a first signal input terminal; a second signal input terminal; an output terminal; an operational amplifier having a non-inverting input, an inverting input, and an output; a negative feedback circuit path from the output of the operational amplifier to the inverting input of the operational amplifier; a first input circuit path from the first signal input terminal to the non-inverting input of the operational amplifier; a second input circuit path from the second signal input terminal to the inverting input of the operational amplifier; an output circuit path from the output of the operational amplifier to the output terminal; and logic units, wherein one or more of the logic units are provided in at least one of the negative feedback circuit path, the first input circuit path, the second input circuit path, and the output circuit path.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: June 20, 2017
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Hideaki Yoshida, Mitsunori Katsu, Hiroyuki Kozutsumi
  • Patent number: 9667211
    Abstract: A circuit includes an electrical gain element, a variable reactance element, and a controller. The electrical gain element is arranged to receive and change an amplitude of a signal over a set frequency range. The variable reactance element is connected to the electrical gain element. The controller is configured to control the variable reactance element to have a reactance such that the electrical gain element has a set gain slope as a function of signal frequency over the set frequency range.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: May 30, 2017
    Assignee: Rockwell Collins, Inc.
    Inventors: Russell D. Wyse, Michael L. Hageman
  • Patent number: 9660589
    Abstract: A power amplifier module includes an amplifier transistor and a bias circuit. A first power supply voltage based on a first operation mode or a second power supply voltage based on a second operation mode is supplied to the amplifier transistor. The amplifier transistor receives a first signal and outputs a second signal obtained by amplifying the first signal. The bias circuit supplies a bias current to the amplifier transistor. The bias circuit includes first and second resistors and first and second transistors. The first transistor is connected in series with the first resistor and is turned ON by a first bias control voltage which is supplied when the first operation mode is used. The second transistor is connected in series with the second resistor and is turned ON by a second bias control voltage which is supplied when the second operation mode is used.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: May 23, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masao Kondo, Hidetoshi Matsumoto
  • Patent number: 9660601
    Abstract: An amplifier includes a differential amplifier and a compensator. A differential amplifier includes a current source and paired transistors. The paired transistors generate an output signal by dividing a source current supplied by the current source into emitter currents of the paired transistors in response to a difference between an input signal and a reference signal. A compensator includes an amplifying transistor and a feedback circuit that feeds a collector current output from a collector of the amplifying transistor back to a base of the amplifying transistor therethrough. The compensator generates the reference signal at a base of the amplifying transistor. The compensator decreases power consumption of the amplifying transistor when the collector current increases, and increases the power consumption of the amplifying transistor when the collector current decreases. The compensator suppresses a peaking of gain in a low frequency band.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: May 23, 2017
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keiji Tanaka, Yoshiyuki Sugimoto
  • Patent number: 9628036
    Abstract: Apparatuses and methods are described where input signals are supplied to a translinear mesh. In some embodiments an output of the translinear mesh is regulated to a desired value.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: April 18, 2017
    Assignee: Infineon Technologies AG
    Inventors: Dieter Draxelmayr, Simone Fabbro
  • Patent number: 9614527
    Abstract: A circuit may include a signal converter configured to convert a differential signal to a single-ended signal. The circuit may also include a biasing circuit configured to set a bias of the signal converter based on a feedback of the single-ended signal such that a voltage level of the single-ended signal is at a target voltage level.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: April 4, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Pradip Thachile
  • Patent number: 9595937
    Abstract: Disclosed examples include a programmable attenuator circuit providing selective cross coupling of impedance components between circuit input nodes and output nodes according to control signals to set or adjust an attenuation value of the attenuator circuit. The attenuator circuit includes a plurality of attenuator impedance components, and a switching circuit to selectively connect at least a first attenuator impedance component between the first input node and the second output node, to selectively connect at least a second attenuator impedance component between the second input node and the first output node, to selectively connect a third attenuator impedance component between the first input node and the first output node, and to selectively connect a fourth attenuator impedance component between the second input node and the second output node.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: March 14, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Rajendrakumar Joish
  • Patent number: 9590607
    Abstract: An input buffer circuit comprising: a first current source; a first differential control circuit, configured to generate a first bias voltage at the first couple terminal according to the input signals, and configured to generate first control signals according to the input signals; a second current source; a second differential control circuit, configured to generate a second bias voltage at the second couple terminal according to the input signals, and configured to generate second control signals according to the input signals; a third current source, configured to provide a first current according to the second bias voltage; a first differential output circuit, configured to receive the first control signals to generate output signals; a fourth current source, configured to drain a second current according to the first bias voltage; and a second differential output circuit, configured to receive the second control signals to generate the output signal.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: March 7, 2017
    Assignee: MEDIATEK INC.
    Inventors: Bo-Jyun Kuo, An-Siou Li
  • Patent number: 9578416
    Abstract: A control signal is generated for mechanical loudspeaker protection, or for other signal pre-processing functions. The procedure contains the following steps: perform a non-linearity analysis based on current and voltage measurements; use the results of the non-linearity analysis, and the voltage and current measurements to control audio processing for the loudspeaker thereby to implement loudspeaker protection and/or acoustic signal processing.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: February 21, 2017
    Assignee: NXP B.V.
    Inventor: Temujin Gautama
  • Patent number: 9575473
    Abstract: An integrated circuit includes a motor current input voltage-to-current (VI) converter that receives a motor current sensor voltage from a motor and a reference voltage to generate an output current related to a motor's current. A motor current calibration VI converter compensates for errors in the motor current input VI converter and generates a calibration output current based on the reference voltage, wherein the output current and the calibration output current are combined to form an estimate of the motor's current.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: February 21, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Qunying Li, Juergen Luebbe, Robert E. Whyte, Jr.
  • Patent number: 9548700
    Abstract: There is provided an output stage comprising: a phase splitter for receiving an input signal and for generating first and second drive signals of opposite phase in dependence thereon; a DC offset signal generator for generating a DC offset signal; an adder for adding the DC offset signal to the first drive signal to provide a first modified drive signal; a subtractor for subtracting the DC offset signal from the second drive signal to provide a second modified drive signal; a first drive transistor associated with a first power supply voltage, for generating a first output signal in dependence on the first modified drive signal; a second drive transistor associated with a second power supply voltage, for generating a second output signal in dependence on the second modified drive signal; and a combiner for combining the first and second output signals to generate a phase combined output signal.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: January 17, 2017
    Assignee: SnapTrack, Inc.
    Inventors: Gerard Wimpenny, Martin Paul Wilson