Having Gain Control Means Patents (Class 330/254)
  • Patent number: 11349463
    Abstract: A wideband buffer circuit and a wideband communication circuit that uses the wideband buffer circuit. The wideband buffer circuit includes first and second transistors deployed as a voltage buffer and connected to first and second input terminals, first and second parallel resistor-capacitor pairs connected to the first and second transistors, first and second cross-coupled transistors connected to the first and second parallel resistor-capacitor pairs and connected to first and second output terminals, and first and second current sources connected to the first and second cross-coupled transistors and a fixed voltage. The first transistor, the first parallel resistor-capacitor pair, the first cross-coupled transistor and the first current source are connected in series. The second transistor, the second parallel resistor-capacitor pair, the second cross-coupled transistor and the second current source are connected in series.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: May 31, 2022
    Assignee: NXP B.V.
    Inventors: Siamak Delshadpour, Xu Zhang
  • Patent number: 11316601
    Abstract: An apparatus for transmitting broadcasting signal using transmitter identification scaled by 4-bit injection level code and method using the same are disclosed. An apparatus for transmitting broadcasting signal according to an embodiment of the present invention includes a waveform generator configured to generate a host broadcasting signal; a transmitter identification signal generator configured to generate a transmitter identification signal for identifying a transmitter, the transmitter identification signal scaled by an injection level code; and a combiner configured to inject the transmitter identification signal into the host broadcasting signal in a time domain so that the transmitter identification signal is transmitted synchronously with the host broadcasting signal.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: April 26, 2022
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11309845
    Abstract: In optical receivers, extending the transimpedance amplifier's (TIA) dynamic range is a key to increasing the receiver's dynamic range, and therefore increase the channel capacity. Ideally, the TIA requires controllable gain, whereby the receiver can modify the characteristics of the TIA and/or the VGA to process high power incoming signals with a defined maximum distortion, and low power incoming signals with a defined maximum noise. A solution to the problem is to provide TIA's with reconfigurable feedback resistors, which are adjustable based on the level of power, e.g. current, generated by the photodetector, and variable load resistors, which are adjustable based on the change in impedance caused by the change in the feedback resistor.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: April 19, 2022
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Ariel Leonardo Vera Villarroel, Abdelrahman Ahmed, Alexander Rylyakov
  • Patent number: 11296667
    Abstract: Embodiments of a linear equalizer are disclosed. In an embodiment, a linear equalizer includes a plurality of input transistors, a plurality of gain control transistors and first and second impedance elements. The plurality of input transistors is connected to input terminals of the linear equalizer to receive input signals. The plurality of gain control transistors is connected between a supply voltage and the plurality of input transistors. The plurality of gain control transistors is also connected to gain control terminals to receive gain control signals. At least some of the gain control transistors are connected to output terminals of the linear equalizer to transmit output signals. The first and second impedance elements are connected between at least some of the input transistors and at least one fixed voltage. A peaking gain of the linear equalizer is defined by gain control signals applied to the gain control terminals.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: April 5, 2022
    Assignee: NXP B.V.
    Inventor: Siamak Delshadpour
  • Patent number: 11275428
    Abstract: The present application provides a capacitance detection circuit, which could reduce the influence of screen noise on capacitance detection. The capacitance detection circuit includes: an amplification circuit connected to the capacitor to be detected, and configured to convert a capacitance signal of the capacitor to be detected into a voltage signal, the voltage signal being associated with the capacitance of the capacitor to be detected; and a control circuit connected to the amplification circuit, and configured to control an amplification factor of the amplification circuit to be a first amplification factor in a first period, and to control the amplification factor of the amplification circuit to be a second amplification factor in a second period, where noise generated by the screen in the first period is less than noise generated by the screen in the second period, and the first amplification factor is greater than the second amplification factor.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: March 15, 2022
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Guangkai Yuan, Guopao Li, Zhi Yao, Guanliang Liao
  • Patent number: 11277108
    Abstract: An example VGA includes a transistor arrangement having a plurality of transistors configured to realize one or more gain step circuits of the VGA, and a cross-couple switching arrangement having a plurality of switches configured to selectively change the coupling of the terminals of at least some of the transistors depending on whether a given gain step circuit is supposed to be in an ON state or in an OFF state. Using the cross-couple switching arrangement advantageously allows keeping all of the transistors ON at all times during operation and changing the coupling of some transistor terminals to either realize an in-phase addition of currents flowing through various transistors to apply the maximum gain or realize a subtraction of currents to apply the minimum gain. Such a VGA may be inherently wideband, enabling a highly linear, wideband operation without having to resort to significant trade-offs with other performance parameters.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: March 15, 2022
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Yahia Z. M. Ibrahim, Mohamed Ahmed Youssef Abdalla
  • Patent number: 11277106
    Abstract: A multi-stage transimpedance amplifier (TIA) with an adjustable input linear range is disclosed. The TIA includes a first stage, configured to convert a single-ended current signal from an optical sensor of a receiver signal chain to a single-ended voltage signal, and a second stage, configured to convert the single-ended voltage signal provided by the first stage to a differential signal. In such a TIA, the input linear range may be adjusted using a clamp that is programmable with an output offset current to keep the second stage of the TIA from overloading and to maintain a linear transfer function without compression.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: March 15, 2022
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Joseph Adut, Jeremy Wong, Eugene Cheung, Brian Hamilton, Gregory Fung
  • Patent number: 11258304
    Abstract: A device configured for wireless power transfer includes a digital controller configured to generate a plurality of switch control signals, and a transceiver configured to generate a wireless signal for the wireless power transfer. The transceiver includes a plurality of switches, each switch of the plurality of switches being responsive to a respective switch control signal of the plurality of switch control signals such that the wireless signal has a waveform shaped in accordance with a code sequence for the wireless power transfer. The code sequence is one of a set of predetermined code sequences, each predetermined code sequence being orthogonal to each other predetermined code sequence of the set of predetermined code sequences.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: February 22, 2022
    Assignee: The Regents of the University of Michigan
    Inventors: Al-Thaddeus Avestruz, Akshay Sarin
  • Patent number: 11245366
    Abstract: Distributed amplifiers with controllable linearization are provided herein. In certain embodiments, a distributed amplifier includes a differential input transmission line, a differential output transmission line, and a plurality of differential distributed amplifier stages connected between the differential input transmission line and the differential output transmission line at different points or nodes. The distributed amplifier further includes a differential non-linearity cancellation stage connected between the differential input transmission line and the differential output transmission line and providing signal inversion relative to the differential distributed amplifier stages. The differential non-linearity cancellation stage operates with a separately controllable bias from the differential distributed amplifier stages, thereby providing a mechanism to control the linearity of the distributed amplifier.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: February 8, 2022
    Assignee: Analog Devices, Inc.
    Inventor: Jonathan Xiang Wu
  • Patent number: 11233482
    Abstract: A receiver front-end includes a first peaking gain stage configured to amplify a received differential pair of signals received on an input differential pair of nodes. The first peaking gain stage has a first frequency response including a first peak gain at or near a carrier frequency in a first pass band. The first peak gain occurs just prior to a first cutoff frequency. A second peaking gain stage is configured to amplify a differential pair of signals generated by the first peaking gain stage. The second peaking gain stage has a high input impedance and a second frequency response including a second peak gain at or near the carrier frequency in a second pass band. The second peak gain occurs just prior to a second cutoff frequency. The first peaking gain stage and the second peaking gain stage have a cascaded peak gain at or near the carrier frequency.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: January 25, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventor: Mohammad Al-Shyoukh
  • Patent number: 11228293
    Abstract: A differential amplifier circuit includes: a control current source supplying a control current; paired bipolar transistors; an a variable resistance circuit including: a series circuit of a first resistor and a second resistor having an identical resistance, the series circuit electrically connected between a first terminal and a second terminal of the variable resistance circuit; a first field effect transistor (FET) having a source and a drain being electrically connected to emitters of the paired bipolar transistors, respectively; and a second FET having a drain, a gate being electrically connected to the drain thereof, the gate of the first FET, and a control terminal of variable resistance circuit, a source being electrically connected to a connection node between the first resistor and the second resistor, wherein the control current source adjusts the control current to allow transconductance of the second FET to be kept constant.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: January 18, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yoshiyuki Sugimoto, Keiji Tanaka
  • Patent number: 11223767
    Abstract: Various embodiments of the present technology may provide methods and apparatus for optical image stabilization. A system may include an actuator control circuit responsive to a sensor and a feedback signal from an actuator. The actuator control circuit may be configured to calibrate a gain applied to a drive signal based on a measured difference value of the feedback signal generated by the actuator control circuit and a predetermined difference value.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: January 11, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yoshihisa Tabuchi, Tomofumi Watanabe
  • Patent number: 11213855
    Abstract: An array of CMUT cells has a DC bias voltage (VB) coupled to the membrane and floor electrodes of the cells to bias the electrode to a desired collapsed or partially collapsed state. The low voltage or ground terminal of the DC bias supply is coupled to the patient-facing membrane electrodes and the high voltage is applied to the floor electrodes. An ASIC for controlling the CMUT array is located in the probe with the array. The ASIC electronics are electrically floating relative to ground potential of the ultrasound system to which the CMUT probe is connected. Control and signal lines are coupled to the CMUT probe by level shifters which translate signals to the floating potential of the ASIC and provide DC isolation between the CMUT probe and the ultrasound system.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: January 4, 2022
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventor: Bernard Joseph Savord
  • Patent number: 11190137
    Abstract: An amplifier includes an amplifying device and a bias circuit for providing a bias voltage for the amplifying device. The bias circuit is configured to provide the bias voltage in dependence of an output signal of an optical coupling arrangement which provides for electrical isolation.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: November 30, 2021
    Assignee: ADVANTEST CORPORATION
    Inventor: Anton Thoma
  • Patent number: 11183979
    Abstract: The invention relates to a gain-control stage (100) for generating gain-control signals (Vc+, Vc?) for controlling an external variable-gain amplifying unit (101). The gain-control stage comprises a first (102) and a second differential amplifier unit (112) that receive, at a respective input interface (104,114) a reference voltage signal (VRef) and a variable gain-control voltage signal (VGC). The second differential amplifier unit is configured to provide, via a second output interface (120), a control voltage signal (V1) to a controllable first current source (106) of the first differential amplifier unit (102). The first differential amplifier unit (102) is configured to provide, via a first output interface (110), the first and the second gain-control signal (VC+, VC?) in dependence on the variable gain-control voltage signal (VGC), the reference voltage signal (VRef) and a first biasing current (IB1) that depends on the control voltage signal.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: November 23, 2021
    Assignee: IHP GMBH—INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS/LEIBNIZ-INSTITUT FÜR INNOVATIVE MIKROELEKTRONIK
    Inventors: Pedro Rito, Iria Garcia Lopez, Minsu Ko, Dietmar Kissinger
  • Patent number: 11177773
    Abstract: The application describes a transimpedance amplifier circuit having a first circuit branch extending between first and second supply nodes. An input NMOS transistor is located in the first circuit branch, with its drain terminal coupled to the first supply node via a load resistor, its source terminal coupled to the second supply node and its gate terminal coupled to an input node for receiving an input signal. The circuit includes a PMOS transistor having its source terminal coupled to a third supply node, its drain terminal coupled to the first circuit branch, at a node in a part of the first circuit branch extending from the drain terminal of the input transistor to the load resistor, and its gate terminal coupled to the input node. A drain current of the PMOS transistor contributes a proportion but not all of a drain current for input NMOS transistor.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: November 16, 2021
    Assignee: SEMTECH CORPORATION
    Inventor: Jonah Edward Nuttgens
  • Patent number: 11159136
    Abstract: A variable gain amplifier (VGA) is provided. The VGA includes at least one amplifier circuit, at least one current-steering circuit and at least one bias voltage circuit. Each current-steering circuit is coupled to its corresponding amplifier circuit. Each bias voltage circuit is coupled to its corresponding current-steering circuit to provide a positive bias voltage to each current-steering circuit.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 26, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jeng-Han Tsai, Yi-Tso Cheng, Wei-Tsung Li
  • Patent number: 11152901
    Abstract: An instrumentation amplifier including a pair of input amplifiers, each including an input transistor and a feedback current amplifier configured to amplify and feedback an error current from the input transistor. The arrangement can enable a current efficient solution where the amplifier can operate with very low input signals that are close to, or potentially below ground, without requiring a negative power supply voltage.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: October 19, 2021
    Assignee: Analog Devices, Inc.
    Inventor: Michael J. Guidry
  • Patent number: 11146217
    Abstract: A signal amplifier circuit having high power supply rejection ratio includes: a pre-amplifier which generates a driving signal at a driving control node; and a driving circuit which converts an input power to an output power. The driving circuit includes: a driving transistor, having a first terminal coupled to the input power and a second terminal coupled to the output power; and a power rejection circuit which includes a noise selection circuit. When the driving transistor operates in its linear region, the power rejection circuit senses an AC component of a power noise of the input power to generate an operation noise signal. The power rejection circuit generates the power rejection signal in AC form according to the operation noise signal to reject the power noise so as to increase the power supply rejection ratio.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: October 12, 2021
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventor: Min-Hung Hu
  • Patent number: 11128267
    Abstract: A variable current trans-impedance amplifier (TIA) for an ultrasound device is described. The TIA may be coupled to an ultrasonic transducer to amplify an output signal of the ultrasonic transducer representing an ultrasound signal received by the ultrasonic transducer. During acquisition of the ultrasound signal by the ultrasonic transducer, one or more current sources in the TIA may be varied.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: September 21, 2021
    Assignee: BFLY OPERATIONS, INC.
    Inventors: Kailiang Chen, Keith G. Fife, Nevada J. Sanchez, Andrew J. Casper, Tyler S. Ralston
  • Patent number: 11092616
    Abstract: A microelectromechanical (MEMS) sensor has a capacitance that varies based on a sensed force. A charge signal representing that capacitance is provide at an input node of an amplifier of a sense circuit. The sense circuit includes a filter and analog-to-digital converter. Feedback from the filter and the analog-to-digital converter is also received at the input node of the amplifier. The sense circuit outputs a digital signal that is representative of the sensed force.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: August 17, 2021
    Assignee: INVENSENSE, INC.
    Inventors: Omid Oliaei, Peter George Hartwell
  • Patent number: 11075607
    Abstract: A differential transimpedance amplifier includes a first pair of common-gate amplifiers having a first NMOS transistor and a second NMOS transistor configured in a cross-coupling topology using a first capacitor and a second capacitor, a second pair of common-gate amplifiers comprising a first PMOS transistor and a second PMOS transistor configured in a cross-coupling topology using a third capacitor and a fourth capacitor, wherein an output of the first pair of common-gate amplifiers and an output of the second pair of common-gate amplifiers are coupled via a fifth capacitor and a sixth capacitor.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: July 27, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 11038490
    Abstract: A PoDL system uses a gyrator for DC coupling of DC power from a PSE to a wire pair, and/or decoupling DC power from a wire pair for a PD. The gyrators obviate the use of discrete inductors for DC-coupling/decoupling and can be formed as an integrated circuit. The gyrators use a small integrated capacitor and invert and multiply the capacitor effect to emulate an inductor. The gyrators present a high impedance to AC current and a low impedance to DC current. Various gyrator designs, such as positive and negative polarity gyrators, and configurations are disclosed. Gyrators are described with analog current limit and power switch control, so multiple functions are integrated on the same IC chip.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: June 15, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Andrew J. Gardner, Heath Stewart, Gitesh Bhagwat
  • Patent number: 11025231
    Abstract: In one embodiment, a tuning network includes: a controllable capacitance; a first switch coupled between the controllable capacitance and a reference voltage node; a second switch coupled between the controllable capacitance and a third switch; the third switch coupled between the second switch and a second voltage node; a fourth switch coupled between the second voltage node and a first inductor; the first inductor having a first terminal coupled to the fourth switch and a second terminal coupled to at least the second switch; and a second inductor having a first terminal coupled to the second terminal of the first inductor and a second terminal coupled to the controllable capacitance.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: June 1, 2021
    Assignee: Silicon Laboratories Inc.
    Inventors: Ruifeng Sun, Abdulkerim Coban
  • Patent number: 10992278
    Abstract: A low noise amplifier includes at least two variable gain amplifier stages, each variable gain amplifier configured to accept an input signal and to provide a load driving signal; a tunable bandpass filter connected as a load to each variable gain amplifier stage, wherein each bandpass filter includes a resonant tank, each resonant tank including an inductor, wherein each inductor of each resonant tank is oriented in orthogonal relation with respect to each respective longitudinal axis of each next inductor, the orthogonal relation of the respective longitudinal axes configured to reduce mutual coupling between the tunable bandpass filters; a cross-coupled transistor pair, and at least one cross-coupled compensation transistor pair biased in a subthreshold region configured to add a transconductance component as a function of a load driving signal; and, a controller circuit configured to tune each tunable bandpass filter.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: April 27, 2021
    Assignee: INNOPHASE INC.
    Inventors: Nicolo Testi, Yang Xu
  • Patent number: 10992277
    Abstract: Certain aspects are directed to an amplifier. The amplifier generally includes a first transistor having a gate coupled to an input node of the amplifier, a source degeneration circuit, and a second transistor coupled between the source degeneration circuit and a source of the first transistor, a gate of the second transistor being configured to receive a gain control signal from a controller.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: April 27, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Li Sun, Dong Ren, Hao Liu, Sudheer Chowdary Gali
  • Patent number: 10924075
    Abstract: Variable gain amplifiers (VGA) with output phase invariance are provided herein. In certain embodiments, a VGA is operable in a selected gain setting chosen from multiple gain settings that provide different amounts of amplification to a radio frequency (RF) input signal. The VGA includes a gain transistor that has a substantially constant bias current across the gain settings, such that the VGA's output phase, input impedance matching, and/or input return loss are substantially constant. The gain setting of the VGA is selected by controlling relative biasing of a pair of cascode transistors each connected to the gain transistor by a corresponding degeneration resistor. The degeneration resistors provide compensation that reduces or eliminates a difference in output phase of the VGA across gain settings, for instance, by introducing a zero in a transfer function of the VGA that cancels a pole arising from the cascode transistors.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: February 16, 2021
    Assignee: Analog Devices, Inc.
    Inventor: Sriram Muralidharan
  • Patent number: 10886882
    Abstract: A load circuit includes a first resistive element, a first transistor and a tristate control circuit. The first transistor has a first control terminal, a first connection terminal and a second connection terminal. The first connection terminal is coupled to to one of a first amplifier output terminal and a connection node through the first resistive element. The second connection terminal is coupled to the other of the first amplifier output terminal and the connection node. The tristate control circuit has a signal output terminal coupled to the first control terminal. When the signal output terminal is in the low impedance state, the first control terminal is arranged to receive a first control signal outputted from the signal output terminal. When the signal output terminal is in the high impedance state, the first control terminal is arranged to receive a second control signal different from the first control signal.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: January 5, 2021
    Assignee: M31 TECHNOLOGY CORPORATION
    Inventor: Ching-Hsiang Chang
  • Patent number: 10879859
    Abstract: A differential power amplifier (DPA) includes an p-side and a n-side half circuit. The p-side and n-side half circuits include an p-side and n-side base, which receive respective in-phase and out-of-phase signals of a differential signal. The DPA includes an p-side biasing circuit and a n-side biasing circuit. The p-side and n-side biasing circuit are configured to provide a controllable p-side and n-side biasing signal to the p-side and n-side base, respectively. The DPA includes a power source which provides positive DC voltage to the controller of the p-side and n-side half circuits. The DPA includes supply and grounding circuit structure which provides common mode DC paths and balances the n-side and p-side half circuits to provide a radio frequency (RF) virtual ground to an emitter of the n-side half circuit and p-side half circuit.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: December 29, 2020
    Assignee: Rockwell Collins, Inc.
    Inventor: Russell D. Wyse
  • Patent number: 10868474
    Abstract: In circuit board for a converter, including control electronics, the circuit board includes a device for current detection, the device respectively having at least two measuring amplifier circuits, only the output of one of the measuring amplifier circuits being supplied as the detected current value to the control electronics of the converter.
    Type: Grant
    Filed: March 21, 2009
    Date of Patent: December 15, 2020
    Assignee: SEW-EURODRIVE GMBH & CO. KG
    Inventors: Harald Wolf, Manuel Heil, Ralf Bennerscheidt
  • Patent number: 10840861
    Abstract: A receiver signal path includes a programmable flat gain stage configured to provide an amplified differential pair of signals based on a first frequency response having a selectable flat gain and a differential input pair of signals received on an input differential pair of nodes. The receiver signal path includes a peaking gain stage configured to generate a second amplified differential pair of signals based on the amplified differential pair of signals according to a second frequency response including a first peak gain at or near a carrier frequency in a first pass band. The first peak gain occurs just prior to a first cutoff frequency of the peaking gain stage. The programmable flat gain stage and the peaking gain stage are configured as a variable peaking gain stage. The selectable flat gain is selectively programmed based on a predetermined power consumption of a receiver path.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: November 17, 2020
    Assignee: Silicon Laboratories Inc.
    Inventor: Mohammad Al-Shyoukh
  • Patent number: 10826451
    Abstract: A combined resistance circuit 2A includes a first circuitry 20A provided between a first end 2a and a second end 2b. This first circuitry 20A includes a resistor R1 provided between a node N11 and a node N12, a resistor R2 provided between the node N12 and a node N13, a resistor R3 provided between the node N13 and a node N14, a resistor R4 provided between the node N14 and the node N11, a resistor R5 provided between the node N11 and the node N13, a switch SW0 provided in series to the resistor R4 between the node N14 and the node N11, and a switch SW1 provided in series to the resistor R2 between the node N12 and the node N13. The node N12 is connected to the first end and the node N14 is connected to the second end.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: November 3, 2020
    Assignee: THINE ELECTRONICS, INC.
    Inventor: Yuji Gendai
  • Patent number: 10812030
    Abstract: Aspects and examples described herein provide a variable gain amplifier circuit and assembly. In one example, a variable gain amplifier circuit includes a signal input, a signal output, and a variable gain amplifier including a plurality of unit cell groups coupled between the signal input and the signal output, the variable gain amplifier configured to provide an adjustable gain to a signal received at the signal input during each of a plurality of amplify modes of the variable gain amplifier, each of the plurality of amplify modes corresponding to at least one unit cell group of the plurality of unit cell groups. A bypass path including a fixed attenuator is coupled in parallel with the variable gain amplifier between the signal input and the signal output to selectively couple the signal input to the signal output through the fixed attenuator during a bypass mode.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: October 20, 2020
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Peihua Ye, Patrick Marcus Naraine, Adrian John Bergsma, Peter Harris Robert Popplewell, Thomas Obkircher
  • Patent number: 10790594
    Abstract: An apparatus includes a first circuit and a plurality of second circuits. The first circuit may be configured to generate a pair of quadrature signals from a radio-frequency signal. The second circuits may each comprise a plurality of cascode amplifiers. The cascode amplifiers may be connected in parallel. The cascode amplifiers may be configured to generate a plurality of intermediate signals by modulating the quadrature signals in response to a first control signal and a second control signal. The first control signal generally switches a contribution of the cascode amplifiers in the generation of the intermediate signal. The second control signal may adjusts a total current passing through all of the cascode amplifiers.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: September 29, 2020
    Assignee: Integrated Device Technology, Inc.
    Inventors: Tumay Kanar, Samet Zihir, Naveen Krishna Yanduru
  • Patent number: 10778478
    Abstract: A reference generator for use with serial link data communication is disclosed. Broadly speaking, a decision circuit may perform a comparison between a particular data symbol included in a serial data stream and a difference between a voltage level of a first signal and a voltage level of a second signal, and generate an output data value based on a result of the comparison. A reference generator circuit may selectively sink a first current value from either the first signal or the second signal based upon another output data value generated from another data symbol included in the serial data stream that was received prior to the particular data symbol.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: September 15, 2020
    Assignee: Oracle International Corporation
    Inventors: Rajesh Kumar, Seno Judaprawira, Dawei Huang
  • Patent number: 10778161
    Abstract: A power splitter that amplifies an input radio-frequency (RF) signal. The power splitter uses a single transistor in a common emitter stage of a cascode amplifier and two or more common base stages of the cascode amplifier to amplify and to split the input RF signal. A common base biasing signal can be used to simultaneously enable two or more of the common base stages to generate two or more amplified RF output signals.
    Type: Grant
    Filed: December 15, 2018
    Date of Patent: September 15, 2020
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Paul Raymond Andrys, David Steven Ripley
  • Patent number: 10771028
    Abstract: An apparatus comprises a plurality of selectable gain stages connected in parallel between a first bias voltage and ground, wherein each selectable gain stage comprises an amplification portion and a current steering portion, and wherein the current steering portion comprises a first selectable signal path connected between an output of the amplification portion and a signal output terminal, and a second selectable signal path connected between the output of the amplification portion and ground through a shunt device.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: September 8, 2020
    Assignee: FutureWei Technologies, Inc.
    Inventors: William Roeckner, Terrie McCain, Matthew Richard Miller, Lawrence E. Connell
  • Patent number: 10749507
    Abstract: A trimming resource includes an adjustable driver resource, a differential voltage generator, and a trim current generator. The adjustable driver resource produces an output signal. The differential voltage generator receives the output signal from the adjustable driver resource and produces a differential drive signal. The trim current generator derives a trim signal from the differential drive signal received from the differential voltage generator. According to one configuration, the trim current generator outputs the trim signal to an electronic component, correcting an operational parameter of the electronic component.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: August 18, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Adriano Sambucco, Emiliano Alejandro Puia
  • Patent number: 10742175
    Abstract: An amplifier circuit includes: an input circuit configured to receive an input signal; a load circuit provided in series with the input circuit and including a first variable resistance unit and a second variable resistance unit, a resistance value of the first variable resistance unit being controlled by a digital code, a resistance value of the second variable resistance unit being controlled by an analog control voltage; and a correction circuit including a third variable resistance unit having a circuit configuration corresponding to the first variable resistance unit and a fourth variable resistance unit having a circuit configuration corresponding to the second resistance unit, a resistance value of the third variable resistance unit being controlled by the digital code, a resistance value of the fourth variable resistance unit being controlled by the analog control voltage, the correction circuit being configured correct a resistance value of the load circuit.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: August 11, 2020
    Assignee: SOCIONEXT INC.
    Inventor: Masahiro Kudo
  • Patent number: 10727884
    Abstract: A reception circuit includes a receiver, a noise boosting circuit and a buffer. The receiver generates a positive amplification signal and a negative amplification signal by amplifying a first input signal and a second input signal. The noise boosting circuit adjusts voltage levels of the positive amplification signal and the negative amplification signal based on the first input signal and the second input signal. The buffer generates an output signal by amplifying the positive amplification signal and the negative amplification signal.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: July 28, 2020
    Assignee: SK hynix Inc.
    Inventor: Hyun Bae Lee
  • Patent number: 10658997
    Abstract: A voltage controlled amplifier with an amplitude limiting circuit, such as a clip limiter, that is separate from the signal path on which the input signal is received by a power amplifier can reduce both noise and power expenditure of the voltage controlled amplifier. The amplitude limiting circuit can include a transistor network that is controlled by a pair of utility operational amplifiers. These utility amplifiers may use less current than the audio amplifier of the voltage controlled amplifier. Further, the transistor network can be deactivated when a signal supplied to the voltage controlled amplifier is below a clipping or other voltage limiting threshold.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 19, 2020
    Assignee: RGB Systems, Inc.
    Inventor: Eric Mendenhall
  • Patent number: 10651825
    Abstract: An attenuator system comprising a variable impedance configured to provide an impedance from among a plurality of impedance states, the variable impedance comprising a first port, a second port, a first transistor comprising first and second channel terminals coupled between the first port and the second port, and a second transistor comprising first and second channel terminals coupled between the first port and the second port, and a control circuit configured to control the variable impedance to a first impedance state of the plurality of impedance states at least in part by providing a first output voltage to a control terminal of the first transistor to turn the first transistor on, wherein the first transistor is configured to operate in an under-driven mode when turned on.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: May 12, 2020
    Assignee: MEDIATEK Singapore Pte. Ltd.
    Inventors: E-Hung Chen, Tamer Mohammed Ali, Ahmed Othman Mohamed Mohamed ElShater, Mazen Soliman Shawky Soliman
  • Patent number: 10644657
    Abstract: A pre-distorter that both accurately compensates for the non-linearities of a radio frequency transmit chain, and that imposes as few computation requirements in terms of arithmetic operations, uses a diverse set of real-valued signals that are derived from separate band signals that make up the input signal. The derived real signals are passed through configurable non-linear transformations, which may be adapted during operation, and which may be efficiently implemented using lookup tables. The outputs of the non-linear transformations serve as gain terms for a set of complex signals, which are functions of the input, and which are summed to compute the pre-distorted signal. A small set of the complex signals and derived real signals may be selected for a particular system to match the classes of non-linearities exhibited by the system, thereby providing further computational savings, and reducing complexity of adapting the pre-distortion through adapting of the non-linear transformations.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: May 5, 2020
    Assignee: NanoSemi, Inc.
    Inventors: Alexandre Megretski, Kevin Chuang, Yan Li, Zohaib Mahmood, Helen H. Kim
  • Patent number: 10622959
    Abstract: A low noise amplifier includes at least two variable gain amplifier stages, each variable gain amplifier configured to accept an input signal and to provide a load driving signal; a tunable bandpass filter connected as a load to each variable gain amplifier stage, wherein each bandpass filter includes a resonant tank, each resonant tank including an inductor, wherein each inductor of each resonant tank is oriented in orthogonal relation with respect to each respective longitudinal axis of each next inductor, the orthogonal relation of the respective longitudinal axes configured to reduce mutual coupling between the tunable bandpass filters; a cross-coupled transistor pair, and at least one cross-coupled compensation transistor pair biased in a subthreshold region configured to add a transconductance component as a function of a load driving signal; and, a controller circuit configured to tune each tunable bandpass filter.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: April 14, 2020
    Assignee: Innophase Inc.
    Inventors: Nicolo Testi, Yang Xu
  • Patent number: 10615261
    Abstract: A technique relates to a semiconductor device. A bipolar transistor includes an emitter layer and a base layer, where the emitter layer and the base layer are doped with an impurity, the impurity being a same for the emitter and base layers. The bipolar transistor includes a collector layer.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guy M. Cohen, Paul M. Solomon, Christian Lavoie
  • Patent number: 10587296
    Abstract: The disclosure relates to technology for an adjustable gain device that includes differential input terminals, differential output terminals, signal processing circuitry, and first and second cross-coupled segments. The first cross-coupled segment is coupled between differential input terminals of the adjustable gain device and a negative input of the signal processing circuitry. The second cross-coupled segment is coupled between differential input terminals of the adjustable gain device and a positive input of the signal processing circuitry. The adjustable gain device has a gain that is adjustable by adjusting values of the first and second cross-coupled segments, while maintaining a substantially consistent frequency response and a substantially consistent input impedance of the adjustable gain device, so long as a specified relationship between values of the first and second cross-coupled segments is kept substantially constant.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: March 10, 2020
    Assignee: Futurewei Technologies, Inc.
    Inventors: Matthew R. Miller, Paul R. Ganci
  • Patent number: 10581395
    Abstract: A variable gain amplifier (1) includes: a signal transmission circuit (10, 20) including amplifying transistor units (111 to 11N, and 211 to 21N) connected in parallel between a signal input port (2P, 2N) and a signal output port (3P, 3N); a load circuit (40) connected between a supply line of power supply voltage (VDD) and an output end of the signal transmission circuit (10, 20); a signal short circuit (30) including a short-circuit transistor unit (31) connected between the supply line of the power supply voltage (VDD) and an input end of the signal transmission circuit (10, 20), a constant-current source circuit (42), and a transistor control circuit (46). The transistor control circuit (46) selects transistor units to be turned on, from among the amplifying transistor units (111 to 11N, and 211 to 21N) and the short-circuit transistor unit (31), and supplies control voltages for turning on the selected transistor units.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: March 3, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Koji Tsutsumi, Takanobu Fujiwara, Atsushi Kato, Shinichi Inabe
  • Patent number: 10581478
    Abstract: Radio-frequency front-end circuitry includes an output terminal, a receive amplifier controllably coupled to the output terminal, at least one transmit amplifier controllably inductively coupled to the output terminal, and at least one impedance element controllably coupled between ground and one of the at least one transmit amplifier to reduce degradation of output of the radio-frequency front-end circuitry when the at least one transmit amplifier is not in use. In differential signaling, there is an impedance element between ground and each pole of the differential signal. A second transmit amplifier may generate second transmit signals and harmonics of the second transmit signals, and the second transmit amplifier may be switchably connected to the output of a first transmit amplifier so that output of the second transmit amplifier is filtered by the one of the first transmit amplifier. The transmit amplifiers may include a WiFi power amplifier and a BLUETOOTH® power amplifier.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: March 3, 2020
    Assignee: Marvell International Ltd.
    Inventors: Sai-Wang Tam, Randy Tsang, Ovidiu Carnu, Donghong Cui, Amir Ghaffari, Wai Lau, Timothy Loo, Alden C. Wong
  • Patent number: 10566941
    Abstract: An integrated circuit having a plurality of miniaturized transistors, wherein the plurality of transistors include: high concentration transistors which include channel regions having impurity concentrations of a first concentration; and low concentration transistors which include channel regions having impurity concentrations of a second concentration lower than the first concentration.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: February 18, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Naohiro Nomura, Sachito Horiuchi, Kunihiko Iwamoto
  • Patent number: 10566954
    Abstract: A capacitor bank has a capacitance value that is discontinuous and has an extremely narrow variable range. Thus, in a case of obtaining a wide variable range of the capacitance value, a large number of capacitors are connected in parallel and used while being switched by switches. The present technology achieves at least one of: allowing the capacitance value of a variable capacitance circuit to be varied continuously by electrical control without increasing the parasitic capacitance; and decreasing the current consumption of an oscillator circuit using the variable capacitance circuit as compared to a conventional case. The variable capacitance circuit includes: a transconductance circuit that includes a MOS transistor; an inductor that is connected in parallel to the transconductance circuit; and a Gm control circuit that varies a transconductance of the MOS transistor.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: February 18, 2020
    Assignee: SONY CORPORATION
    Inventor: Masahiro Ichihashi