Abstract: An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and selectively coupling at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles.

Abstract: A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.

Abstract: A tunable inductor arrangeable on a chip or substrate comprises a first winding part connected at one end to a first input of the tunable inductor arrangement, a second winding part connected at one end to the other end of the first winding part, a third winding part connected at one end to a second input of the tunable inductor arrangement, a fourth winding part connected at one end to the other end of the third winding part, and a switch arrangement arranged. The switch arrangement tunes the tunable inductor by selectively connecting the first and fourth winding parts in parallel and the second and third winding parts in parallel, with the parallel couplings in series between the first and second inputs, or connecting the first, second, fourth and third winding parts in series between the first and second inputs. Corresponding transceivers, communication devices, methods and computer programs are disclosed.

Abstract: A blocking signal cancellation low noise amplifier system includes a first low noise amplifier, a second low noise amplifier, a blocking signal extraction and bias generation circuit, a bias switching circuit, and a bias switching signal generating circuit. The first low noise amplifier is used for dynamic input matching, and the first low noise amplifier receives an input signal and outputs it after amplifying. The blocking signal extraction and bias generation circuit is used to extract a blocking signal from the output signal of the first low noise amplifier, and output a DC voltage signal. The bias switching circuit is used to switch the first low noise amplifier between a blocking mode and a small signal mode. The bias switching signal generating circuit is used to compare the DC bias voltage signal VB2 with a preset reference voltage signal Vref.

Abstract: An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain-stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.

Abstract: A variable gain amplifier includes input terminals configured to receive a differential input of the variable gain amplifier, output terminals configured to generate a differential output of the variable gain amplifier, the differential output having a gain applied by the variable gain amplifier to the differential input, and an impedance ladder circuit coupled to the input terminals, the impedance ladder circuit comprising a plurality of semiconductor switches configured to receive respective control signals based on a control voltage. The plurality of semiconductors switches are responsive to the respective control signals to adjust the gain of the variable gain amplifier and configured with a predetermined exponential scale such that the impedance ladder circuit causes a slope of the gain of the variable gain amplifier relative to the control voltage to be generally linear.

Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration.

Abstract: The present application relates to current sensing circuitry (100) that comprises a differential amplifier (110) comprising first and second inputs configured to sense a current across a sense resistance, and an output configured to output a current sense signal. The circuitry (100) further comprises a first current source, a second current source and a switch network operable in: a first phase in which the first current source is connected to the first input and disconnected from the output, and the second current source is connected to the output and disconnected from the first input; and a second phase in which the first current source is connected to the output and disconnected from the first input, and the second current source is connected to the first input and disconnected from the output.

Abstract: Apparatus and methods for biasing power amplifiers are provided herein. In certain embodiments, a power amplifier includes a bipolar transistor having a base biased by a bias network having a reactance that controls an impedance at the transistor base to achieve substantially flat phase response over large dynamic power levels. For example, the bias network can have a frequency response, such as a high-pass or band-pass response, that reduces the impact of power level on phase distortion (AM/PM).

Abstract: A piecewise linear gain amplifier circuit includes a differential preamplifier and a plurality of transconductors. The differential preamplifier is electrically coupled to a differential input having an input voltage. The transconductors are electrically coupled in parallel with each other. Each transconductor includes a respective differential input that is electrically coupled to a differential output of the differential preamplifier. In addition, each transconductor includes a respective differential output that is electrically coupled to a common differential PWL output. Each transconductor has a different linear input range. An optional attenuation circuit can be electrically coupled in parallel to the differential preamplifier. The differential output of the attenuation circuit can be electrically coupled to a differential input of another transconductor, and that transconductor can have a differential output that is electrically coupled to the common differential PWL output.

Abstract: A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.

Abstract: A variable gain amplifier includes a first transistor group which is connected to an input terminal and an output terminal, and which amplifies a signal from the input terminal to output the amplified signal to the output terminal; a second transistor group connected to the input terminal; a third transistor group connected to the output terminal; and a controller configured to control the first transistor group, the second transistor group, and the third transistor group so that a total number of the number of transistors to be turned on in the first transistor group and the second transistor group is kept at a constant value, and total numbers of transistors to be turned on in the first transistor group and in the third transistor group are the same.

Abstract: A split-steer amplifier with an invertible phase output, includes a first transistor having its base coupled to a positive node of an input port, its emitter coupled to ground, and collector connected to a positive intermediate node; a second transistor having its base coupled to a negative node of the input port, its emitter coupled to ground, and collector connected to a negative intermediate node; and multiple output ports each having a transistor arrangement operable to couple a positive node of that output port to the positive intermediate node and a negative node of that output port to the negative intermediate node, operable to couple the positive node of that output port to the negative intermediate node and the negative node of that output port to the positive intermediate node, and operable to decouple the positive node and the negative node of that output port from the intermediate nodes.

Abstract: The present invention is directed to electrical circuits. In a specific embodiment, the present invention provides variable gain amplifier that includes an impedance ladder and a control circuit. The impedance ladder includes n switches configured in parallel. The control circuit includes a digital-to-analog converter and an amplifier. The control circuit generates n control signals for the n switches. There are other embodiments as well.

Abstract: Equalizing an input signal according to a receiver equalizer peaking circuit having a capacitor FET (CFET) providing a capacitive value and a resistor FET (RFET) providing a resistive value, generating a capacitor control voltage at a gate of the CFET using a capacitor controller DAC based on a first reference voltage, and a RFET control voltage at a gate of the RFET using a resistor controller DAC based on a second reference voltage, generating the first reference voltage using a replica input FET, the first reference voltage varying according to a threshold voltage (Vt) of an input FET, providing the first reference voltage to the capacitor controller DAC, generating the second reference voltage using a replica RFET, the second reference voltage varying with respect to the first reference voltage and a Vt of the replica of the RFET, and providing the second reference voltage to the resistor controller DAC.

Abstract: The present invention is directed electrical circuits. According to a specific embodiment, the present invention provides a variable gain amplifier that includes a first switch, which includes drain terminal coupled to an inductor. A second switch is configured in parallel to the inductor, and the resistance value of the second switch is adjustable in response to a control signal. There are other embodiments as well.

Abstract: A wideband buffer circuit and a wideband communication circuit that uses the wideband buffer circuit. The wideband buffer circuit includes first and second transistors deployed as a voltage buffer and connected to first and second input terminals, first and second parallel resistor-capacitor pairs connected to the first and second transistors, first and second cross-coupled transistors connected to the first and second parallel resistor-capacitor pairs and connected to first and second output terminals, and first and second current sources connected to the first and second cross-coupled transistors and a fixed voltage. The first transistor, the first parallel resistor-capacitor pair, the first cross-coupled transistor and the first current source are connected in series. The second transistor, the second parallel resistor-capacitor pair, the second cross-coupled transistor and the second current source are connected in series.

Abstract: An apparatus for transmitting broadcasting signal using transmitter identification scaled by 4-bit injection level code and method using the same are disclosed. An apparatus for transmitting broadcasting signal according to an embodiment of the present invention includes a waveform generator configured to generate a host broadcasting signal; a transmitter identification signal generator configured to generate a transmitter identification signal for identifying a transmitter, the transmitter identification signal scaled by an injection level code; and a combiner configured to inject the transmitter identification signal into the host broadcasting signal in a time domain so that the transmitter identification signal is transmitted synchronously with the host broadcasting signal.

Abstract: In optical receivers, extending the transimpedance amplifier's (TIA) dynamic range is a key to increasing the receiver's dynamic range, and therefore increase the channel capacity. Ideally, the TIA requires controllable gain, whereby the receiver can modify the characteristics of the TIA and/or the VGA to process high power incoming signals with a defined maximum distortion, and low power incoming signals with a defined maximum noise. A solution to the problem is to provide TIA's with reconfigurable feedback resistors, which are adjustable based on the level of power, e.g. current, generated by the photodetector, and variable load resistors, which are adjustable based on the change in impedance caused by the change in the feedback resistor.

Abstract: Embodiments of a linear equalizer are disclosed. In an embodiment, a linear equalizer includes a plurality of input transistors, a plurality of gain control transistors and first and second impedance elements. The plurality of input transistors is connected to input terminals of the linear equalizer to receive input signals. The plurality of gain control transistors is connected between a supply voltage and the plurality of input transistors. The plurality of gain control transistors is also connected to gain control terminals to receive gain control signals. At least some of the gain control transistors are connected to output terminals of the linear equalizer to transmit output signals. The first and second impedance elements are connected between at least some of the input transistors and at least one fixed voltage. A peaking gain of the linear equalizer is defined by gain control signals applied to the gain control terminals.

Abstract: The present application provides a capacitance detection circuit, which could reduce the influence of screen noise on capacitance detection. The capacitance detection circuit includes: an amplification circuit connected to the capacitor to be detected, and configured to convert a capacitance signal of the capacitor to be detected into a voltage signal, the voltage signal being associated with the capacitance of the capacitor to be detected; and a control circuit connected to the amplification circuit, and configured to control an amplification factor of the amplification circuit to be a first amplification factor in a first period, and to control the amplification factor of the amplification circuit to be a second amplification factor in a second period, where noise generated by the screen in the first period is less than noise generated by the screen in the second period, and the first amplification factor is greater than the second amplification factor.

Abstract: An example VGA includes a transistor arrangement having a plurality of transistors configured to realize one or more gain step circuits of the VGA, and a cross-couple switching arrangement having a plurality of switches configured to selectively change the coupling of the terminals of at least some of the transistors depending on whether a given gain step circuit is supposed to be in an ON state or in an OFF state. Using the cross-couple switching arrangement advantageously allows keeping all of the transistors ON at all times during operation and changing the coupling of some transistor terminals to either realize an in-phase addition of currents flowing through various transistors to apply the maximum gain or realize a subtraction of currents to apply the minimum gain. Such a VGA may be inherently wideband, enabling a highly linear, wideband operation without having to resort to significant trade-offs with other performance parameters.

Abstract: A multi-stage transimpedance amplifier (TIA) with an adjustable input linear range is disclosed. The TIA includes a first stage, configured to convert a single-ended current signal from an optical sensor of a receiver signal chain to a single-ended voltage signal, and a second stage, configured to convert the single-ended voltage signal provided by the first stage to a differential signal. In such a TIA, the input linear range may be adjusted using a clamp that is programmable with an output offset current to keep the second stage of the TIA from overloading and to maintain a linear transfer function without compression.

Abstract: A device configured for wireless power transfer includes a digital controller configured to generate a plurality of switch control signals, and a transceiver configured to generate a wireless signal for the wireless power transfer. The transceiver includes a plurality of switches, each switch of the plurality of switches being responsive to a respective switch control signal of the plurality of switch control signals such that the wireless signal has a waveform shaped in accordance with a code sequence for the wireless power transfer. The code sequence is one of a set of predetermined code sequences, each predetermined code sequence being orthogonal to each other predetermined code sequence of the set of predetermined code sequences.

Abstract: Distributed amplifiers with controllable linearization are provided herein. In certain embodiments, a distributed amplifier includes a differential input transmission line, a differential output transmission line, and a plurality of differential distributed amplifier stages connected between the differential input transmission line and the differential output transmission line at different points or nodes. The distributed amplifier further includes a differential non-linearity cancellation stage connected between the differential input transmission line and the differential output transmission line and providing signal inversion relative to the differential distributed amplifier stages. The differential non-linearity cancellation stage operates with a separately controllable bias from the differential distributed amplifier stages, thereby providing a mechanism to control the linearity of the distributed amplifier.

Abstract: A receiver front-end includes a first peaking gain stage configured to amplify a received differential pair of signals received on an input differential pair of nodes. The first peaking gain stage has a first frequency response including a first peak gain at or near a carrier frequency in a first pass band. The first peak gain occurs just prior to a first cutoff frequency. A second peaking gain stage is configured to amplify a differential pair of signals generated by the first peaking gain stage. The second peaking gain stage has a high input impedance and a second frequency response including a second peak gain at or near the carrier frequency in a second pass band. The second peak gain occurs just prior to a second cutoff frequency. The first peaking gain stage and the second peaking gain stage have a cascaded peak gain at or near the carrier frequency.

Abstract: A differential amplifier circuit includes: a control current source supplying a control current; paired bipolar transistors; an a variable resistance circuit including: a series circuit of a first resistor and a second resistor having an identical resistance, the series circuit electrically connected between a first terminal and a second terminal of the variable resistance circuit; a first field effect transistor (FET) having a source and a drain being electrically connected to emitters of the paired bipolar transistors, respectively; and a second FET having a drain, a gate being electrically connected to the drain thereof, the gate of the first FET, and a control terminal of variable resistance circuit, a source being electrically connected to a connection node between the first resistor and the second resistor, wherein the control current source adjusts the control current to allow transconductance of the second FET to be kept constant.

Abstract: Various embodiments of the present technology may provide methods and apparatus for optical image stabilization. A system may include an actuator control circuit responsive to a sensor and a feedback signal from an actuator. The actuator control circuit may be configured to calibrate a gain applied to a drive signal based on a measured difference value of the feedback signal generated by the actuator control circuit and a predetermined difference value.

Abstract: An array of CMUT cells has a DC bias voltage (VB) coupled to the membrane and floor electrodes of the cells to bias the electrode to a desired collapsed or partially collapsed state. The low voltage or ground terminal of the DC bias supply is coupled to the patient-facing membrane electrodes and the high voltage is applied to the floor electrodes. An ASIC for controlling the CMUT array is located in the probe with the array. The ASIC electronics are electrically floating relative to ground potential of the ultrasound system to which the CMUT probe is connected. Control and signal lines are coupled to the CMUT probe by level shifters which translate signals to the floating potential of the ASIC and provide DC isolation between the CMUT probe and the ultrasound system.

Abstract: An amplifier includes an amplifying device and a bias circuit for providing a bias voltage for the amplifying device. The bias circuit is configured to provide the bias voltage in dependence of an output signal of an optical coupling arrangement which provides for electrical isolation.

Abstract: The invention relates to a gain-control stage (100) for generating gain-control signals (Vc+, Vc?) for controlling an external variable-gain amplifying unit (101). The gain-control stage comprises a first (102) and a second differential amplifier unit (112) that receive, at a respective input interface (104,114) a reference voltage signal (VRef) and a variable gain-control voltage signal (VGC). The second differential amplifier unit is configured to provide, via a second output interface (120), a control voltage signal (V1) to a controllable first current source (106) of the first differential amplifier unit (102). The first differential amplifier unit (102) is configured to provide, via a first output interface (110), the first and the second gain-control signal (VC+, VC?) in dependence on the variable gain-control voltage signal (VGC), the reference voltage signal (VRef) and a first biasing current (IB1) that depends on the control voltage signal.

Abstract: The application describes a transimpedance amplifier circuit having a first circuit branch extending between first and second supply nodes. An input NMOS transistor is located in the first circuit branch, with its drain terminal coupled to the first supply node via a load resistor, its source terminal coupled to the second supply node and its gate terminal coupled to an input node for receiving an input signal. The circuit includes a PMOS transistor having its source terminal coupled to a third supply node, its drain terminal coupled to the first circuit branch, at a node in a part of the first circuit branch extending from the drain terminal of the input transistor to the load resistor, and its gate terminal coupled to the input node. A drain current of the PMOS transistor contributes a proportion but not all of a drain current for input NMOS transistor.

Abstract: A variable gain amplifier (VGA) is provided. The VGA includes at least one amplifier circuit, at least one current-steering circuit and at least one bias voltage circuit. Each current-steering circuit is coupled to its corresponding amplifier circuit. Each bias voltage circuit is coupled to its corresponding current-steering circuit to provide a positive bias voltage to each current-steering circuit.

Abstract: An instrumentation amplifier including a pair of input amplifiers, each including an input transistor and a feedback current amplifier configured to amplify and feedback an error current from the input transistor. The arrangement can enable a current efficient solution where the amplifier can operate with very low input signals that are close to, or potentially below ground, without requiring a negative power supply voltage.

Abstract: A signal amplifier circuit having high power supply rejection ratio includes: a pre-amplifier which generates a driving signal at a driving control node; and a driving circuit which converts an input power to an output power. The driving circuit includes: a driving transistor, having a first terminal coupled to the input power and a second terminal coupled to the output power; and a power rejection circuit which includes a noise selection circuit. When the driving transistor operates in its linear region, the power rejection circuit senses an AC component of a power noise of the input power to generate an operation noise signal. The power rejection circuit generates the power rejection signal in AC form according to the operation noise signal to reject the power noise so as to increase the power supply rejection ratio.

Abstract: A variable current trans-impedance amplifier (TIA) for an ultrasound device is described. The TIA may be coupled to an ultrasonic transducer to amplify an output signal of the ultrasonic transducer representing an ultrasound signal received by the ultrasonic transducer. During acquisition of the ultrasound signal by the ultrasonic transducer, one or more current sources in the TIA may be varied.

Abstract: A microelectromechanical (MEMS) sensor has a capacitance that varies based on a sensed force. A charge signal representing that capacitance is provide at an input node of an amplifier of a sense circuit. The sense circuit includes a filter and analog-to-digital converter. Feedback from the filter and the analog-to-digital converter is also received at the input node of the amplifier. The sense circuit outputs a digital signal that is representative of the sensed force.

Abstract: A differential transimpedance amplifier includes a first pair of common-gate amplifiers having a first NMOS transistor and a second NMOS transistor configured in a cross-coupling topology using a first capacitor and a second capacitor, a second pair of common-gate amplifiers comprising a first PMOS transistor and a second PMOS transistor configured in a cross-coupling topology using a third capacitor and a fourth capacitor, wherein an output of the first pair of common-gate amplifiers and an output of the second pair of common-gate amplifiers are coupled via a fifth capacitor and a sixth capacitor.

Abstract: A PoDL system uses a gyrator for DC coupling of DC power from a PSE to a wire pair, and/or decoupling DC power from a wire pair for a PD. The gyrators obviate the use of discrete inductors for DC-coupling/decoupling and can be formed as an integrated circuit. The gyrators use a small integrated capacitor and invert and multiply the capacitor effect to emulate an inductor. The gyrators present a high impedance to AC current and a low impedance to DC current. Various gyrator designs, such as positive and negative polarity gyrators, and configurations are disclosed. Gyrators are described with analog current limit and power switch control, so multiple functions are integrated on the same IC chip.

Abstract: In one embodiment, a tuning network includes: a controllable capacitance; a first switch coupled between the controllable capacitance and a reference voltage node; a second switch coupled between the controllable capacitance and a third switch; the third switch coupled between the second switch and a second voltage node; a fourth switch coupled between the second voltage node and a first inductor; the first inductor having a first terminal coupled to the fourth switch and a second terminal coupled to at least the second switch; and a second inductor having a first terminal coupled to the second terminal of the first inductor and a second terminal coupled to the controllable capacitance.

Abstract: A low noise amplifier includes at least two variable gain amplifier stages, each variable gain amplifier configured to accept an input signal and to provide a load driving signal; a tunable bandpass filter connected as a load to each variable gain amplifier stage, wherein each bandpass filter includes a resonant tank, each resonant tank including an inductor, wherein each inductor of each resonant tank is oriented in orthogonal relation with respect to each respective longitudinal axis of each next inductor, the orthogonal relation of the respective longitudinal axes configured to reduce mutual coupling between the tunable bandpass filters; a cross-coupled transistor pair, and at least one cross-coupled compensation transistor pair biased in a subthreshold region configured to add a transconductance component as a function of a load driving signal; and, a controller circuit configured to tune each tunable bandpass filter.

Abstract: Certain aspects are directed to an amplifier. The amplifier generally includes a first transistor having a gate coupled to an input node of the amplifier, a source degeneration circuit, and a second transistor coupled between the source degeneration circuit and a source of the first transistor, a gate of the second transistor being configured to receive a gain control signal from a controller.

Abstract: Variable gain amplifiers (VGA) with output phase invariance are provided herein. In certain embodiments, a VGA is operable in a selected gain setting chosen from multiple gain settings that provide different amounts of amplification to a radio frequency (RF) input signal. The VGA includes a gain transistor that has a substantially constant bias current across the gain settings, such that the VGA's output phase, input impedance matching, and/or input return loss are substantially constant. The gain setting of the VGA is selected by controlling relative biasing of a pair of cascode transistors each connected to the gain transistor by a corresponding degeneration resistor. The degeneration resistors provide compensation that reduces or eliminates a difference in output phase of the VGA across gain settings, for instance, by introducing a zero in a transfer function of the VGA that cancels a pole arising from the cascode transistors.

Abstract: A load circuit includes a first resistive element, a first transistor and a tristate control circuit. The first transistor has a first control terminal, a first connection terminal and a second connection terminal. The first connection terminal is coupled to to one of a first amplifier output terminal and a connection node through the first resistive element. The second connection terminal is coupled to the other of the first amplifier output terminal and the connection node. The tristate control circuit has a signal output terminal coupled to the first control terminal. When the signal output terminal is in the low impedance state, the first control terminal is arranged to receive a first control signal outputted from the signal output terminal. When the signal output terminal is in the high impedance state, the first control terminal is arranged to receive a second control signal different from the first control signal.

Abstract: A differential power amplifier (DPA) includes an p-side and a n-side half circuit. The p-side and n-side half circuits include an p-side and n-side base, which receive respective in-phase and out-of-phase signals of a differential signal. The DPA includes an p-side biasing circuit and a n-side biasing circuit. The p-side and n-side biasing circuit are configured to provide a controllable p-side and n-side biasing signal to the p-side and n-side base, respectively. The DPA includes a power source which provides positive DC voltage to the controller of the p-side and n-side half circuits. The DPA includes supply and grounding circuit structure which provides common mode DC paths and balances the n-side and p-side half circuits to provide a radio frequency (RF) virtual ground to an emitter of the n-side half circuit and p-side half circuit.

Abstract: In circuit board for a converter, including control electronics, the circuit board includes a device for current detection, the device respectively having at least two measuring amplifier circuits, only the output of one of the measuring amplifier circuits being supplied as the detected current value to the control electronics of the converter.

Abstract: A receiver signal path includes a programmable flat gain stage configured to provide an amplified differential pair of signals based on a first frequency response having a selectable flat gain and a differential input pair of signals received on an input differential pair of nodes. The receiver signal path includes a peaking gain stage configured to generate a second amplified differential pair of signals based on the amplified differential pair of signals according to a second frequency response including a first peak gain at or near a carrier frequency in a first pass band. The first peak gain occurs just prior to a first cutoff frequency of the peaking gain stage. The programmable flat gain stage and the peaking gain stage are configured as a variable peaking gain stage. The selectable flat gain is selectively programmed based on a predetermined power consumption of a receiver path.

Abstract: A combined resistance circuit 2A includes a first circuitry 20A provided between a first end 2a and a second end 2b. This first circuitry 20A includes a resistor R1 provided between a node N11 and a node N12, a resistor R2 provided between the node N12 and a node N13, a resistor R3 provided between the node N13 and a node N14, a resistor R4 provided between the node N14 and the node N11, a resistor R5 provided between the node N11 and the node N13, a switch SW0 provided in series to the resistor R4 between the node N14 and the node N11, and a switch SW1 provided in series to the resistor R2 between the node N12 and the node N13. The node N12 is connected to the first end and the node N14 is connected to the second end.

Abstract: Aspects and examples described herein provide a variable gain amplifier circuit and assembly. In one example, a variable gain amplifier circuit includes a signal input, a signal output, and a variable gain amplifier including a plurality of unit cell groups coupled between the signal input and the signal output, the variable gain amplifier configured to provide an adjustable gain to a signal received at the signal input during each of a plurality of amplify modes of the variable gain amplifier, each of the plurality of amplify modes corresponding to at least one unit cell group of the plurality of unit cell groups. A bypass path including a fixed attenuator is coupled in parallel with the variable gain amplifier between the signal input and the signal output to selectively couple the signal input to the signal output through the fixed attenuator during a bypass mode.

Abstract: An apparatus includes a first circuit and a plurality of second circuits. The first circuit may be configured to generate a pair of quadrature signals from a radio-frequency signal. The second circuits may each comprise a plurality of cascode amplifiers. The cascode amplifiers may be connected in parallel. The cascode amplifiers may be configured to generate a plurality of intermediate signals by modulating the quadrature signals in response to a first control signal and a second control signal. The first control signal generally switches a contribution of the cascode amplifiers in the generation of the intermediate signal. The second control signal may adjusts a total current passing through all of the cascode amplifiers.