Abstract: A method, computer program, device and system are provided for determining channel state information for use in a wireless communications network. The channel state information includes a rank indicator (RI), precoding matrix index (PMI) and channel quality indicator (CQI). The RI, PMI or CQI can be determined based on channel covariance estimation and the Taylor series approximation of its inverse. Further, the RI and PMI can be determined separately.

Abstract: A device comprising a clock circuit, a control circuit, and a current mode logic (CML) circuit is disclosed. The clock circuit provides a first differential clock signal and the control circuit generates a control signal based at least in part on the frequency of the first differential clock signal. The CML circuit generates a second differential clock signal based at least in part on the first differential clock signal. The CML circuit operates in one of a plurality of different frequency modes based at least in part on the control signal and includes a number of variable resistors that are responsive to the control signal.

Abstract: A protection circuit includes a transformer (11), wherein a terminal (11a) of the transformer (11) is connected to a terminal part (1) of a radio IC, a terminal (11b) thereof is connected to a grounding point, a terminal (11c) thereof is connected to an input or output of an on-chip circuit (7), and a terminal (11d) thereof is connected to a bias power supply circuit (18). A signal is transmitted between a terminal-side inductor (11f) and a circuit-side inductor (11g) due to magnetic coupling therebetween. The terminal-side inductor and the circuit-side inductor are insulated to each other from a standpoint of DC and hence isolated completely to each other. Thus, different voltages can be applied to the terminal part (1) and the input or output of the on-chip circuit (7), respectively.

Abstract: A multi-mode OPAMP-based circuit is provided. An input amplifying stage amplifies a pair of input differential signals to provide a pair of intermediate differential signals. An output amplifying stage amplifies the pair of intermediate differential signals to provide a pair of output differential signals. A first capacitor is disposed in a first negative feedback loop of the output amplifying stage. A second capacitor is disposed in a second negative feedback loop of the output amplifying stage. A third capacitor is selectively disposed in a first positive feedback loop of the output amplifying stage or coupled to the first capacitor in parallel according to a control signal. A fourth capacitor is selectively disposed in a second positive feedback loop of the output amplifying stage or coupled to the second capacitor in parallel according to the control signal.

Abstract: A method may include applying an input differential voltage to input terminals of an amplifier, a first input terminal coupled to a gate of a first transistor and a second input terminal coupled to a gate of a second transistor. The method may also include varying a gain of the amplifier by varying at least one of: a resistance of a first resistor, the first resistor coupled between a source of the first transistor and a source of the second transistor; and a resistance of a second resistor, the second resistor coupled between a source of a third transistor and a source of a fourth transistor; wherein: the third transistor is coupled at its drain to the drain of the first transistor; and the fourth transistor is coupled at its drain to the drain of the second transistor and a gate of the third transistor and coupled at its gate to the drain of the third transistor.

Abstract: An instrumentation amplifier includes first and second resistors for gain setting. The operational amplifiers within the instrumentation amplifier include selectively enabled current drive sources coupled to the amplifier output. The first and second resistors have variable resistances. A control circuit is configured to select the variable resistances of the first and second resistors to implement a fixed gain for the instrumentation amplifier and further selectively enable the current drive sources. The control circuit receives an indication of a downstream programmable gain (for example, from a downstream programmable gain amplifier). The variable resistances of the first and second resistors are selected to be scaled inversely with respect to the downstream programmable gain and the current drive sources are enabled proportionately with respect to the downstream programmable gain.

Abstract: An integrated circuit having transceiver circuitry is provided. The transceiver circuitry may include an equalization circuit such as a decision feedback equalizer (DFE). The DFE may include a variable gain amplifier (VGA) that is coupled to a summation node circuit and a digital sampler. The DFE may also include an operational amplifier that is coupled in a negative feedback loop and that provides a controlled power supply voltage to the VGA so that the VGA is able to provide a stable common mode output voltage to the digital sampler. The operational amplifier may be a self-biased operational amplifier with an output stage that includes miller compensation circuitry for enhanced stability.

Abstract: First and second transconductance amplifier input stages having first and second gain characteristics, respectively, are combined. The resulting combined input stage has a third gain characteristic with a linear range that is larger than a linear range of either of the first and second gain characteristics.

Abstract: Disclosed herein is a signal processor including: a plurality of parallel-connected variable gain amplification sections with variable gains; and a control section adapted to control the potentials of control terminals of each of the variable gain amplification sections and make transitions in the control terminal potentials according to different input signal levels.

Abstract: Receiver circuits that can be reconfigured to generate test signals in a wireless device are disclosed. In an exemplary design, an apparatus includes a mixer and an amplifier. The mixer downconverts an input radio frequency (RF) signal based on a local oscillator (LO) signal in a first mode. The amplifier, which is formed by at least a portion of the mixer, amplifies the LO signal and provides an amplified LO signal in a second mode. In another exemplary design, an apparatus includes an amplifier and an attenuator. The amplifier receives and amplifies an input RF signal in a first mode. The attenuator, which is formed by at least a portion of the amplifier, receives and passes an LO signal in a second mode.

Abstract: An amplifier, including a voltage-to-current converter (V2I) to control an output current based on an input voltage, resistive degeneration circuitry to reduce baseband gain of the voltage-to-current converter, capacitive degeneration circuitry to increase passband gain of the voltage-to-current converter, and impedance control circuitry to compensate for negative input impedance of the capacitive degeneration circuitry. The V2I may include series-connected complimentary V2Is. The impedance control circuitry may include resistive negative feedback to provide a real part of input impedance, which may increase a frequency range for which the amplifier is linear. Capacitive degeneration and associated phase compensation may increase a frequency range for which the resistive feedback is negative. The amplifier may be configured as a single-input/single-output system and/or as a differential system.

Abstract: According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TIA) implemented using a current mode buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced.

Abstract: An amplifier biasing circuit that reduces gain variation in short channel amplifiers, an amplifier biasing circuit that produces a constant Gm biasing signal for short channel amplifiers, and a multistage amplifier that advantageously incorporates embodiment of both types of amplifier biasing circuits are described. Both amplifier biasing circuit approaches use an operational amplifier to equalize internal bias circuit voltages. The constant Gm biasing circuit produces a Gm of 1/R, where R is the value of a trim variable resistor value. The biasing circuit that reduces gain variation produces a Gm of approximately 1/R, where R is the value of a trim variable resistor value, however, the biasing circuit is configurable to adjust the bias circuit Gm to mitigate the impact of a wide range of circuit specific characteristics and a wide range of changes in the operational environment in which the circuit can be used, such as changes in temperature.

Abstract: A receiver circuit includes a first differential amplification unit including a variable load section, and configured to receive first and second input signals, and to generate first and second output signals, which are amplified based on an impedance value of the variable load section and a voltage difference between the first and second input signals, a second differential amplification unit configured to receive the first and second output signals and to generate a third output signal based on a voltage difference between the first and second output signals, and a signal generating unit configured to generate an equalization signal for controlling the variable load section based on the third output signal.

Abstract: A circuit is provided for both boosting output current and providing short circuit protection in an integrated circuit such as an operational amplifier. In an embodiment, a current-boosting output stage with short-circuit protection includes six current sources and six transistors, where the the boosting of output current is achieved using positive feedback and the short circuit protection is achieved using negative feedback.

Abstract: A Radio Frequency (RF) amplifier in a communication system and a method for controlling the RF amplifier are provided. The RF amplifier includes an input unit for receiving an RF signal, a cascode unit for amplifying the RF signal according to a gain of the RF amplifier and for outputting the amplified RF signal, a load unit connected to the cascode unit, and a gain controller for controlling the gain by converting an impedance in a baseband to an impedance viewed from an RF band, the gain controller being connected in parallel to the load unit.

Abstract: Embodiments include systems and methods for accurately controlling gain of a high-speed variable-gain amplifier (VGA) without adversely impacting bandwidth performance. Embodiments include a VGA with a variable resistor, for which resistance is a function of a control level. A gain calibration system controls the control level by using a gain control feedback subsystem to sample outputs of a duplicate VGA, which includes a duplicate variable resistor. The sampled duplicate outputs are compared to a target gain generated by a reference generator. The control level can be fed back to control the gain of the duplicate VGA until the target gain is reached. The control level can also be fed to the actual VGA to control its gain. By performing gain control on the duplicate VGA without interfering with the output signal path of the actual VGA, the actual VGA's gain can be accurately controlled without impacting its bandwidth.

Abstract: An amplifying circuit comprises a differential input stage having a first input terminal, a second input terminal, and an intermediate node, wherein the differential input stage is configured to generate a differential current flowing through the intermediate node in response to an input voltage difference between the first and second input terminals. The amplifying circuit further comprises a first current source coupled to the intermediate node, which is configured to provide a first bias current which allows the differential current to vary within a predetermined range. The amplifying circuit further comprises an output terminal coupled to the intermediate node, and a second current source coupled to the intermediate node and configured to provide a second bias current. The second bias current compensates the differential current and the first bias current and produces an output current flowing through the output terminal in a predetermined direction. A measurement device is also described.

Abstract: Disclosed is a power amplification module which has a comparatively small size and is capable of adjusting the rising characteristic of a gain. The power amplification module includes a first gain control current generation circuit which generates a first gain control current changing with a control voltage, a first bias current generation circuit which generates a first bias current according to the first gain control current, a gain control voltage generation circuit which generates a gain control voltage changing with the control voltage, a first transistor which is emitter-grounded and in which an input signal and the first bias current are supplied to a base thereof, and a second transistor which is cascode-connected to the first transistor and in which the gain control voltage is supplied to a base thereof and a first output signal obtained by amplifying the input signal is output from a collector thereof.

Abstract: A programmable gain amplifier (PGA) includes an op amp, an input circuit, a feedback circuit, and a calibration circuit. The input circuit is connected between a PGA input node and an op-amp input node and selectively applies the analog input signal to the op-amp input node. The feedback circuit is connected between an op-amp output node and the op-amp input node and applies the amplified analog output signal as a feedback signal to the op-amp input node. The calibration circuit is connected between a calibration reference node and the op-amp input node and selectively connects the calibration reference node directly to the op-amp input node without traversing any of the input circuit. The PGA may be implemented as a single-ended or differential amplifier. The PGA avoids reduced linearity resulting from series combinations of switches in the input circuit when configured for its normal operating mode.

Abstract: The programmable multi-gain current amplifier circuitry includes a pair of MOS transistors setting the voltage at X terminal to zero using negative feedback formed by a third MOS transistor. Input resistance is in the range of few tens of ohms. The input current ix, which is forced by the constant currents of the circuitry, is conveyed to the output port Z by source-coupling a complementary output pair of MOS transistors. Since this coupled pair is biased with a constant tail current, the drain current changes are equal but with opposite sign, regardless of their matching resulting in negative type CA with unity gain (iz=ix). Programmability is achieved utilizing the output stages. When a second differential pair is connected in parallel, it provides two additional current outputs. With the two differential pairs being biased with different tail currents (IT1 and IT2), the outputs are programmed by adjusting these tail currents.

Abstract: A resistive ladder has first, second and third resistors coupled in series between first and second voltage terminals. A first node of the first resistor is coupled to the first voltage terminal and a first node of the third resistor is coupled to the second voltage terminal. A voltage selection unit has a first input coupled to a first node of the second resistor and a second input coupled to a second node of the second resistor and is adapted to selectively couple one of the first and second inputs to an output node of said resistive ladder. The resistive ladder also includes a first switch coupled between a second node of the third resistor and the second voltage terminal.

Abstract: The electronic circuit (1) includes, in an automatic gain control loop, an input amplifier (2), an AGC unit connected to the amplifier output to detect the amplitude of an output signal and a unit (10) for attenuating an input signal of the amplifier based on an adaptation signal (VAGC) from the AGC unit. The attenuation unit includes a means of comparing the adaptation signal to a reference signal (VREF) and for supplying an attenuation current as a function of the difference between the adaptation and reference signals, to a diode-connected PMOS replica transistor (M2), which is connected by a source to a common mode voltage (VCM) dependent on the input signal of the amplifier. The replica transistor controls a PMOS shunt transistor (M1) defining a shunt resistance connected to the amplifier input, whose resistive value depends on the attenuation current passing through the replica transistor.

Abstract: An amplifier circuit has: a main amplifier connected between an input terminal and an output terminal, the main amplifier amplifying an input signal input to the input terminal and outputting an amplified signal to the output terminal; a compensation circuit comprising a variable delay circuit and a variable gain inverting circuit, the variable delay circuit receiving the input signal and outputting a delay signal with a delay time from the input signal, the variable gain inverting amplifier inverting and amplifying the delay signal with a gain and outputting a compensation signal to the output terminal; and a controller configured to control the gain of the pre-emphasis circuit and the delay time of the variable delay circuit to compensate a response of the main amplifier in a first frequency band lower than a base frequency of a target signal of compensation and in a low frequency band higher than zero Hertz.

Abstract: The electronic circuit is arranged for the fast, automatic gain control of an input amplifier. It includes a non-linear amplifier-comparator for comparing a reference signal (VR) to an amplitude signal (VP) at the output of the input amplifier. The amplifier-comparator performs dual slope adaptation of the input amplifier gain according to a defined deviation threshold between the two input signals. The amplifier-comparator includes two branches each with three transistors connected in series between the terminals of a supply voltage source. First and second polarization transistors (M5, M6) are connected to the first and second input transistors (M1, M2) controlled by the first and second input signals, which are respectively connected to a first diode-connected transistor (M3) and a second transistor (M4) of a current mirror. A non-linear transconductance element (RNL) connects the sources of the input transistors to define a dual slope gain adaptation of the non-linear amplifier-comparator.

Abstract: A device comprises a first amplifier, a first resistive element that comprises a first resistor and a first dummy switch, a second amplifier, a second resistive element that comprises a second resistor and a second dummy switch, and a programmable resistive gain element operable to receive control input, wherein a resistance value of the programmable resistive gain element is based at least in part on the received control input, wherein a first end of the programmable resistive gain element is connected to both the first inverting input of the first amplifier and to a second end of the first dummy switch, and wherein a second end of the programmable resistive gain element is connected to both the second inverting input of the second amplifier and to a second end of the second dummy switch.

Abstract: A differential circuit topology that produces a tunable floating negative inductance, negative capacitance, negative resistance/conductance, or a combination of the three. These circuits are commonly referred to as “non-Foster circuits.” The disclosed embodiments of the circuits comprises two differential pairs of transistors that are cross-coupled, a load immittance, multiple current sources, two Common-Mode FeedBack (CMFB) networks, at least one tunable (variable) resistance, and two terminals across which the desired immittance is present. The disclosed embodiments of the circuits may be configured as either a Negative Impedance Inverter (NII) or a Negative Impedance Converter (NIC) and as either Open-Circuit-Stable (OCS) and Short-Circuit-Stable (SCS).

Abstract: An integrated, fully-differential current-feedback transimpedance operational amplifier circuit is disclosed. The circuit can be configured as a class-AB, low-impedance input stage, followed by an inverter-based, rail-to-rail output stage. For enhancing the open-loop transimpedance gain of the amplifier without consuming additional DC power, the same bias current is used both in the input stage and in a gain-enhancement stage serving as its load. The gain-enhancement stage can be either DC- or AC-coupled to the input of the amplifier. In the case of DC coupling, an output common-mode feedback loop can be used to provide the proper operating voltages in the amplifier.

Abstract: An innovative analog circuit design using digital components is disclosed. Embodiments of the present invention includes, but not limited to analog amplifiers and comparators. An amplifier of an embodiment of the present invention includes an inverter, a plurality of switches, offset capacitor and flying capacitor. The one terminal of the offset capacitor is connected to the input of the inverter. During setup phase of clock signals, the switches are configured to connect input and output of the inverter and to connect the flying capacitor to input terminals of the amplifier, respectively, for storing a differential input voltage. Then, during the enable phase of the clock signals, the switches are configured to connect the first terminal of the second capacitor and the first terminal of the first capacitor, and to connect the second terminal of the second capacitor to the output of the inverter.

Abstract: A current voltage conversion circuit includes first to fourth signal amplifiers; and first and second resistive passive elements, an input terminal of the first signal amplifier being connected to a terminal for inputting a current signal, one and the other terminals of the first resistive passive element being connected to output and input terminals of the first signal amplifier, respectively, an input terminal of the second signal amplifier being connected to a first connection point, input and output terminals of the third signal amplifier being connected to an output terminal of the second signal amplifier and the first connection point, respectively, an input terminal of the fourth signal amplifier being connected to a second connection point, and one and the other terminals of the second resistive passive element being connected to an output terminal of the fourth signal amplifier and the second connection point.

Abstract: Circuits for reducing power consumption in power amplifier circuits are disclosed. In certain embodiments, a circuit for power control in the transmitter includes a coupling circuit, a first power amplifier circuit and a second power amplifier circuit. The coupling circuit includes a primary winding inductively associated with a first secondary winding and a second secondary winding. The coupling circuit provides a signal at output terminals of the first secondary winding and the second secondary winding in response to a signal at the primary winding. A first power amplifier circuit is coupled with output terminals of the first secondary winding, and a second power amplifier is coupled with output terminals of the second secondary winding. The first power amplifier circuit and second power amplifier circuit are configured to be enabled or disabled based on a bias voltage.

Abstract: An analog amplifier for recovering an abnormal operation of a common-mode feedback is provided. An analog variable amplifier includes a first input transistor and a second input transistor, a first output transistor and a second output transistor, a third transistor and a fourth transistor, a first current source, a fifth transistor and a sixth transistor, and a second current source. The first input transistor and the second input transistor amplify a bias current depending on a magnitude of a first input voltage and a second input voltage. The first output transistor and the second output transistor output the amplified bias current. The third transistor and the fourth transistor receive an output voltage of the first output transistor as an input and amplifying the received output voltage. The first current source provides a predetermined current between the first output transistor and the third transistor.

Abstract: Embodiments include systems and methods for accurately controlling gain of a high-speed variable-gain amplifier (VGA) without adversely impacting bandwidth performance. Embodiments include a VGA with a variable resistor, for which resistance is a function of a control level. A gain calibration system controls the control level by using a gain control feedback subsystem to sample outputs of a duplicate VGA, which includes a duplicate variable resistor. The sampled duplicate outputs are compared to a target gain generated by a reference generator. The control level can be fed back to control the gain of the duplicate VGA until the target gain is reached. The control level can also be fed to the actual VGA to control its gain. By performing gain control on the duplicate VGA without interfering with the output signal path of the actual VGA, the actual VGA's gain can be accurately controlled without impacting its bandwidth.

Abstract: An inductor-less balun low-noise amplifier (LNA) includes a cross-coupled network coupled between first and second input terminals and first and second summing nodes. The cross-coupled network may include: a first non-inverting gain stage coupled between the first input terminal and the first summing node; a first inverting gain stage coupled between the first input terminal and the second summing node; a second non-inverting gain stage coupled between the second input terminal and the second summing node; and a second inverting gain stage coupled between the second input terminal and the first summing node. The cross coupled network may be configurable to provide common-mode rejection when operated in a differential or in a single-ended mode of operation.

Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

Abstract: Improved preamplifier circuits for converting single-ended input current signals to differential output voltage signals, including first and second transimpedance amplifiers with input transistors operating according to bias currents from a biasing circuit, output transistors and adjustable feedback impedances modified using an automatic gain control circuit, as well as a reference circuit controlling the bias currents according to an on-board reference current and the single-ended input or the differential output voltage signals from the transimpedance amplifiers.

Abstract: A semiconductor device capable of achieving high speed performance in addition to correction of differential offset and a communication device provided with the semiconductor device are provided. For example, there are provided: a variable gain type differential amplifier circuit VGA1 which receives a gain setting signal ASET, which amplifies differential input signals INP and INN by a gain indicated by the gain setting signal, and which outputs differential output signals OUTP? and OTUN?; and an offset correcting circuit unit OFCBK1 which cancels an offset voltage (VOF and VOFO) generated in the VGA1. Here, the OFCBK1 cancels an output offset voltage VOFO (which results in an input offset voltage VOF) by receiving the ASET, generating a correction voltage changed in accordance with the gain, and adding the correction voltage to the OUTP? and OUTN?.

Abstract: The present invention discloses a gain control circuit capable of easing leakage current influence. According to an embodiment of the present invention, the gain control circuit comprises: at least one signal input end for receiving at least one input signal; a signal output end for outputting an output signal; an amplifier coupled between an amplifier input end and the signal output end; and a plurality of gain schemes. Each of the gain schemes is set between the at least one signal input end and the signal output end; and when one of the gain schemes is activated to generate the output signal, the rest gain schemes are inactivated to stop gain production and concurrently discharge leakage currents through their respective grounding paths.

Abstract: The programmable multi-gain current amplifier circuitry includes a pair of MOS transistors setting the voltage at X terminal to zero using negative feedback formed by a third MOS transistor. Input resistance is in the range of few tens of ohms. The input current ix, which is forced by the constant currents of the circuitry, is conveyed to the output port Z by source-coupling a complementary output pair of MOS transistors. Since this coupled pair is biased with a constant tail current, the drain current changes are equal but with opposite sign, regardless of their matching resulting in negative type CA with unity gain (iz=ix). Programmability is achieved utilizing the output stages. When a second differential pair is connected in parallel, it provides two additional current outputs. With the two differential pairs being biased with different tail currents (IT1 and IT2), the outputs are programmed by adjusting these tail currents.

Abstract: A low noise amplifier including a variable gain amplifier stage configured to accept an input signal and to provide a load driving signal; a tunable bandpass filter connected as a load to the variable gain amplifier stage, wherein the bandpass filter includes a cross-coupled transistor pair, and at least one cross-coupled compensation transistor pair biased in a subthreshold region configured to add a transconductance component when the load driving signal is of a magnitude large enough to decreases a transconductance of the cross-coupled transistor pair; and, a controller circuit configured to tune the bandpass filter. The filter can be tuned in respect to the frequency and the quality factor Q.

Abstract: A differential circuit with a function to compensate the gain enhancement due to the self-heating of the transistor is disclosed. The differential circuit includes an equalizer unit coupled with one of paired transistors. The other of the paired transistor receives the input signal to be amplified. The base level, or the base-emitter bias, is oppositely modulated by the input signal through the common emitter, which causes the modification of the base current. The equalizer unit reduces the variation of the base level only in low frequencies where the self-heating effect of the transistor appears.

Abstract: The present document relates to multi-stage amplifiers, such as linear regulators or linear voltage regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients. A multi-stage amplifier is described. The multi-stage amplifier comprises a first amplification stage configured to provide a stage output voltage at a stage output node. Furthermore, the amplifier comprises an intermediate amplification stage comprising an amplifier current source configured to provide an amplifier current and an amplifier transistor arranged in series with the amplifier current source. A gate of the amplifier transistor is coupled to the stage output node of the first amplification stage. The intermediate amplification stage is configured to provide an amplified or attenuated stage output voltage at a midpoint between the amplifier current source and the amplifier transistor.

Abstract: The present document relates to multi-stage amplifiers, such as linear regulators or linear voltage regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients. A multi-stage amplifier is described, having a differential amplification stage which comprises a differential transistor pair. The differential amplification stage is configured to provide a stage output voltage at a stage output node of the differential transistor pair, based on a first input voltage at a first stage input node and a second input voltage at a second stage input node. The differential transistor pair also comprises a reference node. The differential amplification stage further comprises an active load comprising a first diode transistor coupled to the reference node and a first mirror transistor coupled to the stage output node.

Abstract: A system includes a first variable gain amplifier configured to receive an input signal and a first down-mixer coupled to the first variable gain amplifier. Also, the system includes a first current conveyor coupled to the first down mixer, where the first current conveyor includes a first cascode and a second cascode coupled to the first cascode. Additionally, the system includes a first channel filter coupled to the first current conveyor and a second variable gain amplifier coupled to the first channel filter.

Abstract: An electronic component includes: a first amplifier configured to amplify one of differential signals; a second amplifier configured to amplify another one of the differential signals; a sensor configured to measure voltages of a first output signal outputted from the first amplifier and a second output signal outputted from the second amplifier; and a controller configured to control, based on the voltages measured by the sensor, either one or both of a current and a resistance value of the first amplifier so that a common voltage of the first output signal and a common voltage of the second output signal are approximate to each other.

Abstract: This invention provides a voltage controlled variable gain amplifier circuit that varies its gain linearly and continuously against a gain control voltage VC. The voltage controlled variable gain amplifier circuit includes a first differential amplifier, a second differential amplifier, a gain control voltage/current conversion circuit and a reference current generation circuit. The first differential amplifier and the second differential amplifier are connected in series. The gain control voltage/current conversion circuit converts the gain control voltage VC into a gain control current IC that varies linearly against the gain control voltage VC. Drain currents Id1 and Id2 of first and second differential input transistors vary linearly against the gain control current IC.

Abstract: An RF amplifier includes an input stage, a buffer stage, and an output stage. The input stage is configured to provide attenuation and impedance matching for an input radio frequency (RF) signal by providing shunt and series variable resistance current paths and RF power to RF current conversion. The input stage routes the RF current between the current paths resulting in an attenuation of the RF input current. The buffer stage is configured to provide an intermediate RF current which tracks the current level of the attenuated RF input current, thereby providing isolation between the input and output stages. The output stage is configured to provide RF current to RF power conversion, utilizing the intermediate RF current to provide an RF signal having an RF output power proportional to the RF input power.

Abstract: The embodiments of the present invention disclose a variable gain amplifier and relate to the field of electronic circuits. The linear-in-dB relationship between an output current and a control voltage of the variable gain amplifier is relatively ideal. The variable gain amplifier includes a fitted differential module group and an offset voltage output module, where the fitted differential module group is configured to output, under the control of a driving voltage and offset voltages, an output current of the variable gain amplifier according to a reference current; and the fitted differential module group includes n fitted differential modules, the n fitted differential modules are cascaded in turn, and n is any positive integer larger than 1.

Abstract: The present disclosure provides a signal processing apparatus including: a short-circuiting controlling section configured to control whether or not the input side of a resistor connected between an input terminal and an output terminal and the output terminal are to be short-circuited in response to a signal level of a signal inputted from the input terminal; and a connection controlling section configured to control whether or not a resistor member is to be connected between the output terminal and a reference potential in response to the signal level of the signal, wherein at least one of the short-circuiting controlling section and the connection controlling section includes a plurality of switches disposed in parallel to each other for changing over a state thereof between open and closed states at signal levels different from each other.

Abstract: A true ground amplifier circuit in which a voltage sensor senses the output voltage and generates a binary output which indicates whether the output is above or below a threshold. A variable gain feedback system generates a feedback signal for combination with the digital input, thereby to provide offset cancellation. The variable gain is reduced over time to provide offset cancellation during an initial period of time of operation of the amplifier circuit. This provides offset cancellation during a start-up period, for example.