Abstract: A simplified VCA circuit is presented. The VCA of the present invention uses fewer components and is less complex than prior art OTA-based VCAs. Further, the VCA of the present invention has improved total harmonic distortion (THD) and DC offset characteristics as compared to prior art VCAs. The VCA may be used to prevent clipping with the addition of clipping detection circuitry.

Abstract: A system for cancelling offset includes a gain circuit. The gain circuit may include a transistor circuit connected to a pair of input nodes and configured to convert an input signal to an output signal so that the output signal has a gain compared with the input signal. The gain circuit also may include a pair of output nodes configured to receive the output signal from the transistor circuit. The gain circuit is configured to cause a voltage change at one of the output nodes relative to another output node, in response to the gain circuit receiving a feedback offset correction signal.

Abstract: A method and apparatus are provided for using an automatic BW adjustment circuit to automatically adjust the bandwidth of an electronic amplifier based on the amplitude of a signal that is output from a variable gain amplifier or of one or more variable gain stages that follow the amplifier. By automatically adjusting the bandwidth of the electronic amplifier based on the amplitude of the signal, bandwidth enhancement can be provided while also preventing, or at least reducing, peaking of the frequency response of the electronic amplifier.

Abstract: A variable gain amplifier has an attenuator having an input and a series of tap points, and a series of low-inertia switches, each switch coupled to a corresponding one of the tap points to steer outputs from the attenuator to an output terminal. An amplifier has an input cell, a load coupled to an output of the input cell, a buffer having an input coupled to the load, a feedback network coupled between an output of the buffer and the input cell, and a variable filter cell coupled to the input cell.

Abstract: The present invention relates to an operational amplifier having low power consumption, which comprises a differential circuit, an output-stage circuit, and a floating bias generating circuit. The differential circuit receives an input signal and produces a control signal. The output-stage circuit is coupled to the differential circuit and produces an output signal according to the control signal. The floating bias generating circuit is coupled between the differential circuit and the output-stage circuit and generates a floating bias according to the control signal for controlling the rising or lowering of the voltage level of the output signal. Accordingly, the operational amplifier can charge and discharge rapidly, and thus extending the applications of the operational amplifier. Besides, the floating bias generating circuit can limit the output current while the operational amplifier is driving, and thus achieving the purpose of low power consumption.

Abstract: According to an embodiment, a variable gain amplifier includes a differential transistor pair including a first and second transistor. A variable resistor for setting a gain is connected between electrodes the transistor pair. A first variable capacitor is connected to an electrode of the first transistor, and a second variable capacitor is connected to an electrode of the second transistor. Corresponding to the gain setting set by adjusting the variable resistor, capacitance values of the variable capacitors can be adjusted to provide improved frequency characteristics of the variable gain amplifier.

Abstract: A system includes a first variable gain amplifier configured to receive an input signal and a first down-mixer coupled to the first variable gain amplifier. Also, the system includes a first current conveyor coupled to the first down mixer, where the first current conveyor includes a first cascode and a second cascode coupled to the first cascode. Additionally, the system includes a first channel filter coupled to the first current conveyor and a second variable gain amplifier coupled to the first channel filter.

Abstract: A method is provided for process, voltage, temperature (PVT) stable transfer function calibration in a differential amplifier. The gain resistors of a differential amplifier are initially selected to achieve a flat amplitude transfer function in the first frequency band. After calibration, the degeneration capacitor is connected and tuned until a peaked amplitude transfer function is measured, which is resistant to variations in PVT. As an alternative, the degeneration capacitor is not disconnected during initial calibration. Then, the gain resistors and the degeneration capacitor values are selectively adjusted until the first peaked amplitude transfer function is obtained. The peaked amplitude transfer function remains even more stable to variations in PVT than the flat amplitude calibration method.

Abstract: Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.

Abstract: Embodiments provide a gm-ratioed amplifier. The gm-ratioed amplifier comprises a first input voltage terminal and a second input voltage terminal, a first output voltage terminal and a second output voltage terminal, and an amplifying unit. The amplifying unit may be coupled between the input voltage terminals and the output voltage terminals and may be adapted to supply an output voltage to the output terminals in dependence on an input voltage supplied to the input terminals. The amplifying unit may comprise a gm-load, which comprises a first load branch comprising a first field effect transistor, and a second load branch comprising a second field effect transistor. A first source/drain terminal and a gate terminal of the first field effect transistor may be coupled to the first output voltage terminal, and a first source/drain terminal and a gate terminal of the second field effect transistor may be coupled to the second output voltage terminal.

Abstract: A differential circuit with a function of a variable gain without shifting the output cross point is disclosed. The differential circuit includes an amplifying stage and a control stage. The amplifying stage includes three units each having a pair of transistors, a pair of load resistors, and a pair of current sources. The second and third units each put between the first unit and the load resistor to bypass the current. The control stage includes two units and two current sources to compensate the current bypassed by the second or third unit to keep the DC output level substantially in constant.

Abstract: An apparatus with associated gain and input impedance includes gain devices, a switching unit and a resistor. A first differential pair of gain devices and associated bias circuitry is configured to operate in a full gain mode. A second differential pair of gain devices is configured to operate in a reduced gain mode. The switching unit is configured to disable the first differential pair of gain devices and enable the second differential pair of gain devices in the reduced gain mode and to disable the second differential pair of gain devices and enable the first differential pair of gain devices in the full gain mode. The resistor is configured to maintain constant input impedance of the apparatus when in the reduced gain mode.

Abstract: An apparatus having a circuit is disclosed. The circuit may be configured to (i) receive an input signal from a communication channel and (ii) generate an intermediate signal by amplifying the input signal (a) by a low-frequency gain in response to an amplitude control signal and (b) by a high-frequency gain in response to a boost control signal.

Abstract: A circuit including an amplifier, a transistor, and first, second and third resistances. The amplifier includes an input and an output. The amplifier receives an input signal. A cycle of the input signal includes first and second pulses. The input signal is asymmetrical such that the first pulse has a different peak magnitude than the second pulse. The transistor is connected to the input and the output. The first, second, and third resistances are each connected to the input of the amplifier. The second resistance receives a first input voltage. The third resistance receives a second input voltage. The input signal is based on the first resistance and the first and second input voltages. The amplifier corrects some asymmetry of the input signal to provide an output signal. An amount of asymmetry of the output signal is based on (i) the input signal, and (ii) a state of the transistor.

Abstract: An operational amplifier (10) capable of driving a capacitive load (CLOAD) and/or a resistive load (RLOAD) includes a first gain stage (2) having an output coupled to a high impedance node (3) and a second gain stage (5) having an input coupled to the first high impedance node. A gain reduction resistor (RD) and an AC coupling capacitor (CD) are coupled in series between the high impedance node and a reference voltage. A Miller feedback capacitor (CM) is coupled between an output conductor (7) of the second gain stage and the high impedance node. The output of the second gain stage may be coupled to the high impedance node by a cascode transistor (MCASCODE).

Abstract: A dynamic feed-forward OPAMP-based circuit is provided. A first amplifying stage amplifies a pair of input differential signals to provide a pair of intermediate differential signals. A second amplifying stage amplifies the pair of intermediate differential signals to provide a pair of output differential signals. A first capacitor is coupled to a non-inverting input terminal of the first amplifying stage. A second capacitor is coupled to an inverting input terminal of the first amplifying stage. A feed-forward transconductance stage is coupled between the first and second capacitors and the second amplifying stage. The first and second capacitors and the feed-forward stage form a high-frequency path with a first gain curve, and the first amplifying stage and the second amplifying stage form a high-gain path with a second gain curve. The operational amplifier provides an open-loop gain according to the first and second gain curves.

Abstract: A signal processing apparatus and method are disclosed. A common mode signal extraction unit is configured to extract a common mode signal from input signals inputted to a differential amplifier. A common mode signal adjustment unit is configured to adjust a gain and a phase of the common mode signal and to output the adjusted common mode signal to the differential amplifier. An optimal set determination unit is configured to determine an optimal gain and phase to be applied to the common mode signal based on an output signal from the differential amplifier.

Abstract: A voltage clamping module is disposed at an output terminal of a gain amplifying module, so that a voltage level of an amplifying signal outputted by the gain amplifying module can be clamped within a predetermined range. The voltage clamping module includes an upper bound voltage clamping module, which is utilized for limiting the voltage level of the amplifying signal to be lower than an upper bound voltage level, and a lower bound voltage clamping module, which is utilized for limiting the voltage level of the amplifying signal to be higher than a lower bound voltage level.

Abstract: A decision feedback equalizer is disclosed. The decision feedback equalizer comprises an amplifier circuit and a latch. The amplifier circuit is configured to receive an input signal, a decision feedback signal and a control signal, and is configured to adjust its driving capability according to the decision feedback signal and the control signal to provide an amplified signal of the input signal. The latch is configured to latch the amplified signal as an output signal.

Abstract: A variable gain amplifier circuit (300) comprising a first transistor (310) and a second transistor (312); and an additional transistor (320). The first transistor (310) and second transistor (312) are arranged as common base transistors. The additional transistor (320) is configured to provide part of a translinear loop with the first (310) and second transistors (310). A current through the conduction channel of the first transistor (310) is configured to contribute to an output of the variable gain amplifier circuit current. The circuit (300) is configured such that a current through the conduction channel of the second transistor (312) is copied to the additional transistor (322).

Abstract: A continuous variable gain amplifier includes an attenuator network, a boost network, a first amplifying network, and a second amplifying network, where the attenuator network generates first differential output signals according to an input signal and sends the first differential output signals to the first amplifying network and the second amplifying network; the first amplifying network and the second amplifying network receive one output of the first differential output signals each, and generate a first final output signal and a second final output signal respectively according to an externally input control voltage; and the boost network receives the first final output signal and the second final output signal, generates second differential output signals, and sends a first output and a second output of the second differential output signals to the first amplifying network and the second amplifying network, respectively

Abstract: A radio frequency (RF) power amplifier (PA) is reconfigured to operate in a low power mode from a high power mode. The RF PA has a first RF amplifier is connected to the first and second inputs of a first transformation network. The RF PA has a second a second RF amplifier connected to a second transformation network. During high power mode, both RF amplifiers drive a load coupled to the transformation networks. In low power mode the first RF amplifier is disabled and the first and second inputs of the first transformation are coupled together so as to change the load impedance seen by the second RF amplifier. The second RF amplifier continues to supply power to the load during operation in the low power mode.

Abstract: An embodiment of the present invention provides a configuration of a cross-coupled common-source differential amplifier stage which enables performing a gain step down (attenuation) while maintaining good step flatness over a large relative bandwidth.

Abstract: In certain embodiments, circuits and methods for time gain compensation are provided. A circuit includes a first op-amp that is configured to compare a first and a second input voltage signal received from first and second input circuits, respectively, and output a first op-amp output signal. A control circuit coupled with a first semiconductor element of the second input circuit is configured to vary a first resistance value of the first semiconductor element to control the first op-amp output signal. The first op-amp output signal includes a relatively high voltage signal and a relative low voltage signal when an input control voltage signal corresponds to a first reference voltage and a second reference voltage signal, respectively associated with the first op-amp. The first op-amp output signal is input to a gate terminal of a load semiconductor element so-as to vary an impedance of the load semiconductor element.

Abstract: In certain embodiments, circuits and methods for time gain compensation are provided. A circuit includes a first op-amp that is configured to compare a first and a second input voltage signal received from first and second input circuits, respectively, and output a first op-amp output signal. A control circuit coupled with a first semiconductor element of the second input circuit is configured to vary a first resistance value of the first semiconductor element to control the first op-amp output signal. The first op-amp output signal includes a relatively high voltage signal and a relative low voltage signal when an input control voltage signal corresponds to a first reference voltage and a second reference voltage signal, respectively associated with the first op-amp. The first op-amp output signal is input to a gate terminal of a load semiconductor element so-as to vary an impedance of the load semiconductor element.

Abstract: This invention provides a multi-stage amplifier incorporating DC offset cancellation. The amplifier has a plurality of series-connected gain stages each of which comprises a differential amplifier unit generating a pair of differential outputs from a pair of differential inputs. In particular, a trailing stage in the plurality of gain stages comprises a digital DC offset cancellation module configured to compensate for a DC offset of the trailing stage's differential amplifier unit. The digital DC offset cancellation module comprises a comparator coupled to the pair of differential outputs of the trailing stage's differential amplifier unit for receiving such differential outputs as inputs for the comparator. Preferably, the comparator has an inherent DC offset that is substantially small. It is preferable that a non-trailing stage of the amplifier comprises an analog DC offset cancellation module for compensating for a DC offset of the non-trailing stage.

Abstract: Apparatus and methods for voltage comparison are provided. In one embodiment, a comparator includes a first input transistor having a gate configured to receive a first input voltage and a second input transistor having a gate configured to receive a second input voltage. The first and second input transistors can be used to compare the first input voltage to the second input voltage. Additionally, the comparator further includes a first Miller capacitor electrically connected to a drain of the first input transistor and a second Miller capacitor electrically connected to a drain of the second input transistor. Furthermore, first and second inverting amplification circuits are electrically connected across the first and second Miller capacitors, respectively, so as to increase the effective capacitance of the capacitors. The first and second Miller capacitors can be used to extend the comparator's integration time, thereby enhancing the performance of the comparator.

Abstract: Memories, sense amplifiers, and methods for amplifying a current input are disclosed, including a sense amplifier including a bias circuit configured to provide a bias voltage having a magnitude responsive to maintaining a substantially constant loop gain, and further including an amplifier stage coupled to the bias circuit to receive the bias voltage and configured to amplify a input current at an input-output node, a loop gain of the current amplifier stage is controlled at least in part to the bias voltage.

Abstract: A direct current-to-direct current (‘DC/DC’) converter for delivering a load to an electrical component, the DC/DC converter including: a coupled inductor, wherein the coupled inductor receives a source input voltage level and a outputs an output voltage level; a transient winding; and a variable impedance switch coupled to the transient winding, the variable impedance switch configured to operate by adjusting a delivered resistance level in dependence upon a change in the load to be delivered to the electrical component by the DC/DC converter.

Abstract: An amplifier circuit includes: a first transistor and a second transistor of which collectors/drains are coupled to a first power-source via a first load-impedance-element and the first power-source via a second load-impedance-element, respectively; a gain-adjustment-resistance-element that is connected to an emitter/source of the first transistor and an emitter/source of the second transistor; a first current-source and a second current-source that are connected to the emitters/the sources of the first transistor and the second transistor respectively, and a second power-source; a third transistor and a fourth transistor of which collectors/drains are connected to the first power-source and bases/gates are connected to the first load-impedance-element and the second load-impedance-element, respectively; a first feedback-resistance-element that is connected to a base/gate of the first transistor and an emitter/source of the third transistor; and a second feedback-resistance-element that is connected to a base

Abstract: An analog to digital converting device includes a first digital conversion (ADC) circuit configured to convert an inputted analog signal into a first digital signal, a first multiplying digital to analog converting (MDAC) circuit configured to amplify a difference between a first converted signal and the inputted analog signal, a second ADC circuit configured to convert an output of the first MDAC circuit into a second digital signal, a second MDAC circuit configured to amplify difference between a second converted signal converted from the second digital signal and the output of the first MDAC circuit, a third ADC circuit configured to convert an output of the second MDAC circuit into a third digital signal, and a common amplifying circuit shared by the first and the second MDAC circuits, wherein the common amplifying circuit consumes current based on which MDAC circuit the common amplifying circuit operates with.

Abstract: A system is provided to protect a loudspeaker (144) by controlling a level of an applied audio signal. A control signal is generated by applying an input audio signal (115) to the collective operations of a gain control system (100). The gain control system (100) uses the input audio signal (115) in conjunction with at least one parameter to derive an estimated stress associated with the loudspeaker (144). The estimated stress is compared with a protection threshold stress (127). If the protection threshold stress is exceeded, a gain applied by a gain component (134) is selectively adjusted to modify the input audio signal (115). The resulting gain-controlled audio signal (116) is employed to drive the loudspeaker (144).

Abstract: Techniques for optimizing a cascade gain device comprising at least two gain stages are disclosed. A first noise figure associated with the first gain stage is incrementally increased by a plurality of noise figure increments determined based, at least in part, on a minimum noise figure and a maximum noise figure associated with the first gain stage. At each of the plurality of noise figure increments, at least a gain value that corresponds to the noise figure increment is calculated. One of the plurality of noise figure increments and the corresponding gain value is selected as an optimum noise figure of the first gain stage and an optimum gain value of the first gain stage respectively. Parameters of an inter-stage matching network associated with the first gain stage are configured based on the optimum noise figure and the optimum gain of the first gain stage.

Abstract: The selectable gain differential amplifier includes a differential amplifier, a plurality of cascade leg pairs connected to the differential amplifier, each leg of each cascode pair including a cascode device and a load resistor configured to provide a selectable gain. A variable voltage generator is connected to each leg configured to set gain resistor voltage of any active cascode leg pair to a uniform predetermined common mode voltage and the output node voltage of any inactive cascode leg pair to a voltage different from the predetermined common mode voltage. A selector circuit is configured to select the output of any said cascode leg pair.

Abstract: An apparatus with associated gain and input impedance includes gain devices, a switching unit and a resistor. A first differential pair of gain devices and associated bias circuitry is configured to operate in a full gain mode. A second differential pair of gain devices is configured to operate in a reduced gain mode. The switching unit is configured to disable the first differential pair of gain devices and enable the second differential pair of gain devices in the reduced gain mode and to disable the second differential pair of gain devices and enable the first differential pair of gain devices in the full gain mode. The resistor is configured to maintain constant input impedance of the apparatus when in the reduced gain mode.

Abstract: The invention concerns a detection device including a photodiode (Ph) designed to capture a luminous signal to transform it into a current (Iph) and including first and second terminals, a transimpedance amplifier circuit connected between the first terminal and the second terminal of the photodiode (Ph) and designed to amplify the current (Iph) coming from the photodiode (Ph). The transimpedance amplifier circuit includes a plurality of operational amplifiers (AOP1, AOP2, AOP3) connected in parallel and a gain resistor (Rgain) common to all the connected amplifiers.

Abstract: A variable gain amplifier circuit is disclosed. The variable gain amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first gain switching circuit, and a second gain switching circuit. The first and the second transistors are respectively coupled to the first and the second nodes for receiving a differential input signal pair. The third transistor is coupled between the first node and a third node. The fourth transistor is coupled between the second node and a fourth node. The first gain switching circuit is coupled between the first node and the third node and further cross-coupled to the fourth node. The second gain switching circuit is coupled between the second node and the fourth node and further cross-coupled to the third node.

Abstract: Techniques for providing adjustable gain in an amplifier. In an aspect, a composite amplifier having adjustable gain includes a plurality of amplifiers coupled in parallel, wherein each of the amplifiers may be turned on or off to adjust the overall gain of the composite amplifier. Each amplifier may include an input transistor and at least two cascode transistors. To turn each amplifier off, the gate voltage of a second or lowermost cascode transistor coupled to the input transistor may be grounded, and the gate voltage of a first cascode transistor coupled to the output voltage may be coupled to a first turn-off voltage to reduce the drain-to-gate voltage drop across the first cascode transistor.

Abstract: A variable gain amplifier canceling the dependence of the frequency bandwidth thereof on the gain is disclosed. The variable gain amplifier includes a differential stage with a cascade transistor put between an amplifying transistor and a load resistor. The amplifier further includes a current supplier and a current extractor. The current supplier extracts a current flowing in the second transistor by supplying an additional current to the amplifying transistor. The current extractor adds the additional current flowing in the load resistor which is extracted by the additional current by the current supplier. The bias condition of the load resistor is kept substantially constant independent of the equivalent impedance of the cascade transistor.

Abstract: An adjustable gain amplifier system having cleanly adjustable and stable linearized gain is provided for amplifying an input signal. The system generally comprises a main amplifier and a linearized transconductance amplifier coupled thereto, which generates an amplified current signal in response to the input signal according to a variably defined transconductance factor. The linearized transconductance amplifier includes a linearized transconductance portion and a translinear current amplifier portion coupled thereto. The linearized transconductance portion generates an intermediate current signal based upon a voltage of the input signal, and forms an unswitched resistor-based conduction path for that intermediate current signal. The translinear current amplifier portion forms a translinear loop section for amplifying the intermediate current signal to generate the amplified current signal.

Abstract: The electronic circuit is arranged for the fast, automatic gain control of an input amplifier. It includes a non-linear amplifier-comparator for comparing a reference signal (VR) to an amplitude signal (VP) at the output of the input amplifier. The amplifier-comparator performs dual slope adaptation of the input amplifier gain according to a defined deviation threshold between the two input signals. The amplifier-comparator includes two branches each with three transistors connected in series between the terminals of a supply voltage source. First and second polarisation transistors (M5, M6) are connected to the first and second input transistors (M1, M2) controlled by the first and second input signals, which are respectively connected to a first diode-connected transistor (M3) and a second transistor (M4) of a current mirror. A non-linear transconductance element (RNL) connects the sources of the input transistors to define a dual slope gain adaptation of the non-linear amplifier-comparator.

Abstract: A system and method are provided for delivering power to a dynamic load. The system includes a power supply providing DC power having a substantially constant power open loop response, a power amplifier for converting the DC power to RF power, a sensor for measuring voltage, current and phase angle between voltage and current vectors associated with the RF power, an electrically controllable impedance matching system to modify the impedance of the power amplifier to at least a substantially matched impedance of a dynamic load, and a controller for controlling the electrically controllable impedance matching system. The system further includes a sensor calibration measuring module for determining power delivered by the power amplifier, an electronic matching system calibration module for determining power delivered to a dynamic load, and a power dissipation module for calculating power dissipated in the electrically controllable impedance matching system.

Abstract: An RE receiver is described comprising a common gate common source LNA with a variable resistor in the source of the common gate transistor, a variable resistor in the source of the common source transistor, and a variable resistor in the RE input. A Smart Gain Control varies the resistance in the resistors to produce linear amplification in the LNA while maintaining input matching. Further, a broad dynamic range RSSI is described that implements a feedback control loop to maintain signal power within a sensitivity range of the power detector in the RSSI.

Abstract: The present disclosure relates to variable-gain low noise amplifiers and RF receivers. An exemplary method for processing a RF signal provides a low noise amplifier with main and auxiliary amplifier modules. When a selection indicates the low noise amplifier operating in a high-gain mode, the main and auxiliary amplifier modules are coupled in parallel. When the selection indicates the low noise amplifier operating in a low-gain mode, the main and auxiliary amplifier modules are cross coupled. When a selection indicates the low noise amplifier operating in a moderate-gain mode, the auxiliary amplifier modules are disconnected from the main amplifier module.

Abstract: The present invention relates to a readout circuit for a touch sensor which can increase touch sensing sensitivity regardless of a process variation and a driving voltage of the touch sensor. The readout circuit includes a comparative circuit for setting an input range of a readout signal from the readout line as well as scaling the readout signal to be a required driving range and forwarding the readout signal scaled thus as a touch sensing signal, and an analog to digital converter for converting the touch sensing signal from the comparative circuit as a digital sensing signal and forwarding the digital sensing signal.

Abstract: An apparatus comprising a first line driver, a second line driver, a charge pump, and a control logic circuit coupled to the first line driver and the second line driver and configured to disable the charge pump when both a first control signal associated with the first line driver and a second control signal associated with the second line driver indicate a charge pump disable state. A network component comprising at least one processor configured to implement a method comprising receiving a first control signal and a second control signal, disabling a charge pump when both the first control signal and the second control signal indicate a charge pump disable state, and operating the charge pump to boost a voltage when the first control signal, the second control signal, or both indicate a charge pump active state.

Abstract: An amplifier with gain boosting is disclosed according to an aspect of the subject technology. The gain boosting may be used to improve the noise figure of the amplifier, and may be achieved by feeding an input signal to the gates of multiple transistors in the amplifier, where each transistor provides a current gain contributing to the total current gain of the amplifier. The amplifier may also include an output driver stage for increasing the driving capability of the amplifier. The amplifier may also include a feedback resistor and an input resistor to obtain a gain with high linearity.

Abstract: In one embodiment, an apparatus includes an amplifier configured to receive an asymmetric signal. A first resistance is coupled between an input node and an output node of the amplifier. A second resistance is coupled to the input node of the amplifier. A first switch is configured to be controlled during a first interval to couple the second resistance to a positive resistance to increase a gain of the amplifier to correct the asymmetric signal. The gain is a function of the first resistance and a combination of the second resistance and the positive resistance. A second switch is configured to be controlled during a second interval to couple the second resistance to a negative resistance to decrease the gain of the amplifier to correct the asymmetric signal. The gain is a function of the first resistance and a combination of the second resistance and the negative resistance.

Abstract: A gain control system may include an input terminal that receives an input signal. The gain control system may include a first transistor having a source connected with the input terminal and a drain connected with an output terminal. The gain control system may include a second transistor having a gate connected with the input terminal and the source of the first transistor. The second transistor may have a drain connected with the output terminal. The second transistor may generate a reduction signal. The output terminal may output an output signal based on the input signal and the reduction signal.

Abstract: A voltage generating circuit includes a range adjusting unit configured to output a code signal for adjusting the range of an output voltage and to determine a magnitude of the output voltage to set a control code while an output range adjusting operation is performed. The range adjusting unit is configured to output the code signal in response to a data code received from the outside after the output range adjusting operation is complete. The voltage generating circuit includes a digital analog converter configured to output a conversion voltage in response to the code signal, and an output unit configured to set an amplification gain thereof according to the control code and to amplify the conversion voltage according to the amplification gain to output the output voltage.