Abstract: An apparatus and method for increasing a slew rate of an operational amplifier are provided. It only requires an operational amplifier, a monitoring control device, a push-pull output device, and a second input current source pair. It uses a monitoring control device controlled by the output stage to control the supplementary device and the second input current source pair in order to increase a slew rate of an operational amplifier. This operational amplifier also provides the rail-to-rail output function. In addition, because it does not require additional circuit to increase the slew rate, the chip size is smaller. With respect to the circuit structure, it is very simple and can be applied to the pre-existing operational amplifier without re-designing the operational amplifier and thus can keep the original characteristics of the operational amplifier.

Abstract: A boosting circuit is disclosed. The boosting circuit includes an input circuit part for outputting a differential current proportional to input voltages; a bias circuit part for mirroring the differential current, and producing an inverted differential current that the differential current is inverted; and an output circuit part for adjusting magnitudes of the differential current and the inverted differential current based on a predetermined ratio of MOS transistors, respectively, adding the adjusted differential current and inverted differential current, and producing an output current in a push-pull form. Accordingly, the boosting circuit has a broad maximum differentiable frequency bandwidth, and facilitates the adjustments of differentiation characteristics of an output current. Further, an amount of output current of differentiation form is not affected by external factors such as voltages, processes, temperatures, and so on.

Abstract: An amplifier circuit has a simple circuit architecture that enables a push-pull output function while exhibiting low power consumption. The amplifier circuit includes a first transconductance amplifier to which an output of a two-input differential amplifier and a first bias voltage are input. An output of the first transconductance amplifier is connected to another input and an output of a second transconductance amplifier, which has one input thereof connected to an output of the first transconductance amplifier and a gate of a first output transistor. The output of the differential amplifier is connected to a gate of a second output transistor, which has the polarity opposite to the polarity of the first output transistor. Drains of the first and the second output transistors are connected to each other thus constituting a push-pull output.

Abstract: A transconductance amplifier generally limits its current output, and specifically decreases its current output as a function of temperature. The circuit is made up of an operational amplifier and two drive transistors that are connected to a first part of the amplifier circuit and a second part of the amplifier circuit respectively. The first part of the circuit is driven by positive input voltages, and the second part of the circuit is driven by negative input voltages. A transistor in each part of the circuit clamps a voltage, thereby limiting the current output. The negative temperature coefficient of the transistor also decreases the output current as the temperature of the circuit rises.

Abstract: An ultra-low voltage rail-to-rail operational transconductance amplifier (OTA) is based on a standard digital 0.18 ?m CMOS process. Techniques for designing a 0.8 volt fully differential OTA include bias and reference current generator circuits. To achieve rail-to-rail operation, complementary input differential pairs are used, where the bulk-driven technique is applied to reduce the threshold limitation of the MOSFET transistors. The OTA gain is increased by using auxiliary gain boosting amplifiers.

Abstract: A class AB output stage of a CMOS amplifier has a level-shifting voltage follower constituted by a level-shifting transistor and a current source. A bias circuit replicates the level-shifting voltage follower in a feedback arrangement to produce a variable bias voltage for the current source of both the main and replica level-shifters. The arrangement serves to control the output voltage of the level-shifter such that it provides the amplifier with a relatively constant quiescent current of the output stage over variations of manufacturing process, supply voltage, and temperature. The level shifting function can be facilitated by a resistive on-state of a power-down transistor between the level-shifting and load transistors.

Abstract: A CMOS operational amplifier with a Class AB output stage has an output terminal and an input stage driving the output stage. The Class AB output stage includes a pair of p-channel and n-channel output transistors series-connected between the VDD and VSS supply terminals of a power supply. Each of the output transistors has associated biasing circuitry with a pair of positive and negative driving inputs and a biasing input. The input stage has driving outputs connected to corresponding ones of the driving inputs of the output stage. Each driving output is derived from the drain of a MOS transistor connected in series with a diode connected MOS transistor between the VDD and VSS supply terminals. By avoiding the conventional stacked MOSFETs that would set the minimum supply voltage to more than two threshold voltages, the op-amp can be operated over the full range of supply voltage.

Abstract: A CMOS-implemented transconductance amplifier has an input gain stage coupled to a CMOS output stage. The inverting input of the input gain stage is coupled to an input/output port to which an input voltage is coupled. The CMOS output stage has a first, transconductance CMOS transistor pair, whose source-drain paths are series-coupled between first and second outputs of the input stage. A second, transimpedance CMOS transistor pair have their source-drain paths series-coupled between first and second power supply terminals, and gate inputs coupled to outputs of the input stage. A third CMOS transistor pair is coupled in parallel with the second CMOS transistor pair to form a pair of current mirror stages. The current output is coupled to a common connection of the third CMOS pair.

Abstract: A bias device that modifies the bias of a device based on an input signal to the device. The device may have a fixed bias, and the bias device can be connected in parallel with the fixed bias. The device can be an amplifier, such as a linear amplifier or a class AB amplifier. The bias device can be configured to provide maximum bias during the device's crossover time period.

Abstract: Disclosed are a power supply circuit which can cope with a multipotential level design and is suitable for generating potentials for driving a liquid crystal, and a liquid crystal device and an electronic instrument which use the power supply circuit. A first step-up circuit in the power supply circuit generates a first stepped-up potential level obtained by stepping up a power-supply level with a ground level taken as a reference. A regulator circuit generates a center potential obtained by regulating the first stepped-up potential level by referring to a reference potential level with the ground level taken as a reference. A second step-up circuit generates a second stepped-up potential level obtained by stepping up the center potential with the ground level taken as a reference.

Abstract: A differential amplifier according to the present invention comprises, in addition to a differential amplifier circuit and an output-stage amplifier circuit, a first source follower circuit for buffering a first output signal of the differential amplifier circuit, a second source follower circuit for buffering the first output signal of the differential amplifier circuit, and a source ground amplifier circuit, to a source of which an output terminal of the second source follower circuit is connected, and driven by a second output signal of the differential amplifier circuit, wherein a first-polar transistor in the output-stage amplifier circuit is driven by an output signal of the first source follower circuit, and the second-polar transistor is driven by an output signal of the source ground amplifier circuit.

Abstract: A semiconductor integrated circuit includes first and second differential amplification devices to amplify a voltage difference of input signals inputted from a positive input terminal and a negative input terminal, first and second addition devices to add an output of the first differential amplification device and the output of the second differential amplification device, an output stage control device controlled by the first and second addition devices, and output stage controlled by the output stage control device, and an output terminal connected to the output stage.

Abstract: An operational amplifier comprises: differential input stages to which differential signals can be inputted with full operating range; current source circuits coupled to determine current values of the differential input stages, phase inverter circuits which are provided between transistors of an output stage circuit and the current source circuits; a driver stage circuit and the output stage circuit. The phase inverter circuits control currents of the current source circuits depending on the output signal potential level. By using this structure, it becomes possible to realize a high slew rate throughout the full operating range.

Abstract: An output stage circuit is configured for enabling an output of an amplifier circuit to be pulled upwards and/or downwards to or beyond an upper power supply or below a lower power supply. The exemplary output stage circuit comprises a pair of output transistors configured to provide an output voltage, and a controlled resistive circuit. The controlled resistive element is configured to enhance the gain of the output stage circuit by modifying the dynamic impedance effect of the upper output transistor during pull-up operation, or the lower output transistor during pull-down operation. During normal operation, the controlled resistive element operates with low resistance, e.g., acts as a “short,” but during the pull-up or pull-down operation the controlled resistive element can be configured to add resistance to modify the dynamic impedance of the upper or lower output transistor.

Abstract: In a circuit according to the present invention, a multi-collector transistor is provided which includes first to third collectors so that, when a current does not flow from the second collector, a current from the first collector increases but a current from the third collector does not vary. When transistors of the circuit turn off because the voltage of an input signal gets out of an in-phase input voltage range, the supply of the current from the second collector comes to a stop and, hence, the current from the first collector increases. In this situation, further transistors carry out their on/off operations, thereby fixing the output of the circuit to a low level. That is, this circuit can, irrespective of poor pair compatibility between the transistors, fix the output logical level to a desired level when the voltage of an input signal gets out of an in-phase input voltage range.

Abstract: An amplifier circuit uses low threshold voltage devices for mid rail response in low voltage applications, but uses a high threshold voltage device at an output stage of the amplifier to generate an output from the amplifier.

Abstract: A differential amplifier for amplifying an input signal at a constant amplification rate regardless of fluctuation in the center voltage of the input signal. The differential amplifier includes a first differential pair operated when a complementary input signal is greater than or equal to an intermediate level between power supplies. A second differential pair is operated when the complementary input signal is less than or equal to an intermediate level of the power supplies. A current synthesizing circuit synthesizes output currents of the first and second differential pairs to generate output voltage. An output current offset circuit offsets a current corresponding to the output current of one of the differential pairs based on the complementary input signal so that the output voltage becomes the output current of one of the first and second differential pairs.

Abstract: An operational amplifier with selectable performance characteristics is provided. The operational amplifier provides a sleep mode (e.g., fully disabled) in addition to providing a number of different levels of awake operation (e.g., different performance characteristics). As such, the op-amp can allow a system to use only the power needed to obtain a required level of performance at any point in time. For example, the op-amp may be operated at a minimum power mode, an awake at mid-level power mode, or an awake at maximum power mode.

Abstract: An adjustable bipolar current source for a load, such as a thermoelectric cooler, includes a voltage-controlled power supply having a unipolar output, and an H-bridge. At least one of the two active elements on a first side and at least one of the two active elements on a second side of the H-bridge comprises an active conductive element responsive to a control signal to set a magnitude of current flow through the active conductive element. Control logic provides the control signals to the active elements on the first and second sides to set the polarity of the current to the load. Logic coupled to the voltage-controlled power supply maintains a supply voltage sufficient to maintain a voltage drop across the active conductive elements within a linear range of operation of the conductive elements. The output of the voltage-controlled power supply is clamped at or near a minimum stable level.

Abstract: A differential circuit comprises first, second, third and fourth devices that have first, second, third and fourth control terminals, respectively. The second and fourth devices are arranged in series with the first and third devices, respectively. A first output communicates with the first device and the second device. A second output communicates with the third device and the fourth device. First and second inputs communicate with the first and fourth control terminals, respectively. The first, second, third and fourth devices are the same type of devices. The third and second control terminals follow the first and fourth control terminals. When the first device pushes, the third device pulls. When the first device pulls, the third device pushes. When the fourth device pushes, the second device pulls. When the fourth device pulls, the second device pushes. The second and third devices and the first and fourth devices are matched.

Abstract: A programmable, rail-to-rail, low-voltage, micro-power harmonic-mean class-AB output stage with MOS devices employed in weak inversion is provided. The output stage MOS devices are arranged in the translinear loop, which avoids having a plurality of MOS devices in series between the power supply rails and thus enables low-voltage operation. The MOS devices in the translinear loop are used to implement the harmonic mean function x*y=z*(x+y) where x and y are mirrored to the output and represent the quiescent push and pull currents, respectively. Circuit operational parameters may be varied to suit a variety of different applications. Increasing the supply voltage for given quiescent current will advantageously increase the maximum current load. Increasing the quiescent current for given supply voltage will advantageously lower the distortion of the output stage.

Abstract: A voltage feedback (“VF”) operational amplifier (“op-amp”) that includes a circuit operable to dynamically bias pre-driver transistors at the op amp output stage. This arrangement provides a dynamic bias from a common base gain stage (302) to the pre-drivers (338, 339) of the output stage (303) so that higher slew rate is achieved with minimal discontinuity in the signal.

Abstract: A driver circuit of an image display apparatus comprises driver circuit with a class A/B push-pull stage (T3, T5). The driver circuit contains an n-type pull transistor (T3), an n-type control transistor (T2) with a main current channel terminal coupled to a control electrode of the pull transistor (T2) and a voltage source (V) applying a predetermined voltage over a series connection of the control electrode-main current channel terminals of the control transistor (T2) and the pull transistor (T3). The current from the control transistor (T2) flows to a p-type push transistor (T5) via a current mirror (T4, T5). An input transistor (T1) draws all of the current from the control transistor (T2) via a node (142) between the control transistor (T2) and the pull transistor (T3) to control the ratio between the currents through these transistors (T2, T3).

Abstract: An operational amplifier comprises: differential input stages to which differential signals can be inputted with full operating range; current source circuits coupled to determine current values of the differential input stages, phase inverter circuits which are provided between transistors of an output stage circuit and the current source circuits; a driver stage circuit and the output stage circuit. The phase inverter circuits control currents of the current source circuits depending on the output signal potential level. By using this structure, it becomes possible to realize a high slew rate throughout the full operating range.

Abstract: An output stage for a Class-G amplifier includes four current mirrors, (CmpL) powered by a first low voltage supply (VspL), (Cmph) powered by a first high voltage supply (Vsph), (CmmL ) powered by a second low voltage supply (VsmL), and (Cmmh) powered by a second high voltage supply (Vsmh). The outputs of the current mirrors are connected together to form an output of the output stage. A buffer (10), whose input forms an input to the output stage, includes a first transistor (19) and a second transistor (27) connected in an emitter follower configuration, which are used to steer the buffer's output either through the first transistor (19) to a first switch (69) or through the second transistor (27) to a second switch (84). The first switch (69), which is controlled by a first comparator (68) connects a collector of the first transistor (19) to either the input to the first current mirror (CmpL) or the input to said second current mirror (Cmph).

Abstract: The circuit with adaptive amplifier output common mode voltage adjustment includes: a differential pre-amplifier; a re-generated comparator having a differential input coupled to a differential output of the pre-amplifier; and a replica comparator coupled to a common mode node of the pre-amplifier for adjusting a common mode of the pre-amplifier. The replica comparator provides a trip-point reference to set the output common mode of the pre-amplifier. This sets the output common mode of the pre-amplifier to the most sensitive region of the re-generated comparator.

Abstract: The present invention is provided with a first, a second and a third differential amplifier which operate at a source voltage with respect to a reference voltage or a voltage between these; an output stage having a first and a second transistor driven complimentarily; a first resistor connected to an input terminal; a second resistor connected to an output of the first differential amplifier circuit; and a first and a second feed back resistor connected to an output terminal of the output stage circuit.

Abstract: This disclosure is generally concerned with devices for determining photocurrent levels. One example of such a device is an optoelectronic device that includes a photodetector. The photodetector is configured to receive an optical signal and generate a corresponding electrical signal. The electrical signal is received by a pre-amplifier circuit which then converts the received electrical signal to a differential output. Finally, a post-amplifier circuit in communication with the first stage circuit is configured to derive an optical signal strength of the optical signal based upon the differential output received from the pre-amplifier circuit.

Abstract: A self-biasing differential buffer generates a self-bias voltage from its inputs. A first amplifier receives a first input signal on gates of four transistors—p and n-channel drive transistors in a drive branch and p and n-channel bias-generating transistors in a bias-generating branch. Current source and current sink transistors source and sink current to both branches. The drains of the drive transistors drive a differential output, while the drains of the bias-generating transistors drive through a transmission gate to a self-bias node. The second amplifier receives the second input signal and has the same structure, with one branch driving the self-bias voltage through another transmission gate, and another branch driving a complementary differential output. The bias-generating branches use smaller transistors so that only a small current is used to generate the self-bias voltage. The self-bias node is fed to the gates of current source and sink transistors.

Abstract: In an operational amplifier, a differential amplifying circuit is configured to amplify an input voltage inputted from the input terminal. An outputting transistor is connected to the output terminal. A driving transistor is connected to the differential amplifying circuit and the outputting transistor. The driving transistor turns on according to a control signal supplied from the differential amplifying circuit to the driving circuit. The driving transistor is also configured to drive the outputting transistor according to the control signal. A control signal reducing circuit, when a voltage is applied on the driving transistor through the outputting transistor, is configured to reduce the control signal within a range that the driving transistor is kept to on state. The voltage applied on the driving transistor exceeds a predetermined threshold voltage.

Abstract: In an operational amplifying circuit, the first transistor is configured to turn on and off according to an output signal outputted from the operational amplifier through the output terminal thereof. The second transistor is connected to the first transistor in series and configured to turn off and on reversely with the on and off operation of the first transistor on the output signal from the operational amplifier. The current control unit is electrically connected to the first and second transistors and configured to detect a current flowing in one of the first and second transistors. The current control circuit is configured to cause a current to flow into the control terminal of the one of the first and second transistors and to make other of the first and second transistors turn off.

Abstract: An operational amplifier that decreases idling current, widens a voltage output range, and increases load driving capacity. The operational amplifier includes a first output transistor connected to a high potential power supply. A second output transistor is connected between the first output transistor and a low potential power supply. The first and second output transistors generate an output signal at a node between the first output transistor and the second output transistor. An idling current control circuit controls the collector current of the first output transistor in accordance with the base voltage of the second output transistor to control the idling current of the first and second output transistors.

Abstract: The present invention relates to an amplifying circuit that can change load drivability responding to load conditions, and reduce power consumption. The amplifying circuit according to the present invention comprises an amplifying means that amplifies input signals a first time to generate a first and a second amplified signals through a first and a second transistors, and further amplifies the first and second amplified signals once again through a third and a fourth transistors, for final outputs; a detecting means for detecting the first and second amplified signals from the amplifying means and generating a first and a second detection signals; and a load drivability control means that is controlled by the first and second detection signals from the detecting means to change load drivability of the amplifying means.

Abstract: A circuit is used in the output stage of an operational amplifier which allows a rail to rail swing of the output voltage while consuming low quiescent power. The circuit includes first and second control elements each having a controllable path and a control node. The circuit further includes a third control element having a controllable path connected between the control nodes of the first and second control elements via a resistive path. A voltage indicative of an input signal is applied to a node of the resistive path. Current flow through the controllable paths of the first and second control elements changes in response to changes in the voltage at the node. More specifically, current flow through the controllable path of the second control element changes in dependance on the current flow through the controllable path of the third control element. Additionally, as one of the first and second control elements is turned on, the other control element is held off.

Abstract: An operational amplifier including a differential input section generating a first signal as a differential voltage between two input signals; an amplifying section amplifying the first signal into second and third complementary signals; a first MOS transistor between a first supply voltage and an output node, a conduction state of the first MOS transistor controlled responsive to the second signal; a second MOS transistor between a second supply voltage and the output node, a conduction state of the second MOS transistor controlled responsive to the third signal; and a step-up section stepping up the first and second supply voltages to generate a step-up voltage higher than the first and second supply voltages, the amplifying section driven by the step-up voltage so that an absolute value of the maximum level of the second or third signal becomes larger than the absolute value of the first or second supply voltage.

Abstract: A transmission channel for a subscriber line interface circuit comprises a front end, tip/ring current-sensing transimpedance stage, containing relatively low valued tip and ring sense resistors coupled in circuit with tip and ring paths of a telecommunication wireline pair. The front end transimpedance stage transforms differential tip and ring input currents sensed by the tip and ring sense resistors into a single ended voltage, which is coupled to a transconductance amplifier filter/gain stage. The filter/gain stage is configured to provide a programmable output impedance, and converts the voltage from the current-sensing transimpedance stage into an output transmission voltage for application to a selected one of a current-sense, voltage-feed, or voltage-sense, voltage-feed telecommunication circuit.

Abstract: A system and method for implementing an amplifier capable of limiting or clamping an amplifier output signal is described. A clamp buffer and an input buffer cooperate to bias an output circuit according to the relative level of a clamp signal and an input signal. In a normal mode, in which the input signal has a first relationship with the clamp signal, the output circuit provides an output signal based on the input signal. In a clamping mode, in which the input signal has a second relationship with the clamp signal, the output circuit provides an output signal based on the clamp signal, which can be substantially fixed. The clamp signal can be set by the user to establish a desired clamping range.

Abstract: A class-A amplifier circuit having output voltage varied according to input voltage includes a class-A amplifier, a voltage pull-up switch level circuit, an output voltage of the class-A amplifier, a voltage pull-up switch circuit, a voltage pull-down switch level circuit, a voltage pull-down circuit, a voltage pull-down switch circuit, and a bias circuit. The circuit utilizes the voltage pull-up and the voltage pull-down circuits to enable an output voltage of the class-A amplifier to rapidly and precisely change as an input voltage changes. Moreover, the circuit utilizes the voltage pull-up and the voltage pull-down switch circuits to prevent an overshooting from occurring.

Abstract: A high output current negative feedback power amplifier amplifies an input signal by use of a monolithic operated amplifier with a current limiting resistor in its output path. The output current of the amplifier is automatically increased when the voltage drop across the current limiting resistor increases beyond a predetermined point and global current limiting automatically occurs when the output current of the monolithic amplifier exceeds a predetermined point.

Abstract: A circuit arrangement prevents clipping of pulse metering (teletax) signals in a telephone line card channel that results from the differential impedance between a subscriber line interface circuit (SLIC) and the line at the frequency band of teletax signals. The circuit arrangement is configured to sense pulse metering signals through a delay circuit, which is coupled to a reflected signal cancellation circuit. The reflected signal cancellation circuit contains a transconductance amplifier circuit that generates a pair of complementary polarity output currents representative of the sensed teletax signal. One of these output currents is fed back to a programmed impedance element in the transmission channel path of the SLIC so as to effectively cancel the reflected teletax signal.

Abstract: Bias current in output transistors of a class AB output stage is controlled by providing equal amplification to both an output of an input stage (2) of an amplifier and an output (17,18) of a class AB control circuit (46). A split input transistor circuit structure for a first side of the differential input stage (2) includes first (15) and second (16) input transistors with gates coupled to a first input (Vin+). A third input transistor (10) of the input stage has a gate coupled to a second input (Vin−). A split folded common gate cascode circuit includes first (25) and second (30) cascode transistors having their drains coupled to gates of the output transistors, respectively, and a third cascode transistor has a source coupled to a drain of the third input transistor.

Abstract: An operational amplifier for increasing the response speed of its output voltage relative to an input signal while increasing the tolerable amplitude of the output voltage. The operational amplifier includes a PNP output transistor connected to a high potential power supply, an NPN output transistor connected between the PNP output transistor and a low potential power supply, and a drive unit, which drives each output transistor in accordance with an input current. The drive unit includes a current source, a first current mirror circuit, and a second mirror circuit. The input current is supplied to a node between the first and second current mirror circuits. The base of the NPN output transistor is connected to the node, and the base of the PNP output transistor is connected to a further node between the current source and the first current mirror circuit.

Abstract: An integrated circuit includes an analog amplifier connected to a terminal pad and has a Miller compensation of a section of the analog amplifier. The Miller compensation circuit is connected to a terminal for reference-ground potential through a capacitive element. An EMC interference radiation that can be coupled in through the terminal pad is attenuated by the capacitive element. The operating points of the internal nodes of the analog amplifier are, thereby, stabilized.

Abstract: An operational amplifier includes: a differential input section for generating a first signal corresponding to a differential voltage between two input signals; an amplifying section for amplifying the first signal in voltage to generate second and third complementary signals; a first MOS transistor connected between a first supply voltage and an output node, a conduction state of the first MOS transistor being controlled in accordance with the second signal; a second MOS transistor connected between a second supply voltage and the output node, a conduction state of the second MOS transistor being controlled in accordance with the third signal; and a step-up section for stepping up the first and second supply voltages to generate a step-up voltage higher than the first and second supply voltages; wherein the amplifying section is driven by the step-up voltage so that absolute value of the maximum level of the second or third signal becomes larger than the absolute value of the first or second supply voltage.

Abstract: An output stage for a differential amplifier is presented. If the differential amplifier is a matched current differential amplifier where the non-inverted and inverted differentials have the same current, the output stages of the present invention may provide optimum gain to the differentials in a single output voltage.

Abstract: According to the invention, the high-frequency power amplifier is characterised in that the power transistor is switched in such a way that said transistor is operated in the breakdown region and that a control loop is provided. Charge carriers that are produced is the breakdown region are carried away from an output of the operational amplifier by means of said control loop.

Abstract: An apparatus for indicating a difference between a first voltage and a second voltage includes: (a) an input unit for receiving the first voltage at a first locus and receiving the second voltage at a second locus; the input unit quanitifying the difference; (b) an output unit coupled with the input unit and cooperating with the input unit to generate an output signal for effecting the indicating; and (c) a signal treating unit coupled with the output unit, the first locus and the second locus, and employing at least one algorithmic relation with at least one of the first voltage and the second voltage to generate at least one bias current for effecting a substantially balanced response by said output section in said generating said output signal as said difference varies. The at least one drive current has nonnegative values as the difference ranges in value.

Abstract: An operational amplifier is configured for low voltage operation and better compliance. An exemplary operational amplifier comprises a folded-cascode amplifier with a class-AB biased output stage configured for low voltage operation. The exemplary output stage includes a class-AB control loop being controlled for the upper output device, and with the complementary, lower output device being driven through an additional gain configuration to allow for the necessary compliance voltage. In addition, the lower output device can be configured to operate with a low gate-source voltage.

Abstract: A power amplifier that utilizes a minimum amount of power, and, simultaneously, inhibits the generation of distortion is described. The power amplifier includes a differential input terminal, an output terminal, a negative feedback circuit, and an adaptive bias current control circuit. The differential input terminal receives a first voltage and a second voltage respectively through a first terminal and a second terminal, and outputs a current corresponding to a difference in the input voltages. The output terminal outputs an amplified signal corresponding to the current output by the differential input terminal. The negative feedback circuit performs negative feedback of an output voltage of the output terminal and provides the output voltage to the first terminal of the differential input terminal. The adaptive bias current control circuit controls a bias current of the output terminal according to distortion information corresponding to the difference between the first voltage and the second voltage.

Abstract: A Complementary CMOS differential amplifier has automatic operating point adjustment (self-biasing) and the properties of a rail-to-rail amplifier. The CMOS differential amplifier uses folded cascodes and is considerably faster in operation than previous CMOS differential amplifiers, since it comprises a circuit element that ensures that, during the operation of the CMOS differential amplifier, all MOS FETs of the cascodes operate in their saturation range (that is not in their resistive range). The CMOS differential amplifier may be used in an input stage, a signal distribution circuit and a clock pulse distribution circuit.