Abstract: A circuit includes an input stage configured to receive and amplify an input signal to produce an amplified signal, where the input signal is referenced to a higher voltage and is associated with a common mode voltage. The circuit also includes level shifter resistors configured to level shift the amplified signal to produce a shifted signal. The level shifter resistors are configured to provide a voltage drop so that the shifted signal is referenced to a lower voltage. The input stage may include multiple transistors floating in one or more isolated portions of a substrate, where the transistors perform amplification in the input stage. The circuit may also include circuitry configured to control current through the level shifter resistors so that the voltage drop depends on the common mode voltage of the input signal. In addition, the lower voltage may be between supply rails of the circuit.

Abstract: A continuous time common mode feedback module is capable of operating in a wide range of input voltages. The common mode feedback module includes a common mode detector and an amplifier for computing and amplifying the difference of a reference voltage and a common mode voltage of a first input signal and a second input signal. The common-mode feedback module includes a common mode resolver and a control voltage generating module coupled to each other to provide a common mode feedback voltage. The common mode feedback module provides a good linearity and a wide bandwidth, without compensation requirements. The common mode feedback module also provides small process corner dependence of bias current and a common mode offset.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for the direct duty cycle calibration of a receiver clock. In some embodiments, an integrated circuit includes a receive (RX) data path, a RX clock path, and a control path. In some embodiments, the control path uses RX latches, a majority detector, and digital duty cycle control logic to calibrate the duty cycle of the clock signal. Other embodiments are described and claimed.

Abstract: There is provided an active balun circuit including: a load circuit unit including a first and a second load; a differential amplifying unit including a first amplifying unit connected to the first load, and a second amplifying unit connected to the second load and forming a differential amplifying unit together with the first amplifying unit, the differential amplifying unit differentially amplifying an input signal, and outputting first and second output signals out-of-phase with each other through first and second output terminals, respectively; a current source connected between a ground and a common connection node of the first and second amplifying units, and maintaining a constant amount of current flowing through the differential amplifying unit; and a compensation amplifying unit amplifying the input signal supplied through the input terminal, transmitting the amplified input signal to the second amplifying unit, and rejecting common mode noise of the differential amplifying unit.

Abstract: An apparatus and method for generating differential signals. The apparatus includes a first operational amplifier receiving a first signal, a second operational amplifier receiving a second signal, and a first transistor. The first transistor includes a first gate, a first terminal, and a second terminal. Additionally, the apparatus includes a second transistor. The second transistor includes a second gate, a third terminal, and a fourth terminal. Moreover, the apparatus includes a first resistor coupled to the first terminal and the third terminal, and a second resistor coupled to the second terminal and the fourth terminal. Also, the apparatus includes a first current supplier coupled to the first terminal, a second current supplier coupled to the second terminal, a third current supplier coupled to the third terminal, and a fourth current supplier coupled to the fourth terminal.

Abstract: Embodiments of the present invention provide a low voltage continuous time common mode feedback (CMFB) module, for low voltage operational amplifiers, providing good linearity, wide bandwidth and low systematic offset. The common mode feedback module includes a controlling module and an initializing module. The controlling module and the initializing module are parallel common mode feedback loops. The controlling module is a main CMFB loop and the initializing module is an auxiliary CMFB loop and both the loops work simultaneously. The controlling module and the initializing module receive a first differential input voltage and a second differential input voltage supplied by differential outputs of a main differential amplifier. Both the CMFB loops are low gain amplifiers in order to provide operation as linear as possible over the entire differential output operating range of the main differential amplifier.

Abstract: In a method and apparatus for trimming values of load resistors to reduce variations there between, a common mode feedback loop (CMFBL) included in a differential amplifier is switched from operating in a closed loop mode to operate in an open loop mode. The CMFBL includes an operational amplifier (OA) generating an output signal. A selector switch, coupled to receive the output signal, is operable to switch a path of the output signal in response to a CAL signal. In the closed loop mode, the selector switch routes the output signal to a feedback loop to provide a regulated current to the load resistors. In the open loop mode, the OA operates as a comparator and the output signal is provided as a digital signal. The selector switch provides the digital signal to a controller to digitally trim the values of the load resistors.

Abstract: Disclosed is a differential amplifier including: first and second transistors each having a first gate, a second gate, a source, and a drain open to a drain side, the first gate and the second gate being controlled independently, a differential input being supplied to between the first gates of the first and second transistors, and the sources of the first and second transistors being connected in common to a first reference potential; first and second load circuits each connected to each of drain sides of the first and second transistors; a detection circuit detecting a common-mode voltage between ones of drain sides of the first and second transistors; and a comparison and amplification circuit amplifying the common-mode voltage in comparison with a second reference potential and supplying an output signal thereof to both of the second gates of the first and second transistors.

Abstract: A fully differential amplifier includes: an N-stage amplifier including first to Nth amplifier stages, where N is a positive integer greater than or equal to 2, the first to Nth amplifier stages being cascaded in sequence so as to generate a pair of differential output voltages; a common mode feedback circuit coupled to the N-stage amplifier, detecting a common mode level of the differential output voltages, and controlling the first amplifier stage according to the common mode level detected thereby; and a common mode frequency compensation circuit including a pair of capacitors, each having a first terminal coupled to the N-stage amplifier to receive a respective one of the differential output voltages, and a second terminal coupled to a common mode node of the first to (N-1)th amplifier stages of the N-stage amplifier.

Abstract: An operational amplifier is provided with an extended common mode input range. This operational amplifier includes an input stage, a common mode feedback circuit, a current mirror, a replica input stage, and an output stage. The input stage couples to the CMFB circuit and replica input stage. The input stage is operable to receive a feedback signal from the CMBF circuit. This feedback signal is based on comparing a common mode voltage to a common mode reference voltage. The current mirror, coupled to the CMFB circuit and input stage, mirrors currents within the input stage as input to the CMFB circuit. The replica input stage, which is also coupled to the CMFB circuit, uses an input common mode (INCM) voltage to adjust current flow within the replica input stage. This allows a current within the CMFB circuit to be a function of the INCM. The output stage couples to the input stage and is operable to provide an amplified signal corresponding to a first differential signal.

Abstract: A transmitter provides fast settling times, slew rate control, and power efficiency while reducing the need for large external capacitors. The transmitter typically includes a pre-driver, driver, and replica circuit. The pre-driver can shift the voltage level of an input signal to produce a shifted signal. The pre-driver can shift the voltage level in response to a selectable load resistance circuit and a voltage regulation feedback signal. The driver receives the shifted signal and generates a driver output signal in response to the received shifted signal. The replica circuit can be a scaled replica of the pre-driver and the driver using scaled components from the pre-driver and driver circuits. The scaled components can be used to generate the voltage regulation feedback signal. The generated voltage regulation feedback signal represents, for example, whether the output voltage of the driver output is above a reference voltage.

Abstract: A multistage RF amplifier amplifies RF signals used for communication in a WLAN communications system. The multistage RF amplifier comprises a first amplifier circuit coupled to a second amplifier circuit to maximize amplification. A common mode of the first amplifier circuit is coupled to a common mode of the second amplifier circuit to provide a voltage offset. The voltage offset counters voltage changes due to oscillations in the first amplifier circuit, thereby reducing interference from the multistage RF amplifier.

Abstract: A receiver has a first input port and a second input port both coupled to a differential amplifier through first and second input capacitors. A bias circuit coupled to the core side of the first input capacitor and to the core side of the second input capacitor is configured to provide a selected voltage to at least one of the first input and the second input of the differential amplifier. In one embodiment, a common mode bias circuit provides a common mode voltage to both inputs of a differential amplifier. In a particular embodiment, a run length detector monitors the output of the differential amplifier and provides a run length feedback signal or an average bit density feedback signal to the set the selected voltage between periods of data reception.

Abstract: A fully-differential amplifier able to operate at a low power supply voltage and provided with a common-mode signal suppression function is disclosed. This fully-differential amplifier is provided with a first fully-differential amplifier configured by a single-stage configuration inverting amplifier and canceling out the common-mode signal of the input side by a feedforward means and a second fully-differential amplifier configured by a single-stage configuration inverting amplifier and canceling out the common-mode signal of the output side by a feedback means, the output of the first fully-differential amplifier being connected to the input of the second fully-differential amplifier.

Abstract: In a method and apparatus for trimming values of load resistors to reduce variations there between, a common mode feedback loop (CMFBL) included in a differential amplifier is switched from operating in a closed loop mode to operate in an open loop mode. The CMFBL includes an operational amplifier (OA) generating an output signal. A selector switch, coupled to receive the output signal, is operable to switch a path of the output signal in response to a CAL signal. In the closed loop mode, the selector switch routes the output signal to a feedback loop to provide a regulated current to the load resistors. In the open loop mode, the OA operates as a comparator and the output signal is provided as a digital signal. The selector switch provides the digital signal to a controller to digitally trim the values of the load resistors.

Abstract: A multi-mode amplifier arrangement comprises an amplifier having a plurality of field effect transistors selectable in response to a control signal at a control terminal, said plurality of field effect transistors coupled to an input terminal to receive a signal to be amplified, said amplifier arranged between a supply terminal and a ground terminal. A tunable current source is coupled to the amplifier to provide in operation of the amplifier a constant drain current through the plurality of field effect transistors.

Abstract: An operational amplifier with a rail-to-rail common-mode input and output range comprises a differential input stage consisting of a first differential pair and a second differential pair for receiving an input signal; a summing circuit coupled to the differential input stage for outputting a summation result of the output signals of the first differential pair and second differential pair; and a push-pull output stage coupled to the summing circuit for outputting an amplified signal comprising an output terminal for outputting the amplified signal, a source coupled transistors for generating a control voltage according to output current of the summing circuit, and a first output transistor and a second output transistor for controlling current of the first output transistor and the second output transistor according to the control voltage of the source coupled transistor.

Abstract: This disclosure relates to a common mode regulation in multi stage differential amplifiers.

Abstract: A pre-amplifier for a receiver including first and second input operational amplifiers; an output module; and first and second feedforward circuits are provided. The input operational amplifiers amplify an input differential voltage pair to output a first and a second differential voltage pairs. The output module includes first and second output operational amplifiers and an inverter. The output operational amplifiers amplify the differential voltage pairs to output first and second output amplified voltages. The inverter pulls an output voltage high or low based on output amplified voltages. The first and second feedforward circuits are respectively for pulling up the first differential voltage pair or pulling down the second differential voltage pair, such that the first and the second output operational amplifiers are not disabled.

Abstract: A differential amplifier includes a differential input pair (2A) coupled to a folded cascode stage (2B) and a common mode feedback circuit (34) including a tracking circuit (30A) coupled to first (Vout?) and second (Vout+) outputs of the folded cascode stage (2B). The first and second outputs are coupled to first terminals of first (31A) and second (31B) tracking capacitors which have second terminals on which a first common mode output signal (VCM1) is produced and also are coupled to first terminals of third (32A) and fourth (32B) tracking capacitors, respectively, which have second terminals on which a second common mode output signal (VCM2) is produced. The first and third tracking capacitors are discharged by first (27A) and second (27B) switches that directly couple the first and second outputs to first and second inputs of a common mode feedback amplifier (4). A desired common mode output voltage (VCM-IN) is applied to a third input of the common mode feedback amplifier.

Abstract: A low noise, low power differential two-stage amplifier includes a first stage comprising a pair of electrical devices that sense an input signal difference across the pair of electrical devices; and a control feedback loop operatively connected to the first stage, wherein the first stage in combination with the control loop feedback is adapted to place an exact copy of the signal across a first pair of resistive components, wherein the first pair of resistive components are adapted to generate a differential signal current, wherein the control feedback loop is adapted to ensure that the differential signal current goes a second pair of resistive components to generate a voltage output. Preferably, the first and second pair of resistive components are in ratio to produce the exact copy of the signal with some gain at an output of the first stage.

Abstract: A differential current amplifier circuit includes a first circuit generating a first pair of output currents based on a first input current to the differential current amplifier circuit. A second circuit generates a second pair of output currents based on a second input current to the differential current amplifier circuit. A first subtraction circuit generates a first output voltage based on a difference between one of the first pair of output currents and one of the second pair of output currents. A second subtraction circuit generates a second output voltage based on a difference between the other one of the second pair of output currents and the other one of the first pair of output currents.

Abstract: In a feedback amplifier circuit, a first switching device executes an auto-zero operation by inputting a signal outputted from an amplifier to an input terminal of the amplifier during an auto-zero operation interval prior to an amplification interval. A first capacitor accumulates and holds an offset voltage at the output terminal of the amplifier during the auto-zero operation interval, and cancels an offset voltage at the input terminal of the amplifier by an accumulated and held offset voltage during an amplification interval subsequent to the auto-zero operation interval. A second switching device grounds the feedback point of the feedback circuit during the auto-zero operation interval. A second capacitor blocks a DC voltage, and accumulates and holds an offset voltage at an output terminal of the amplifier, and cancels an offset voltage at an input terminal of the amplifier by the accumulated and held offset voltage during an amplification interval.

Abstract: A differential operation circuit that uses the differential input signals to generate a reference voltage that fluctuates with the common mode voltage of the differential input signals. The reference voltage includes a common mode component that generally follows the common mode voltage of the differential input signals. The common mode component of the reference voltage is used to fully or almost fully offset the common mode voltage of the differential input signals, thereby increasing the differential operation circuit's common mode rejection characteristics.

Abstract: A multistage RF amplifier amplifies RF signals used for communication in a WLAN communications system. The multistage RF amplifier comprises a first amplifier circuit coupled to a second amplifier circuit to maximize amplification. A common mode of the first amplifier circuit is coupled to a common mode of the second amplifier circuit to provide a voltage offset. The voltage offset counters voltage changes due to oscillations in the first amplifier circuit, thereby reducing interference from the multistage RF amplifier.

Abstract: A fully differential amplifier includes a first single-ended current mirror type fully differential amplifier outputting a first output signal by two stage amplifying a difference between a first input signal and a second input signal and a second single-ended current mirror type fully differential amplifier outputting a second output signal by two stage amplifying a difference between the first input signal and the second input signal. A first tail of the first single-ended current mirror type fully differential amplifier and a second tail of the second single-ended current mirror type fully differential amplifier are connected to each other and the first output signal and the second output signal are differential signals.

Abstract: A preamplifier used in a receiver is provided. The preamplifier comprises an input circuit and an output circuit. The input circuit receives an input differential voltage pair, pulls it down when the common voltage of the input differential voltage pair is higher than a reference voltage. The output circuit receives the input differential voltage pair outputted from the input circuit to pull high or low an output voltage accordingly.

Abstract: A differential audio amplification apparatus with common mode rejection is shown, having a first input current path (401) and a second input current path (402) with a shunting input resistance (400) therebetween. The apparatus also has a first output current path (403) and a second output current path (404) with a shunting output resistance (405) therebetween. Differential amplifiers (412, 413) are provided with feedback connecting the input paths with the output paths and providing an output signal. The output shunting resistance (405) is controlled to provide gain control while maintaining common mode rejection.

Abstract: Apparatuses, circuits, and methods to amplify signals with reduced jitter are disclosed. Embodiments generally comprise amplifiers coupled with apparatuses that adjust peak frequencies of the amplifiers to reduce jitter. In many system and apparatus embodiments, the frequency gain boosters receive one or more feedback signals derived from input signals applied to the amplifiers. The frequency gain boosters generally respond to the feedback signals by manipulating or controlling active loads coupled to the amplifiers. In controlling the active loads, the frequency gain boosters generally cause the active loads to peak at frequencies at or near the input signals, the result being attenuated jitter in an output signal of the amplifier.

Abstract: A preamplifier used in a receiver is provided. The preamplifier comprises an input circuit and an output circuit. The input circuit receives an input differential voltage pair, pulls it down when the common voltage of the input differential voltage pair is higher than a reference voltage. The output circuit receives the input differential voltage pair outputted from the input circuit to pull high or low an output voltage accordingly.

Abstract: Consistent with the present invention, there is provided a circuit for extracting a common mode voltage of an input signal. The device may include an operational amplifier having an output, at least one negative input and at least one positive input, a first transistor, and a second transistor. A terminal of the first transistor may be coupled to the output of the operational amplifier. A terminal of the second transistor may be coupled to a terminal of the first transistor and the at least one positive input of the operational amplifier to create a negative feedback loop. The device may further include a common mode output, wherein the negative feedback loop extracts the common mode voltage of the input signal, the common mode voltage of the input signal being output at the common mode output. The device consistent with the present invention may provide the common mode voltage of the input signal without using any resistors, and while only occupying a small die area.

Abstract: A common mode rejection calibration scheme for use with a difference amplifier having an associated signal path. A signal is generated which varies with the common mode voltage of the differential input voltage applied to the amplifier. This signal is scaled and coupled into the signal path such that the scaled signal reduces the common-mode error that would otherwise be present in the difference amplifier's output.

Abstract: A common-mode feedback circuit is provided. An amplifier with a common-mode feedback circuit is compensated by adding a compensating unit so that the amplifier totally has two poles and one zero in its frequency response. Accordingly, the gain of the amplifier is not sacrificed, and both the stability and the phase margin of the circuit are improved.

Abstract: A structure and related design structure for providing a common mode feedback to a differential amplifier are disclosed. A common mode feedback amplifier is connected to a differential amplifier to provide common mode feedback voltage thereto. An input of the common mode feedback amplifier is shorted to an output terminal of the differential amplifier during a sampling phase, and is coupled to the differential output voltage through two matched capacitors during a holding phase.

Abstract: An improved amplifier circuit is provided herein with a gain stage and a bias stage, which may be switchably connected to the gain stage during power-up operations. The bias stage reduces a power-up time associated with the gain stage, while minimizing current consumption in the next amplifier stage and improving battery life. For example, during power-up, the bias stage may enable the output voltage of the gain stage to gradually rise from a ground potential to a desired common mode level in a highly controlled and predictable manner. By preventing “glitches” in the output voltage, the bias stage eliminates the need for inserting switches in the signal path between the output nodes of the gain stage and input nodes of the next amplifier stage.

Abstract: Various systems and methods for signal amplification are disclosed. For example, some embodiments of the present invention provide differential amplifiers that include dual transconductance characteristics. Such amplifiers include two dual input operational amplifiers that each include two input sets. A first of the input sets exhibits a first transconductance and a second of the input sets exhibits a second transconductance. The two dual input operational amplifiers are configured such that to a common mode signal, the amplifier exhibits an overall transconductance that is the difference between the first transconductance and the second transconductance. In contrast, to a differential signal, the overall transconductance is the sum of the first transconductance and the second transconductance.

Abstract: An amplifier topology includes an input stage comprising a differential pair which conducts respective output currents in response to a differential input signal. Bias current sources provide the pair's tail current and respective bias currents for the input stage in response to a drive voltage. After flowing through the input stage, most or all of the input stage bias currents are summed at a summing node, the summed currents being a current Isum. The input stage also has a feedback loop which includes a bias generator circuit arranged to receive Isum, and to provide the drive voltage to the bias current sources such that Isum is maintained approximately constant. By so doing, the output impedance of the bias current sources is effectively increased, which serves to improve the amplifier's CMR and PSR characteristics.

Abstract: Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One such input buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition of a signal applied to the second input terminal in the opposite direction. The aforementioned input buffer includes two amplifier circuits structured to be complementary with respect to each other. Each of the amplifier circuits includes a first transistor having a first input node that receives an input signal transitioning across a range of high and low voltage levels, and a second transistor having a second input node that receives a reference signal.

Abstract: An operational amplifier circuit includes an input differential circuit and a trim circuit for sensing the operational amplifier's input common mode voltage and generating an offset correction voltage in response thereto. The trim circuit reduces the amplifier's offset voltage dependence on input common mode voltage, and hence improves the common mode rejection ratio of the operational amplifier circuit.

Abstract: Various systems and methods for common mode detection are disclosed. As one example, a common mode detection circuit including a differential input stage, a common mode replica stage, and an amplifier is disclosed. The differential input stage exhibits an input common mode, and includes two differential inputs. A signal from the differential input stage representing the input common mode is electrically coupled to an input of the amplifier. Another input of the amplifier is electrically coupled to the common mode replica stage, and the amplifier outputs a signal indicative of the input common mode.

Abstract: A fully differential amplifier with a high common mode rejection ratio with an independent output voltage setting is disclosed. The amplifier may be arranged with a single ended output or a differential output. The gain may be set by adjusting a resistor without affecting bandwidth of the circuit. The circuit exhibits high speed and may be implemented with various electronic component types. The DC voltage of the output, single ended or differential, may be adjusted by adjusting a reference voltage, wherein the output voltage adjustment does not substantially affect the performance of the differential amplifier.

Abstract: A differential amplifier with a rail-to-rail input stage includes a feedback circuit that maintains the output common mode voltage of the amplifier within a narrow range of an externally supplied value. To reduce harmonic distortions and to further stabilize the output common mode voltage of the amplifier, current is controllably drawn from a biasing circuit coupled to an intermediate stage of the amplifier. Optionally, to reduce harmonic distortions and to further stabilize the output common mode voltage of the amplifier, current is controllably supplied to the intermediate stage of the amplifier.

Abstract: To eliminate common-mode components in differential input signals without the necessity of introducing a transformer and a special feedback loop for eliminating common-mode components, a differential amplifier (1) comprises a first input stage (11) for receiving differential input signals comprising common-mode signals and for outputting first differential intermediate signals, a second input stage (12) for inverting the common-mode signals and for combining inverted common-mode signals and the first differential intermediate signals into second differential intermediate signals, and an output stage (13) for receiving the second differential intermediate signals and for outputting differential output signals.

Abstract: A low power, low noise amplifier system includes at least one amplifier having first and second differential input terminals, first and second differential output terminals and providing a differential output; first and second input capacitors interconnected with the first and second differential amplifier input terminals; first and second feedback circuits containing first and second feedback capacitors, respectively, interconnected with the amplifier differential input and output terminals; an input chopper switch circuit for receiving a low frequency differential input and selectively, alternately swapping those low frequency differential inputs through the input capacitors to the differential input terminals of the amplifier; an output chopper switch for receiving and selectively, alternately swapping the amplifier differential outputs synchronously with the input chopper switch circuit; and a low pass filter responsive to the swapped differential outputs for providing a low noise, low power amplification

Abstract: An amplifier topology includes an input stage comprising a differential pair which conducts respective output currents in response to a differential input signal. Bias current sources provide the pair's tail current and respective bias currents for the input stage in response to a drive voltage. After flowing through the input stage, most or all of the input stage bias currents are summed at a summing node, the summed currents being a current Isum. The input stage also has a feedback loop which includes a bias generator circuit arranged to receive Isum, and to provide the drive voltage to the bias current sources such that Isum is maintained approximately constant. By so doing, the output impedance of the bias current sources is effectively increased, which serves to improve the amplifier's CMR and PSR characteristics.

Abstract: In an example embodiment, an apparatus, such as a two stage operational amplifier, comprising a first stage amplifier having an input and an output, and a second stage amplifier having an input and an output, the input of the second stage amplifier is coupled to the output of the first stage amplifier. A first bias circuit is operable to set a common mode voltage of the first amplifier. A second bias circuit is operable to set a common mode voltage of the second amplifier. A first feedback circuit is coupled to the first bias circuit and the output of the first stage. The first feedback circuit is operable to control the common mode voltage of the first stage amplifier based on the common mode voltage set by the first bias circuit and the output of the first stage amplifier.

Abstract: An auxiliary current source is provided that includes MOS transistors feeding startup auxiliary current to the input portion of an output common mode voltage generation circuit amplifying the output of a differential amplifier and generating an output common voltage, and a correction current source is provided that includes MOS transistors feeding correction current corresponding to the auxiliary current to a common mode feedback comparator. Thereby, a control loop that controls the output common voltage to a predetermined voltage even when the input of the differential amplifier is outside the dynamic range at the beginning is correctly started up, thereby stabilizing the output common voltage at a desired voltage.

Abstract: An electrical circuit comprises a plurality of amplifiers. Each of the plurality of amplifiers comprises an input circuit in communication with an input of the amplifier and a start-up circuit in communication with the input circuit. The start-up circuit is configured to generate a start-up signal to enable subsequent operation of the amplifier. An output circuit communicates with an output of the amplifier and with the input circuit and the start-up circuit. Respective inputs of a first and a second amplifier of the plurality of amplifiers are in communication with outputs of a third amplifier of the plurality of amplifiers. Outputs of the second amplifier are in communication with inputs of the third amplifier.

Abstract: A differential amplifier (10-1,2) includes an input stage (7) including first (M1) and second (M2) input transistors and first (4A) and second (4B) load devices. Sources of the first and second input transistors are connected together. Drains of the first and second input transistors are coupled by first (12) and second (13) conductors to the first and second load devices, respectively. Common mode feedback circuitry (6A) including first (M3), second (M4), and third (M5) transistors is combined with offset correction circuitry (8) including the second transistor and the third transistor. Sources of the first, second, and third transistors are coupled to a tail current source (11). Drains of the second and third transistors are coupled to the first and second conductors, respectively. A common mode voltage (VOCM) is applied to a gate of the first transistor. Offset trim voltages are applied to gates of the second and third transistors.

Abstract: Disclosed is a differential amplifier including: first and second transistors each having a first gate, a second gate, a source, and a drain open to a drain side, the first gate and the second gate being controlled independently, a differential input being supplied to between the first gates of the first and second transistors, and the sources of the first and second transistors being connected in common to a first reference potential; first and second load circuits each connected to each of drain sides of the first and second transistors; a detection circuit detecting a common-mode voltage between ones of drain sides of the first and second transistors; and a comparison and amplification circuit amplifying the common-mode voltage in comparison with a second reference potential and supplying an output signal thereof to both of the second gates of the first and second transistors.