Abstract: Apparatus and methods for electronic amplification are provided. In one embodiment, an amplifier includes a first adaptive level shifter (ALS), a second ALS, a first transconductance amplification circuit, a second transconductance amplification circuit, and a transimpedance amplification circuit. The first ALS and the second ALS are electrically coupled to the first and second transconductance amplification circuits to improve the input voltage range and common-mode rejection ratio (CMRR) of the amplifier. The transimpedance amplification block is electrically coupled to the first and second transconductance amplification blocks and generates an output voltage of the amplifier. The first ALS receives a differential input voltage, and the second ALS is configured to receive a feedback signal configured to change in relation to the output voltage signal.

Abstract: A differential amplifier circuit with common-mode feedback is disclosed.

Abstract: In one embodiment, a comparator of a Flash analog-to-digital converter (ADC) is calibrated in the background by switching the comparator to a feedback loop, determining the comparator's current reference level, and adjusting the comparator's reference level to a target reference level by charging a reference capacitor coupled the comparator.

Abstract: An amplifier circuit may include an input differential pair that includes a first transistor and a second transistor, a positive input voltage being supplied to a gate terminal of the first transistor, a negative input voltage being supplied to a gate terminal of the second transistor, a first resistor that generates a differential current corresponding to a differential voltage between the positive input voltage and the negative input voltage, an output differential pair that includes a third transistor and a fourth transistor, a negative output voltage being supplied from a drain terminal of the third terminal, a positive output voltage being supplied from a drain terminal of the fourth terminal, a second resistor that is connected to a reference voltage, the differential current generated by the first resistor being supplied to the second resistor, and a bias circuit that supplies a constant bias current to the first, second, third, and fourth transistors.

Abstract: In an embodiment are provided are a differential amplifier, a method of amplifying a differential input signal, a device including a differential amplifier, and a low voltage differential signaling receiver.

Abstract: A voltage level shifter for a direct coupling of an external voltage source to a common mode of a circuit may include an amplifier, a voltage-controlled current source, a first and second resistors. A first input of the amplifier may be connected to the common mode. A second input of the amplifier may, via the first and second resistors, receive a voltage indicative of the external voltage source. The output of the amplifier may indicate a voltage difference between the first and second inputs. The voltage-controlled current source may be controlled by the voltage difference to supply a current to a common node of the first and second resistors so that the voltage difference between the first and second inputs may be minimized.

Abstract: Embodiments of a radio frequency (RF) receiver implementing one or more forms of protection to protect devices of the RF receiver from in-band interferers is provided. The RF receiver includes an integrated circuit terminal configured to couple a RF signal received at an antenna to a RF signal path, and a low noise amplifier (LNA) coupled to the RF signal path and configured to amplify the RF signal to provide an amplified RF signal. To protect the LNA from in-band interferers, the RF receiver can further include one or more clamping circuits and/or an over-voltage detector to determine if a peak of the RF signal exceeds an acceptable level.

Abstract: A common-mode feedback circuit includes an amplifying circuit, a biasing circuit connected with the amplifying circuit, and a feedback loop connecting the amplifying circuit with the biasing circuit. The feedback loop includes a first field effect transistor M1, a eighth field effect transistor M1B connected with the first field effect transistor M1, a tenth field effect transistor M2B and an eleventh field effect transistor MFB connecting the eighth field effect transistor M1B and the tenth field effect transistor M2B. The common-mode voltage value of the common-mode feedback circuit is adjusted by the eleventh field effect transistor MFB. The common-mode feedback circuit has the simple structure and is capable of achieving the common-mode feedback without the peripheral feedback circuit and the input reference voltage.

Abstract: A variable gain amplifier (VGA) disclosed herein includes an input current connector, an output current connector, a gain adjustment connector, scaled current mirrors copying the input current, means for steering the copied currents either to the current output or to another appropriate location based on the signal present at the gain adjustment connector.

Abstract: A differential amplifier includes a pair of input transistors, a pair of load transistors, a pair of impedance devices, a pair of auxiliary input transistors, and a pair of shield transistors is provided. The input transistors provide two input terminals. The load transistors provide two output terminals and two first terminals connected to first voltage. The impedance devices are coupled between the output terminals in series. The auxiliary input transistors have two control terminals respectively connected to the input terminals, two first terminals, and two second terminals. The input transistors and the auxiliary input transistors have reverse conductive type. The shield transistors has a pair of control terminals, a pair of first terminals respectively connected to the second terminals of the auxiliary input transistors and coupled to a second voltage through a pair of current sources, and a pair of second terminals respectively connected to the output terminals.

Abstract: A variable gain amplifier device (100) with improved gain resolution is achieved. The device includes a programmable gain amplifier (PGA) (110), an analog-to-digital converter (ADC) (160), an automatic level control (ALC) algorithm means (176), and a delta-sigma modulator (180). The PGA (110) is capable to receive and to amplify an analog input signal (154) to thereby generate an analog output signal (164). The PGA (110) includes an amplifier (160) and a switchable resistor network (120). The ADC (170) is coupled to the PGA (110) and is capable to convert the analog output signal (164) to a digital signal (174). The ALC algorithm means (176) is coupled to the ADC (170) and is capable to generate a control code (178) by processing the digital signal (174). The delta-sigma modulator (186) is coupled to the ALC algorithm means (186) and is capable to generate a pulse-density modulated (PDM) signal (182) by processing the control code (178).

Abstract: An amplifier circuit is provided to be switchable between a single end output configuration and a differential output configuration without increasing a circuit area. When first and fourth switches are turned off and a second switch is turned on, a load circuit functions as an active load on a differential pair and a first output terminal is internally disconnected. The amplifier circuit is provided with a single end output configuration and differentially amplifies input voltages inputted to input terminals and outputs an imbalanced signal from a second output terminal. When the first and fourth switches are turned on and the second switch is turned off, the load circuit functions as a load on the differential pair and the first output terminal is internally connected. The amplifier circuit is provided with a differential output configuration and differentially amplifies the input voltages inputted to the input terminals and outputs balanced signals from the output terminals.

Abstract: An amplifier with a cascode device contains a common mode feedback circuit to ensure correct operating point in the amplifier. Common mode feedback is provided to the amplifier to maintain the common mode operating point during active operation. Additional common mode feedback is provided to the cascode devices to ensure correct start-up by forcing the node voltages to go to their desired voltage levels.

Abstract: A method for providing common-mode feedback is provided. A common-mode current is applied to a common-gate amplifier, and the common-mode current is sensed. In response to the sensed common-mode current, a control voltage is generated. A first feedback current (which is generated in response to the control voltage) can then be applied to differential ground of the common-gate amplifier if the common-mode current is less than a predetermined threshold. Additionally, a second feedback current (which is generated in response to the control voltage) can be applied to input terminals of the common-gate amplifier if the common-mode current is greater than the predetermined threshold.

Abstract: A receiving circuit in accordance with an exemplary aspect of the present invention includes a first voltage-dividing circuit that outputs a first input signal obtained by voltage division of one of differential signals based on the resistance ratio between first and second resistors, a second voltage-dividing circuit that outputs a second input signal obtained by voltage division of the other of the differential signals based on the resistance ratio between third and fourth resistors, a differential amplifier that amplifies the differential component between the first and second input signals, a common-mode voltage detection circuit that detects the common-mode voltage of the differential signals, and a bias voltage switching circuit that switches the voltage value of a bias voltage based on the common-mode voltage.

Abstract: Circuits that operate with power supplies of less than 1 Volt are presented. More particularly, circuits that operate with supply voltages near or lower than the threshold voltage of the transistors in those circuits are presented. Various circuits embodiments such as operational transconductance amplifiers (1101, 1102, 1103), biasing circuits, integrators (1113, 1123, 1133), continuous-time sigma delta modulators, track-and-hold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor to bipolar junction transistors may implement the techniques presented herein.

Abstract: An amplifier (A1) within a signal processor comprises a pair of complementary differential pairs (DP1, DP2) in the sense that one differential pair comprises transistors having a polarity opposite to that of transistors in the other differential pair. The one and the other differential pair commonly receive a differential input signal, which has a common mode component. A current combining circuit (CC) combines output currents of the one and the other differential pair so as to obtain an output current that varies as a function of the differential input signal. The one and the other differential pair each have a biasing circuit (R1, R2), which provides a tail current that varies with the common mode component in a substantially linear fashion.

Abstract: An operational amplifier that can suppress lowering of the current driving capability while performing a self adjustment of the common mode voltage is disclosed. A common mode voltage adjusting transistor and an auxiliary transistor are connected in parallel with a low-voltage side drive transistor of each of push-pull amplifying circuits that produce first and second amplified difference signals having different polarities in accordance with drive signals obtained by level-shifting a difference signal indicating a difference value of the levels of the first and second input signals by predetermined values. Current drive capabilities during a period of outputting said first and second amplified difference signals and a common mode voltage adjusting period respectively are increased by driving said auxiliary drive transistor by alternately using the drive signal obtained by level-shifting the difference signal and a common mode voltage adjusting signal.

Abstract: In an embodiment, a circuit includes a two-stage amplifier and a feedback component. The two stage amplifier consists of an input stage biased at a first power supply voltage, and an output stage biased at a second power supply voltage. The second power supply voltage is greater than the first power supply voltage, and the second stage is configured for high voltage operation. The feedback component is connected between the output stage to the input stage.

Abstract: An equalization circuit includes a first differential amplifier having first and second transistors, and a first differential high-pass filter coupled to respective gate terminals of the first and second transistors. A source terminal of the first transistor is coupled to a first input node, and a source terminal of the second transistor is coupled to the second input node. The equalization circuit further includes a second differential amplifier having third and fourth transistors, and a second differential high-pass filter coupled to respective gate terminals of each of the third and fourth transistors. A source terminal of the third transistor is coupled to the first input node, and a source terminal of the second transistor is coupled to the second input node. Using such a circuit, continuous time decision feedback equalization may be performed.

Abstract: A signal generating apparatus comprises an amplifier, which comprises differential input terminals for receiving a first input signal, a common mode output signal adjusting terminal for receiving a second input signal, and an output terminal. The signal generating apparatus may provide two or more differential output signals according to the first input signal, and provide two or more common mode output signals according to the second input signal. The amplifier provides an output signal comprising one of the differential output signals and one of the common mode output signals at the output terminal.

Abstract: Provided herein are methods and circuits that reduce a differential capacitance at differential nodes of a differential circuit while boosting the common mode capacitance at the differential nodes, where the differential circuit includes a pair of inputs and differential outputs. A negative capacitance is generated between differential nodes of the differential circuit, which can be accomplished by connecting a negative capacitance circuit between the differential nodes of the differential circuit. In an embodiment, the negative capacitance circuit is connected in parallel with the differential outputs of the differential circuit. In another embodiment, the negative capacitance circuit is connected in parallel with the inputs of the differential circuit. In still another embodiment, the negative capacitance circuit is connected in parallel with the differential internal nodes (i.e., nodes other than the input and output nodes) of the differential circuit.

Abstract: A level formatter is provided that has differentially coupled closed loop current sources, each configured to precisely establish a current proportional to a reference voltage. A bridge circuit is differentially coupled to two supplementary current sources and controlled to rapidly switch the current from the supplementary current sources to produce output voltages at respective outputs that are approximately equal to respective one of two reference voltages.

Abstract: A switched-capacitor amplifier circuit (200 and 300) with rail-to-rail capability without requiring a rail-to-rail operational amplifier includes a switched-capacitor amplifier (202 and 302) and an input network (201) coupled to the switched-capacitor amplifier. The switched-capacitor amplifier includes a non-rail-to-rail operational amplifier (275 and 375). The input network prevents the non-rail-to-rail operational amplifier from receiving an input differential signal that has a common-mode voltage at or near rails of the non-rail-to-rail operational amplifier. Voltages at input terminals of the operational amplifier remain near analog ground, which is an arbitrary voltage level between the rails, during both phases of switching in the switched-capacitor amplifier. In one embodiment, the switched-capacitor amplifier uses a correlated double sampling technique.

Abstract: An approach to rejecting input common-mode voltage variations in a sampler/converter that avoids the use of a differential amplifier in the signal path, and without introducing added distortion or noise. In one embodiment, the input common-mode variations are sensed on a pair of matched resistors that straddle the common mode analog inputs, on a node ‘Vcmi’. An alternative, switched-capacitor-based sensing scheme is also possible. Using this measured Vcmi, adjustments are then made to the rest of the sampler/converter to take out any variations observed at Vcmi.

Abstract: A variable gain amplifier includes a first common mode (CM) node configured to receive a first differential signal of a pair of differential signals. A first regulator couples to the first CM node, the first regulator being configured to generate a first CM offset. A second CM node is configured to receive a second differential signal of the pair of differential signals. A second regulator couples to the second CM node, the second regulator being configured to generate a second CM offset. In one embodiment, the first CM offset and the second CM offset together comprise a net CM offset, the net CM offset being configured to replace a current source net offset.

Abstract: A switched-capacitor circuit including at least one first capacitor and a circuit for switching at least one armature of the first capacitor alternately to one and the other of two terminals at a switching frequency. The circuit further includes a second capacitor connected to the first capacitor at a node; and a filtering circuit connecting the node to a virtual ground only for frequencies belonging to a frequency range.

Abstract: There is provided a circuit to make a bias for adjusting a threshold voltage of MOS devices available in a wide range, to extend the amplitude range of the input voltage range of a semiconductor differential amplifier from a power supply potential to a ground potential, and automatically to ensure an operation of a differential pair in the saturation region as rejecting the common-mode signal in the entire voltage range. The semiconductor differential amplifier is configured by the first gates of two four-terminal fin type FETs serving as an input terminal of differential pair, and in that the second gates of the four-terminal fin type FETs interconnected with each other, wherein a signal decreasing monotonously along with the increase in the input common-mode component is input.

Abstract: A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is optionally powered by a supply voltage that is greater than a permitted supply voltage for a processes technology that is used to fabricate the CMOS gain stage. In order to protect CMOS devices within the CMOS gain stage, optional drain-to-bulk junction punch-through protection circuitry is disclosed. A variety of optional features can be implemented alone and/or in various combinations of one another. Optional features include process-voltage-temperature (“PVT”) variation protection circuitry, which renders a gain relatively independent of process, voltage, and/or temperature variations. Optional features further include bandwidth enhancement circuitry.

Abstract: A circuit is provided for use with a reference voltage. The circuit includes a voltage source, a common-mode feedback amplifier and a feedback impedance portion. The common-mode feedback amplifier may be connected to the voltage source and may be arranged to receive the reference voltage. The common-mode feedback amplifier may include an input stage, an output stage, a positive input, a negative input and an output. The output may be connected to the feedback impedance portion. The feedback impedance portion may additionally be connected to one of the positive input and the negative input. A feedback factor, based on the feedback impedance portion, is less than one.

Abstract: In an embodiment of the invention, a differential input signal is coupled to a plurality of transconductance blocks. In some embodiments, each of the transconductance blocks divide an input transconductance among a plurality of signal paths to a plurality of outputs in each transconductance block. In an embodiment, the input transconductance may be divided based a ratio of transistor areas in the plurality of signal paths, though other embodiments may divide the transconductance differently. In some embodiments, transconductance block outputs of a plurality of transconductance blocks may be cross-coupled to provide a gain path for a differential signal than is greater than that of a common mode signal.

Abstract: An amplifier circuit may include an input differential pair that includes a first transistor and a second transistor, a positive input voltage being supplied to a gate terminal of the first transistor, a negative input voltage being supplied to a gate terminal of the second transistor, a first resistor that generates a differential current corresponding to a differential voltage between the positive input voltage and the negative input voltage, an output differential pair that includes a third transistor and a fourth transistor, a negative output voltage being supplied from a drain terminal of the third terminal, a positive output voltage being supplied from a drain terminal of the fourth terminal, a second resistor that is connected to a reference voltage, the differential current generated by the first resistor being supplied to the second resistor, and a bias circuit that supplies a constant bias current to the first, second, third, and fourth transistors.

Abstract: A driver circuit for a semiconductor laser diode (LD) is disclosed, in which the driver circuit drives the LD in the differential mode and lowers the power consumption thereof. The driver circuit includes a differential unit to provide the modulation current to the LD, a voltage converter to provide a positive power supply to the differential unit, a detector to detect the common mode voltage of the differential outputs of the unit, and a comparing unit to control the voltage converter dynamically such that the output common mode voltage is set in a preset reference level.

Abstract: System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.

Abstract: The present disclosure describes a variable gain transconductor having gain and/or linearity performance that are selectively controllable in operation. In one embodiment the gain and/or linearity performance are selectively controllable in response to the strength of an input signal, such as an incoming radio frequency (RF) signal to a radio receiver. In one embodiment, gain and/or linearity performance of the variable gain transconductor are selectively controllable by selecting or deselecting a number of operating bias cells. In one embodiment, gain and/or linearity performance of the variable gain transconductor are selectively controllable by selecting or deselecting a number of operating transconductance (gm) cells. In one embodiment, gain and/or linearity performance of the variable gain transconductor are selectively controllable by selecting or deselecting a combination of operating bias cells and gm cells.

Abstract: An improved rail-to-rail (R-R) input stage circuit with dynamic bias control is described. Input stage circuit includes a differential pair circuit, a level shifted differential pair and a bias control circuit. The differential pair circuit and the level shifted differential pair are of same type, non-complementary MOS devices. In exemplary embodiments, a first and a second bias control circuits dynamically control the bias current of the level shifted differential pair and the bias current of the differential pair circuit, respectively, in response to the input common mode voltage of the rail-to-rail input stage circuit. First and second bias control circuits maintain the output impedance of the R-R input stage circuit at a desired level, as the R-R input stage circuit operates outside the input common mode voltage range supported by the level shifted differential pair and the differential pair circuit, respectively. Further exemplary embodiments include a first and a second gm control circuits.

Abstract: A variable gain amplifier includes a first common mode (CM) node configured to receive a first differential signal of a pair of differential signals. A first regulator couples to the first CM node, the first regulator being configured to generate a first CM offset. A second CM node is configured to receive a second differential signal of the pair of differential signals. A second regulator couples to the second CM node, the second regulator being configured to generate a second CM offset. In one embodiment, the first CM offset and the second CM offset together comprise a net CM offset, the net CM offset being configured to replace a current source net offset.

Abstract: A broadband active circuit with a feedback structure includes: an active load unit providing a load varied according to a control voltage; an active circuit unit connected between the active load unit and a ground and outputting a signal corresponding to a pre-set bandwidth, among input signals; and a feedback circuit unit formed between an output terminal of the active circuit unit and the active load unit and providing a signal from the output terminal of the active circuit unit to the active load unit.

Abstract: A fully differential amplifier circuit according to one embodiment includes a first section for generating first and second output signals on first and second outputs from first and second input signals; a first feedback loop coupled to the first section, the first feedback loop including a second section for adjusting the first output signal towards a common mode voltage level, and for reducing an offset voltage of the first output signal; a second feedback loop coupled to the first section, the second feedback loop including a third section for adjusting the second output signal towards the common mode voltage level, and for reducing an offset voltage of the second output signal; and a filter section positioned on the first and second feedback loops between outputs of the second and third sections and the first section.

Abstract: An operational amplifier has an input stage that branches a first current according to first and second input signals. An output stage generates an output signal from a second current and one of the branch currents in the input stage. A first transistor supplies the first current to the input stage. A second transistor supplies the second current to the output stage. A first gate line supplies a first bias potential to the gate terminal of the first transistor. A second gate line supplies a second bias potential to the gate terminal of the second transistor. The first gate line and the second gate line are electrically isolated from each other, preventing unwanted feedback of the output signal to the input stage by leakage through the gate lines.

Abstract: Briefly, one or more embodiments of an amplifier, including example applications, are described.

Abstract: The present invention is intended to achieve a transconductance amplifier and a voltage/current converting method which can provide a sufficient amplitude and a high degree of design freedom. The method comprises the steps of converting a first voltage signal to a first current signal; converting a second voltage signal to a second current signal; obtaining the common-mode components of the first and second current signals; and subtracting the common-mode components from the first and second current signals to obtain third and fourth signals, and further, subtracting the fourth current signal from the third current signal to generate a first output, while subtracting the third current signal from the fourth current signal to generate a second output.

Abstract: A device and a method for eliminating feedback common mode signals are provided, which belong to the electronic technology field. The device includes an operational amplifier circuit with two output ends. The two output ends are a first output end and a second output end. The device also includes a feedback unit. The feedback unit is configured to receive level signals of the first output end and the second output end of the operational amplifier circuit, and superpose feedback common mode signals to input ends of the operational amplifier circuit according to states of the level signals. The method includes: the feedback unit receives level signals of a first output end and a second output end of an operational amplifier circuit, and superposes feedback common mode signals to the input ends of the operational amplifier circuit according to the states of the level signals.

Abstract: An amplifier includes a first pair of transistors (the first pair) that defines a first output, each transistor of the first pair having a gate coupled to a first input terminal; a second pair of transistors (the second pair) that defines a second output, each transistor of the second pair having a gate coupled to a second input terminal; a first capacitor coupled to the second output terminal and to the gate of a first transistor of the first pair; a second capacitor coupled to the second output terminal and to the gate of a second transistor of the first pair; a third capacitor coupled to the first output terminal and to the gate of a third transistor of the second pair; and a fourth capacitor coupled to the first output terminal and to the gate of a fourth transistor of the second pair.

Abstract: Circuits (FIG. 1) that operate with power supplies (VDD) of less than 1 Volt are present. More particularly, circuits (FIG. 1) that operate with supply voltages (VDD) near or lower than the threshold voltage of the transistors (M1A, M1B) in those circuits are presented. Various circuits and embodiments such as operational transconductance amplifiers, biasing circuits, integrators, continuous-time sigma delta modulators, track-and-hold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor (MOS) to bipolar junction transistors may implement the techniques presented herein.

Abstract: To provide a common-mode feedback circuit that feeds back signal corresponding to common-mode components of output terminal voltage of first and second amplifiers to input terminals of the first and second amplifiers via first and second passive elements connected to a common terminal, respectively.

Abstract: A differential amplifier unit and a feedback unit are provided. The differential amplifier unit includes first and second transistors and first to fourth loads. Each of the first and second transistors is provided with a current input end, a current output end connected to a lower potential power source and a control end. The first and second loads are cascade connected between a higher potential power source and the current input end of the first transistor. The third and fourth loads are cascade connected between the higher potential power source and the current input end of the second transistor. The feedback unit generates first and second feedback currents based on first and second output voltages. The feedback unit inputs the first and second feedback currents to a third node connecting the first and second loads and a fourth node connecting the third and fourth loads.

Abstract: A circuit for outputting an amplified clock signal is disclosed. The circuit includes a first input terminal for inputting a first clock signal, a second input terminal for inputting a second clock signal, a first amplifier circuit for amplifying the first clock signal and outputting a first amplified clock signal at a first output terminal, and a second amplifier circuit for amplifying the second clock signal and outputting a second amplified clock signal at a second output terminal. The circuit additionally includes a level maintenance circuit connected to the first output terminal and the second output terminal. The circuit further includes an output circuit connected to the first output terminal and the second output terminal and configured to output a further amplified clock signal based on the first amplified clock signal and the second amplified clock signal. The level maintenance circuit is configured to reduce duty distortion in the further amplified clock signal.

Abstract: An operational amplifier includes an input stage for generating a first differential output signal pair according to a first differential input signal pair, an output stage for generating a second differential output signal pair according to at least a second differential input signal pair, and a high-pass filtering circuit coupled between the input stage and the output stage for performing high-pass filtering on the first differential output signal pair, for generating the at least a second differential input signal pair.

Abstract: An electronic system generates at least one floating supply voltage, wherein during operation of the circuit the floating supply voltage tracks a common mode voltage of first and second differential input signals. By tracking the common mode voltage, in at least one embodiment, the floating supply voltage adjusts as the common mode voltage changes. Thus, the floating supply voltages can be based upon the peak-to-peak values of the first and second output signals without factoring in the common mode voltage. In at least one embodiment, the electronic system provides the floating supply voltages to an amplifier. The amplifier amplifies the first and second differential input signals and generates differential output signals. A differential sampling circuit samples the differential output signals to cancel the common mode voltage from the differential output signals. In at least one embodiment, an analog-to-digital converter converts the sampled differential output signals into a digital output signal.