Including Field Effect Transistor Patents (Class 330/277)
  • Patent number: 10270402
    Abstract: A system may include a radio frequency (RF) amplifier device that includes an input impedance matching network and first and second baseband decoupling circuits, which may remove intermodulation distortion products from signal energy input to the RF amplifier device at baseband frequencies. The input impedance matching network may act as a band-pass or low-pass filter. A gate bias voltage may be applied to the gate of a transistor in the RF amplifier device through one of the baseband decoupling circuits or, alternatively, at an input node of the RF amplifier device.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 23, 2019
    Assignee: NXP USA, Inc.
    Inventors: Damon G. Holmes, Jeffrey Kevin Jones, Ning Zhu, Jeffrey Spencer Roberts
  • Patent number: 10270406
    Abstract: A power amplifier includes a main amplifier, an auxiliary amplifier, and a control circuit. The main amplifier is configured to amplify input power, and the auxiliary amplifier is configured to amplify the input power when the input power exceeds a certain level. The control circuit, which is provided between a source of the main amplifier and a ground, is configured to control a source potential of the main amplifier so as to increase the source potential when the input power reaches at least a certain value.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: April 23, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Masato Nishimori, Tatsuya Hirose, Ikuo Soga, Masayuki Hosoda, Tadahiro Imada
  • Patent number: 10263815
    Abstract: This disclosure relates generally to continuous time linear equalization. In an example of a continuous time linear equalizer, a variable gain circuit includes transistors having gate nodes respectively as a first and a second input node. A first transimpedance circuit is connected between the first input node and a first output node. A second transimpedance circuit is connected between the second input node and a second output node. A source node of each of the first transistor and the second transistor are commonly connected to one another. In the same or another equalizer, output nodes of a first frequency peaking circuit are connected to input nodes of a second frequency peaking circuit. In such a same or another equalizer, an RC feedback circuit has tap-off nodes and summing nodes respectively connected at the output nodes of the first frequency peaking circuit.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: April 16, 2019
    Assignee: XILINX, INC.
    Inventors: Kevin Geary, Declan Carey, Mohamed Elzeftawi
  • Patent number: 10250209
    Abstract: Provided is a power amplification module that supports a plurality of communication systems. The power amplification module includes: two power amplifiers that can be selectively connected in parallel with each other; a switch that, in accordance with one communication system selected from among the plurality of communication systems, selects one power amplifier that is to operate by itself from among the two power amplifiers or selects the two power amplifiers and connects the two power amplifiers in parallel with each other; and a phase correction circuit that, when the two power amplifiers are both selected, corrects a phase difference by being selectively connected between the outputs of the two selected power amplifiers such that a phase difference is not generated between the output signals of the two selected power amplifiers.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: April 2, 2019
    Assignee: MURATA MANUGACTURING CO., LTD.
    Inventors: Takayuki Tsutsui, Fumio Harima
  • Patent number: 10250197
    Abstract: A multiple-stage amplifier includes a driver stage die and a final stage die. The final stage die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a first transistor. The driver stage die includes another type of semiconductor substrate (e.g., a silicon substrate), a second transistor, and one or more secondary circuits that are electrically coupled to a control terminal of the first transistor. A connection (e.g., a wirebond array or other DC-coupled connection) is electrically coupled between an RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die. The secondary circuit(s) of the driver stage die include a final stage bias circuit and/or a final stage harmonic control circuit, which are electrically connected to the final stage die through various connections.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: April 2, 2019
    Assignee: NXP USA, Inc.
    Inventors: Joseph Schultz, Enver Krvavac, Yu-Ting David Wu, Nick Yang, Jeffrey Jones, Mario Bokatius, Ricardo Uscola
  • Patent number: 10171040
    Abstract: The present disclosure provides a trans-impedance amplifier, comprising: an equivalent secondary amplifier module, having an input end and an output end, wherein the input end is coupled to an optical diode and used for accessing an input voltage signal, and the output end is used for outputting a secondarily amplified first voltage signal; an inverting amplifier unit, coupled to the output end of the equivalent secondary amplifier module and used for accessing the first voltage signal and outputting an inverting amplified voltage signal, the inverting amplifier unit comprising a third N-type transistor and a fourth N-type transistor coupled to the third N-type transistor; and a feedback resistor, coupled to the input end of the equivalent secondary amplifier module and an output end of the inverting amplifier unit. The feedback resistor of the trans-impedance amplifier can be not restricted by original conditions, may increase resistance, reduce input noise and improve sensitivity.
    Type: Grant
    Filed: December 17, 2017
    Date of Patent: January 1, 2019
    Assignee: HANGZHOU HONGXIN MICROELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Hehong Zou
  • Patent number: 10171047
    Abstract: A power amplifier circuit comprising a transistor for receiving a signal to be amplified at an input and for outputting an amplified signal at an output; a modulated power supply connected to the transistor output; and a resistive element connected at the transistor output such that a low impedance is maintained at the transistor output across a range of operational frequencies.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: January 1, 2019
    Assignee: SnapTrack, Inc.
    Inventor: Martin Paul Wilson
  • Patent number: 10153738
    Abstract: A radio frequency (RF) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, a first current electrode for providing an RF output signal at an output terminal, and a second current electrode coupled to a voltage reference. The decoupling circuit includes a first inductive element, a first resistor, and a first capacitor coupled together in series between the first current electrode of the power transistor and the voltage reference. The decoupling circuit is for dampening a resonance at a frequency lower than an RF frequency.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: December 11, 2018
    Assignee: NXP USA, INC.
    Inventors: Hussain H. Ladhani, Gerard J. Bouisse, Jeffrey K. Jones
  • Patent number: 10116264
    Abstract: Embodiments of the disclosure relate to calibrating a power amplifier. The power amplifier calibration circuit is configured to provide a plurality of bias signal combinations each including a respective first bias signal and a respective second bias signal to the power amplifier. Power amplifier performance parameters for each of the bias signal combinations can be measured and provided to a control circuit in the power amplifier calibration circuit. The control circuit is configured to rank the measured power amplifier performance parameters based on predefined ranking criteria and determines a selected bias signal combination that can optimize the power amplifier performance parameters of the power amplifier. As such, it is possible to calibrate the power amplifier to operate at a balanced performance level, thus helping to improve radio frequency (RF) coverage and performance of the remote unit in a wireless distribution system (WDS).
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: October 30, 2018
    Assignee: Corning Optical Communications Wireless Ltd
    Inventors: Amit Gutman, Shlomi Kaduri, Roi Yosy Ziv
  • Patent number: 10109625
    Abstract: A power integrated circuit and a method of forming includes forming a first body region of a first conductivity type in a first deep well of a second conductivity type. The power integrated circuit includes a first deep diffusion region formed under the first body region and in electrical contact with the first body region where the first deep diffusion region is formed by performing first and second ion implantations of dopants of the first conductivity type and using second implant energy greater than the first implant energy.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: October 23, 2018
    Assignee: Alpha and Omega Semiconductor, Inc.
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 10108209
    Abstract: According to one embodiment, there is provided a semiconductor integrated circuit including an output transistor, an error amplifier, and a control circuit. The output transistor is connected between a first node on an input terminal side and a second node on an output terminal side. The error amplifier has a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal is connected to a third node between the second node and a standard potential. The inverting input terminal is connected to a reference voltage. The output terminal is connected to the gate of the output transistor. The control circuit makes responsiveness of the error amplifier at startup slower than responsiveness of the error amplifier at steady operation.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: October 23, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroyuki Ideno, Hidefumi Kushibe
  • Patent number: 10089573
    Abstract: [Problem to be Solved] To provide an RF tag antenna capable of improving readability and a method of manufacturing the same, and an RF tag.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: October 2, 2018
    Assignee: PHOENIX SOLUTION CO., LTD.
    Inventors: Shiro Sugimura, Tatsuji Niwata
  • Patent number: 10069464
    Abstract: The present disclosure relates systems and methods for providing a three-dimensional device architecture for transistor elements in a power amplifier circuit. Namely, an example system may include a plurality of high electron mobility transistors disposed on a first substrate. A first portion of the plurality of high electron mobility transistors are electrically coupled via respective first level interconnects disposed on the first substrate. The system also includes a plurality of second level interconnects disposed on a second substrate. A second portion of the plurality of high electron mobility transistors are electrically coupled via respective second level interconnects. The first substrate and the second substrate are coupled such that the plurality of high electron mobility transistors provides an amplified output signal via at least one of the first level interconnects or the second level interconnects.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: September 4, 2018
    Assignee: The Boeing Company
    Inventors: Andrew George Laquer, Dean L Araki, Pohan Yang
  • Patent number: 10064585
    Abstract: According to an embodiment, a photon detecting element includes one or more avalanche photodiodes and a circuit. The circuit is connected between cathodes of the one or more avalanche photodiodes and an external power source. The circuit is configured in which a first temperature coefficient representing variation of a setting potential with respect to temperature variation when constant-current driving is performed so that electrical potential of the cathodes becomes equal to the setting potential is substantially the same as a second temperature coefficient representing variation of breakdown voltage of the one or more avalanche photodiodes with respect to temperature variation.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: September 4, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shunsuke Kimura, Hiroshi Ota, Go Kawata, Hideyuki Funaki, Rei Hasegawa
  • Patent number: 10062947
    Abstract: An RF transmitter with a power combiner and a differential amplifier is provided. The power combiner converts a differential output signal to a single-end output signal and transmits the single-end output signal to the antenna. The differential amplifier includes common-source input transistors, common-gate output transistors and a switch module. The common-source input transistors amplify a differential input signal and output an amplified differential signal. The common-gate output transistors, including sources electrically coupled to the common-source input transistors and drains electrically coupled to the power combiner, generate the differential output signal according to the amplified differential signal. The switch module is electrically coupled between the gates. The switch module electrically couples the gates of the common-gate output transistors if the RF transmitter is in operation and electrically isolates the gates if the RF receiver is in operation.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: August 28, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ting-Yao Huang, Po-Chih Wang
  • Patent number: 10033340
    Abstract: Certain aspects of the present disclosure generally relate to a multi-output amplifier implemented using a capacitive attenuator. For example, the multi-output amplifier generally includes a first capacitive attenuator coupled to an input node of the multi-output amplifier. In certain aspects, the multi-output amplifier also includes a first amplification stage having an input coupled to a tap node of the first capacitive attenuator and an output coupled to a first output node of the multi-output amplifier, and a second amplification stage having an output coupled to a second output node of the multi-output amplifier. For certain aspects, the multi-output amplifier includes a second capacitive attenuator coupled to the input node of the multi-output amplifier, and the second amplification stage may have an input coupled to a tap node of the second capacitive attenuator.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: July 24, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Bassel Hanafi, Sherif Abdelhalem, Hasnain Lakdawala
  • Patent number: 10033337
    Abstract: A multi-stage low-noise amplifier (LNA) device with a band pass response includes a first LNA in series with a second LNA. The device further includes multiple outputs coupled to the second LNA. Each of the outputs is capable of being active at the same time. The device further includes a high pass filter coupled between the first LNA and the second LNA.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: July 24, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Chirag Dipak Patel, Sasha Vujcic, Aleksandar Miodrag Tasic, Timothy Gathman, Wu-Hsin Chen, Klaas Van Zalinge
  • Patent number: 10014844
    Abstract: A circuit includes an amplifier having an input that receives an alternating current (AC) waveform and an output that is coupled to a power source via a bias resistor. A bulk acoustic wave (BAW) resonator is coupled in parallel to the bias resistor via the power source and the amplifier output. The BAW resonator and the amplifier output forms a band pass filter to filter the AC waveform received at the amplifier input and to provide a filtered AC waveform at the amplifier output.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: July 3, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kumar Anurag Shrivastava, Subhashish Mukherjee, Madhulatha Bonu
  • Patent number: 10014829
    Abstract: Amplifier circuits comprising an input transistor, a load transistor, and a feedback resistor. In one example, one embodiment is directed to an amplifier circuit comprising an input transistor, a load transistor having a control terminal and a reference terminal, and a feedback transistor. The input transistor receives an input signal, the input transistor is electrically coupled to the load transistor and the feedback transistor, the control terminal of the load transistor is electrically coupled to a bias voltage, the feedback transistor is electrically coupled to the load transistor providing negative feedback, and the reference terminal of the load transistor serves as an output of the amplifier circuit.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: July 3, 2018
    Assignee: OMNI DESIGN TECHNOLOGIES, INC.
    Inventor: Hae-Seung Lee
  • Patent number: 9985684
    Abstract: A passive equalizer is provided. The passive equalizer includes a first resistive element, a first inductive element, a second resistive element, and a first variable capacitor. The first resistive element is coupled between an input node and an output node. The first inductive element and the second resistive element are coupled in series between the output node and a first voltage supply node. The first variable capacitor is coupled between the input node and a first node located between the first inductive element and the second resistive element.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 29, 2018
    Assignee: NXP USA, INC.
    Inventor: Kevin Yi Cheng Chang
  • Patent number: 9961440
    Abstract: A method and a system for ultra-low-power acoustic sensor including a buffer transistor, which gate terminal is connected to a first terminal of a capacitive acoustic sensor, which drain terminal is connected via a load network to a power source and to an output terminal, and which source terminal is connected to the regulated current source, where the regulated current source is connected between the source terminal of the buffer transistor and a reference terminal, and where the reference terminal being connectable to a second terminal of the capacitive acoustic sensor.
    Type: Grant
    Filed: December 25, 2014
    Date of Patent: May 1, 2018
    Assignee: WIZEDSP LTD.
    Inventors: Oz Gabai, Haim Primo
  • Patent number: 9954492
    Abstract: An amplifier arrangement comprises N amplifier stages, wherein N is an integer equal or greater than five. The amplifier arrangement comprises a first cascade of quarter wavelength transmission line segments coupled to receive a first set of amplifier stages, and at least a second cascade of quarter wavelength transmission line segments coupled to receive a second set of amplifier stages. The first cascade and second cascade are connected to a common node, for example in parallel to an output node, or in parallel to an intermediate node.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: April 24, 2018
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventor: Richard Hellberg
  • Patent number: 9948249
    Abstract: An integrated matching circuits for a high frequency amplifier transistor having an input terminal, an output terminal and a reference terminal. The reference terminal is coupled to a reference potential. The integrated matching circuit comprises an inductive element, and a capacitive element arranged in a series arrangement with the inductive element. The series arrangement has a first terminal end connected to the input terminal or to the output terminal and a second terminal end connected to the reference terminal. The first terminal end and the second terminal end are arranged at a same lateral side of the integrated matching circuit to obtain a geometry with the first terminal end adjacent to the input terminal or to the output terminal and the second terminal end adjacent to the reference terminal.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: April 17, 2018
    Assignee: NXP USA, INC.
    Inventor: Youri Volokhine
  • Patent number: 9912305
    Abstract: A semiconductor integrated circuit includes a transformer that includes a first winding and a second winding, a low-noise amplifier circuit that includes an input terminal in which at least one end of the second winding of the transformer is connected to the input terminal; and a switch that is provided between the one end and another end of the second winding of the transformer. The switch is opened and the transformer functions as an input impedance matching circuit for the low-noise amplifier circuit in a period in which a reception signal is supplied to the first winding of the transformer. On the other hand, the switch is closed and the transformer is caused to become an element including a predetermined capacitance in a period in which another circuit connected to the predetermined node operates.
    Type: Grant
    Filed: February 14, 2016
    Date of Patent: March 6, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Noriaki Matsuno
  • Patent number: 9912301
    Abstract: Amplifiers can be used for a variety of electronic-based applications. Therefore, amplifier performance is of importance. A low noise amplifier can be interfaced after an antenna or a band-select filter as a first active stage, in a receiver since its bandwidth characteristics can be closely related to a system data rate. A bandwidth enhancement technique can be leverage for low noise amplifiers by embedding a transformer between a gate and a drain terminal of a common gate transistor in a cascode topology. The embedded transformer can introduce an additional high-frequency conjugate zero pair, which can push the gain rolling-off start-up point to a higher frequency, peak the higher frequency gain, and broaden the low noise amplifier gain bandwidth.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: March 6, 2018
    Assignee: CITY UNIVERSITY OF HONG KONG
    Inventors: Quan Xue, Pei Qin, Kam Man Shum
  • Patent number: 9900717
    Abstract: A thermal protecting device of a speaker is provided. The thermal protecting device includes an amplifier and a temperature detecting unit. An input end of the amplifier receives an audio reference signal, an output end of the amplifier provides an audio output signal to the speaker. The temperature detecting unit receives an audio input signal to provide the audio reference signal, and detects an operation temperature of the speaker to determine an amplitude of the audio reference signal. The amplitude is inversely proportional to the operation temperature.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: February 20, 2018
    Assignee: ASUSTeK COMPUTER INC.
    Inventor: Wen-Hung Lin
  • Patent number: 9882531
    Abstract: A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: January 30, 2018
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Simon Edward Willard, Chris Olson, Tero Tapio Ranta
  • Patent number: 9866190
    Abstract: An amplifier circuit (100) comprises three amplifier subcircuits (121,131,141) connected via a network of transmission lines to a common node. A control circuit is configured to control the three amplifier subcircuits (121,131,141) to operate in first, second, and third operating modes, such that a first subcircuit (121) is active in the first, second, and third modes, a second sub-circuit (141) is inactive in the first mode but active in the second and third modes, and a third subcircuit (131) is inactive in the first and second modes but active in the third. A quarter-wavelength transmission line (170) couples the output node of the second sub circuit (141) to the output node (160) of the third subcircuit (131).
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: January 9, 2018
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Richard Hellberg
  • Patent number: 9853605
    Abstract: A transistor package according to one exemplary embodiment includes main transistors and a sub-transistor placed in the same package as the main transistors and having a smaller size than the main transistors. It is thereby possible to provide a transistor package with more versatility capable of forming various types of Doherty amplification circuits such as a Doherty amplification circuit with auto-biasing function and an extended Doherty amplification circuit with desired operating characteristics, an amplification circuit including the same, and a method of forming a transistor.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: December 26, 2017
    Assignee: NEC Corporation
    Inventor: Kazumi Shiikuma
  • Patent number: 9848264
    Abstract: An audio signal amplification device of the disclosure includes: a delta-sigma modulation part configured to resample an input digital audio signal with a quantization number smaller than a quantization number of the digital audio signal; a pulse-width modulation part configured to convert an output signal from the delta-sigma modulation part into a pulse-width modulation signal which sets a gradation of the output signal in an amplitude direction at a gradation of a pulse width; a power amplification part configured to perform power amplification on an output signal from the pulse-width modulation part; a low-pass filter configured to diminish a component higher than a predetermined cutoff frequency, in an output signal from the power amplification part, and to output the resultant signal; and a correction processing part configured to generate a correction signal for correcting the digital audio signal.
    Type: Grant
    Filed: July 10, 2016
    Date of Patent: December 19, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Kazuya Iwata
  • Patent number: 9800154
    Abstract: A voltage supply unit includes a regulator unit, a current mirror, and a cascode unit. The regulator unit is configured to receive first and second voltage signals and generate a third voltage signal. The current mirror is configured to generate first and second current signals based on the third voltage signal. The cascode unit includes a first terminal configured to receive the first current signal, a second terminal configured to receive a first bias voltage signal, a third terminal configured to receive a second bias voltage signal, and a fourth terminal electrically connected to the regulator unit. An output voltage supply signal is controlled by the second current signal.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: October 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Patent number: 9787258
    Abstract: Circuits, methods and devices are disclosed, related to fast turn-on of radio-frequency (RF) amplifiers. In some embodiments, an RF amplifier circuit includes an amplification path implemented to amplify an RF signal, where the amplification path includes a switch and an amplifier. In some embodiments, each of the switch and the amplifier are configured to be ON or OFF to thereby enable or disable the amplification path, respectively. In some embodiments, the RF amplifier circuit includes a compensation circuit coupled to the amplifier, where the compensation circuit is configured to compensate for a slow transition of the amplifier between its ON and OFF states resulting from a signal applied to the switch.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: October 10, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Lui Lam, Vinu Govind
  • Patent number: 9780741
    Abstract: Compression control of cascode power amplifiers. A power amplifier module can include a power amplifier including a cascode transistor pair. The cascode transistor pair can include a first transistor and a second transistor. The power amplifier module can include a current comparator configured to compare a first base current of the first transistor and a second base current of the second transistor to generate a comparison signal. The power amplifier module can include a saturation controller configured to maintain the power amplifier out of saturation based on the comparison signal.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: October 3, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: David Steven Ripley, Philip John Lehtola
  • Patent number: 9767888
    Abstract: Embodiments relate to systems, methods and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a first resistor connected to a first receiver input, four N-type metal oxide semiconductor (NMOS) field effect transistors (FETs), two PMOS FETS, and a trans-impedance amplifier wherein an input terminal of the trans-impedance amplifier is connected to a drain terminal of the second NMOS FET. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 19, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hari Anand Ravi, Thomas Evan Wilson, Balbeer Singh Rathor
  • Patent number: 9762185
    Abstract: A radio frequency (RF) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, a first current electrode for providing an RF output signal at an output terminal, and a second current electrode coupled to a voltage reference. The decoupling circuit includes a first inductive element, a first resistor, and a first capacitor coupled together in series between the first current electrode of the power transistor and the voltage reference. The decoupling circuit is for dampening a resonance at a frequency lower than an RF frequency.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: September 12, 2017
    Assignee: NXP USA, INC.
    Inventors: Hussain H. Ladhani, Gerard J. Bouisse, Jeffrey K. Jones
  • Patent number: 9755584
    Abstract: According to one embodiment, an amplifier includes: a transistor; a ground circuit connected to a ground terminal of the transistor; a first capacitor connected between an output terminal of the transistor and the ground circuit; a first inductor connected to the output terminal of the transistor; a second capacitor connected between the first inductor and the ground circuit; a bias circuit connected between the first inductor and the ground circuit; a first circuit connected to the output terminal of the transistor, the first circuit including a second inductor and a third capacitor connected in series to the second inductor; a fourth capacitor connected between the first circuit and a load circuit; a fifth capacitor connected between an output terminal of the first circuit and the ground circuit; and a third inductor connected between a terminal on a load circuit side of the fourth capacitor and the ground circuit.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: September 5, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keiichi Yamaguchi
  • Patent number: 9712125
    Abstract: Power amplification system with shared common base biasing. A power amplification system can include a plurality of cascode amplifier sections. Each one of the plurality of cascode amplifier sections can include including a first transistor and a second transistor. The power amplification system can include a plurality of common emitter biasing components. Each one of the plurality of common emitter biasing components can be coupled to a base of the first transistor of a respective one of the plurality of cascode amplifier sections and can be controllable to bias the first transistor of the respective one of the plurality of cascode amplifier sections. The power amplification system can include a common base biasing component coupled to a base of the second transistor of each of the plurality of cascode amplifier sections and controllable to bias the second transistor of each of the plurality of cascode amplifier sections.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: July 18, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Philip John Lehtola, David Steven Ripley
  • Patent number: 9712124
    Abstract: The present disclosure provides a distributed amplifier, including: a drain transmission line; a gate transmission line; GFETs, in which sources of the graphene field-effect transistors are respectively grounded; gates of the graphene field-effect transistors respectively connected with a plurality of first shunt capacitors which are grounded; the gate transmission line is connected with a plurality of first nodes respectively between the gates of the graphene field-effect transistors and the plurality of first shunt capacitors, having a plurality of first inductors respectively between each two first nodes; drains of the graphene field-effect transistors respectively connected with a plurality of second shunt capacitors which are grounded; the drain transmission line is connected with a plurality of second nodes respectively between the drains of the graphene field-effect transistors and the plurality of second shunt capacitors, having a plurality of second inductors respectively between each two second node
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: July 18, 2017
    Assignee: Tsinghua University
    Inventors: Huaqiang Wu, Hongming Lyu, He Qian, Zhiping Yu, Yilin Huang, Jinyu Zhang
  • Patent number: 9705463
    Abstract: Radio frequency power amplifier circuitry includes an amplifier element, power supply modulation circuitry, and bias modulation circuitry. The amplifier element is configured to amplify an RF input signal using a modulated power supply signal and a modulated bias signal to produce an RF output signal. The power supply modulation circuitry is coupled to the amplifier element and configured to provide the modulated power supply signal. The bias modulation circuitry is coupled to the amplifier element and the power supply modulation circuitry and configured to receive the modulated power supply signal and provide the modulated bias signal. Notably, the modulated bias signal is a function of the modulated power supply signal such that the modulated bias signal is configured to maintain a small signal gain of the amplifier element and the phase of the RF input signal at a constant value as the modulated power supply signal changes.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: July 11, 2017
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, George Maxim, Dirk Robert Walter Leipold
  • Patent number: 9698742
    Abstract: An electronic amplifier has a feedback circuit with a transconductance amplifier.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: July 4, 2017
    Assignee: Allegro Microsystems, LLC
    Inventors: Virag V. Chaware, Stephen Marshall
  • Patent number: 9680418
    Abstract: A voltage gain amplifier (VGA) configured to have reduced supply noise. The VGA includes first resistor, first FET, and a first current-source coupled between first and second voltage rails. The VGA includes second resistor, second FET, and second current-source coupled between the voltage rails. A variable resistor is coupled between the respective sources of the first and second FETs. Variable capacitors are coupled between the first or a third voltage rail and the sources of the first and second input FETs, respectively. If capacitors are coupled to the first voltage rail, noise cancellation occurs across the gate-to-source voltages of the FETs if an input differential signal applied to the gates of the FETs is derived from a supply voltage at the first voltage rail. If capacitors are coupled to the third rail, supply noise is reduced if the supply voltage at the third rail is generated by a cleaner regulator.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: June 13, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaobin Yuan, Joseph Natonio, Kevin Robert Bartholomew, Mangal Prasad
  • Patent number: 9680425
    Abstract: A driver circuit for a power amplifier of a radio base station. The driver circuit comprises a radio frequency input, an output for connection to a power amplifier, a combiner connected to the radio frequency input and a first bias leg. The first bias leg comprises a bias source input, a first capacitor leg and a second capacitor, wherein the first capacitor leg is connected between the combiner and ground, and the second capacitor is connected between the combiner and ground. The first capacitor leg comprises a first switch and a first capacitor, the first switch being provided between the combiner and the first capacitor such that, in a first state, the first capacitor is connected to the combiner and, in a second state, the first capacitor is disconnected from the combiner. A corresponding power amplifier assembly, radio base station and method are also presented.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: June 13, 2017
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventor: Zhanyu Wu
  • Patent number: 9673312
    Abstract: A power semiconductor device has an upper transistor and a lower transistor that is coupled in cascode with the upper transistor. The upper transistor comprises an upper drain, upper gate, and an upper source. The lower transistor comprises a lower drain that is coupled to the upper source, a lower gate, and a lower source that is coupled to the upper gate. The upper transistor is a depletion mode device and has a first saturation current. The lower transistor is an enhancement mode device and has a second saturation current, which is lower than the first saturation current.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: June 6, 2017
    Assignee: Qorvo US, Inc.
    Inventors: David Charles Sheridan, Xing Huang
  • Patent number: 9673764
    Abstract: An amplifier circuit, comprises a first amplifier stage contributing to a power of an amplified signal and a second amplifier stage contributing to the power of the amplified signal. The first amplifier stage and the second amplifier stage share a transistor.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: June 6, 2017
    Assignee: Intel IP Corporation
    Inventors: Harald Doppke, Vadim Issakov
  • Patent number: 9673759
    Abstract: Off-chip distributed drain biasing increases output power and efficiency for high power distributed amplifier MMICs. An off-chip bias circuit has a common input for receiving DC bias current and a plurality of parallel-connected bias chokes among which the DC bias current is divided. The chokes are connected to a like plurality of drain terminals at different FET amplifier stages to supply DC bias current at different locations along the output transmission line. Off-chip distributed drain biasing increases the level of DC bias current that can be made available to the amplifier and add inductances to selected FET amplifier stages, typically the earlier stages, to modify the load impedance seen at the drain terminal to better match the amplifier stages to improve power and efficiency.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 6, 2017
    Assignee: Raytheon Company
    Inventors: David R. Fletcher, David D. Heston
  • Patent number: 9660598
    Abstract: Devices and methods for improving reliability of scalable periphery amplifiers is described. Amplifier segments of the scalable periphery architecture can be rotated to distribute wear. Further, extra amplifier segments can be implemented on amplifier dies to extend the overall lifetime of amplifiers.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: May 23, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Chris Olson
  • Patent number: 9654055
    Abstract: A radio-frequency power amplifier with envelope tracking, having a power RF amplifying device for amplifying a RF signal and a switching DC/DC converter for providing the power RF amplifying device with a DC power supply at a voltage level (VSUPP) proportional to an envelope of the RF signal, wherein the switching DC/DC converter has a reversed buck topology. Advantageously the switching device is a N-type GaN Field Effect Transistor having its drain connected to the ground.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: May 16, 2017
    Assignee: Agence Spatiale Europeenne
    Inventors: Christophe Delepaut, Nicolas Le Gallou
  • Patent number: 9634616
    Abstract: A single-end amplifier includes: a noise cancelling circuit, coupled to a power supply, configured to receive a power signal and to cancel a part of ripples and noises in the power signal to generate an initial signal; an amplifying circuit, configure to receive the initial signal at a first end of the amplifying signal, and to amplify the initial signal to generate a first signal at a second end; and a first transmitting circuit, configured to receive the power signal and to generate a second signal at the second end of the amplifying circuit. The first signal and the second signal are superimposed and outputted to cancel most part of the ripples and noises in the power signal. The noise cancelling circuit includes a first capacitor and a first choke coil.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: April 25, 2017
    Assignee: MStar Semiconductor, Inc.
    Inventors: Chao-Zhou Nan, Jun-Xiong Deng
  • Patent number: 9621115
    Abstract: The embodiments described herein include amplifiers that are typically used in radio frequency (RF) applications. The amplifiers described herein use a combiner that is implemented inside the device package. Specifically, the amplifiers can be implemented with a combiner that includes a transmission line inside the device package, where the transmission line has a length between first and second ends configured to provide an impedance inverter between the outputs (e.g., drain terminals) of transistors in the amplifier.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: April 11, 2017
    Assignee: NXP USA, INC.
    Inventor: Yu-Ting D. Wu
  • Patent number: 9608437
    Abstract: Techniques for improving electro-static discharge (ESD) performance in integrated circuits (IC's). In an aspect, one or more protective diodes are provided between various nodes of the IC. For example, protective diode(s) may be provided between the drain and gate of an amplifier input transistor, and/or between the drain and ground, etc. In certain exemplary embodiments, the amplifier may be a cascode amplifier. Further aspects for effectively dealing with ESD phenomena are described.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: March 28, 2017
    Assignee: Qualcomm Incorporated
    Inventors: Ahmed Abdel Monem Youssef, Prasad Srinivasa Siva Gudem, Li-Chung Chang, Ehab Ahmed Sobhy Abdel Ghany