Including Field Effect Transistor Patents (Class 330/277)
  • Patent number: 11973470
    Abstract: Methods and apparatuses for controlling impedance in intermediate nodes of a stacked FET amplifier are presented. According to one aspect, a series-connected resistive and capacitive network coupled to a gate of a cascode FET transistor of the amplifier provide control of a real part and an imaginary part of an impedance looking into a source of the transistor. According to another aspect, a second parallel-connected resistive and inductive network coupled to the first network provide further control of the real and imaginary parts of the impedance. According to another aspect, a combination of the first and/or the second networks provide control of the impedance to cancel a reactance component of the impedance. According to another aspect, such combination provides control of the real part for distribution of an RF voltage output by the amplifier across stacked FET transistors of the amplifier.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: April 30, 2024
    Assignee: PSEMI CORPORATION
    Inventor: Tero Tapio Ranta
  • Patent number: 11959847
    Abstract: Systems and methods taught herein advantageously provide extended dynamic range capabilities to detect low intensity and high intensity emitted or scattered light from particles at high speeds with high sensitivity. Independently controlled first and second optical detector elements that handle light intensities in different dynamic ranges, large overall dynamic range is created. Signals from the detector elements can be combined to create a single combined signal that has excellent sensitivity over a large dynamic range. The detector systems and methods taught herein are particularly advantageous in particle processing where the population of particles can emit or scatter light over a large range of intensity values.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: April 16, 2024
    Assignee: CYTONOME/ST, LLC
    Inventors: Johnathan Charles Sharpe, Donald Francis Perrault, Jr., Peter Kiesel
  • Patent number: 11955961
    Abstract: Disclosed is a switch circuit for an ultra-high frequency band, which includes a transistor including a first terminal connected to an input stage, a second terminal connected to an output stage, and a gate terminal, an inductor connected to the transistor in parallel, between the input stage and the output stage, a variable gate driver to apply a gate input voltage to the gate terminal and, an input resistor connected between the variable gate driver and the gate terminal. The variable gate driver adjusts the gate input voltage to be in one of a first voltage level for turning on the transistor and a second voltage level for turning off the transistor. The second voltage level varies depending on a capacitance between the first terminal and the second terminal, when the transistor is in a turn-off state.
    Type: Grant
    Filed: August 2, 2022
    Date of Patent: April 9, 2024
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hong Gu Ji, Dong Min Kang, Byoung-Gue Min, Jongmin Lee, Kyu Jun Cho
  • Patent number: 11949385
    Abstract: A biasing circuit with high current drive capability for fast settling of a biasing voltage to a stacked cascode amplifier is presented. According to a first aspect, the biasing circuit uses transistors matched with transistors of the cascode amplifier to generate a boost current during a transition phase that changes the biasing voltage by charging or discharging a capacitor. The boost current is activated during the transition phase and deactivated when a steady-state condition is reached. According to a second aspect, the biasing circuit uses an operational amplifier in a feedback loop that forces a source node of a cascode transistor of a reference circuit, that is a scaled down replica version of the cascode amplifier, to be at a reference voltage. The high gain and high current capability of the operational amplifier, provided by isolating a high frequency signal processed by the cascode amplifier from the reference circuit, allow for a quick settling of the biasing voltage.
    Type: Grant
    Filed: March 3, 2023
    Date of Patent: April 2, 2024
    Assignee: pSemi Corporation
    Inventors: Jonathan James Klaren, Tero Tapio Ranta
  • Patent number: 11942913
    Abstract: A gain adjustment unit constituted by a distribution switch having a control terminal is provided in an input unit of an amplifier circuit. One end of a coupler is connected to an output line of the amplifier circuit, another end of the coupler is connected to an anode of a diode, and a monitor terminal is connected via a low-pass filter to a cathode of the diode. The anode of the diode is unbiased.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: March 26, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hiroshi Hamada, Hideyuki Nosaka
  • Patent number: 11935961
    Abstract: A semiconductor device capable of measuring a minute current is provided. The semiconductor device includes an operational amplifier and a diode element. An inverting input terminal of the operational amplifier and an input terminal of the diode element are electrically connected to a first terminal to which current is input, and an output terminal of the operational amplifier and an output terminal of the diode element are electrically connected to a second terminal from which voltage is output. A diode-connected transistor that includes a metal oxide in a channel formation region is used as the diode element. Since the off-state current of the transistor is extremely low, a minute current can flow between the first terminal and the second terminal. Thus, when voltage is output from the second terminal, a minute current that flows through the first terminal can be estimated from the voltage.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: March 19, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Eri Sato, Tatsuya Onuki, Yuto Yakubo, Hitoshi Kunitake
  • Patent number: 11876138
    Abstract: A semiconductor device capable of measuring a minute current is provided. The semiconductor device includes an operational amplifier and a diode element. An inverting input terminal of the operational amplifier and an input terminal of the diode element are electrically connected to a first terminal to which current is input, and an output terminal of the operational amplifier and an output terminal of the diode element are electrically connected to a second terminal from which voltage is output. A diode-connected transistor that includes a metal oxide in a channel formation region is used as the diode element. Since the off-state current of the transistor is extremely low, a minute current can flow between the first terminal and the second terminal. Thus, when voltage is output from the second terminal, a minute current that flows through the first terminal can be estimated from the voltage.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: January 16, 2024
    Inventors: Eri Sato, Tatsuya Onuki, Yuto Yakubo, Hitoshi Kunitake
  • Patent number: 11824499
    Abstract: A power amplifier circuit includes a first amplifier that amplifies a first signal, and a second amplifier arranged subsequent to the first amplifier. The second amplifier amplifies a second signal that is based on an output signal of the first amplifier. The first amplifier performs class inverse-F operation, and the second amplifier performs class F operation.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: November 21, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hisanori Namie, Mitsunori Samata, Satoshi Tanaka
  • Patent number: 11784610
    Abstract: Embodiments of a device and method are disclosed. In an embodiment, a Doherty amplifier module includes a first amplifier die with a first output terminal, a second amplifier die with a second output terminal, and a wideband impedance inverter circuit electrically coupled between the first and second output terminals. The wideband impedance inverter circuit includes a network of capacitors, the network of capacitors including at least a series capacitor having a positive capacitance, a first shunt circuit having a first negative capacitance, and a second shunt circuit having a second negative capacitance.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: October 10, 2023
    Assignee: NXP USA, Inc.
    Inventors: Anthony Lamy, Olivier Lembeye
  • Patent number: 11777450
    Abstract: An apparatus for turning off a cascode amplifier having a common-gate transistor and a common-source transistor is disclosed that includes the cascode amplifier, a feedback circuit, and a bias circuit. The feedback circuit is configured to receive a drain-voltage from the drain of the common-source transistor when the common-source transistor is switched to a first OFF state and produce a first feedback signal. The drain-voltage is equal to a source voltage of the common-gate transistor and the drain-voltage increases in response to switching the common-source transistor to the first OFF state. The bias circuit is configured to receive the first feedback signal and produce a bias-voltage. A first gate-voltage is produced from the bias-voltage. The cascode amplifier is configured to receive the first gate-voltage and a second gate-voltage. The common-gate transistor is configured to switch to a second OFF state in response to receiving the second gate-voltage.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: October 3, 2023
    Assignee: Silanna Asia Pte Ltd
    Inventor: Stuart Ide Hodge, Jr.
  • Patent number: 11742810
    Abstract: A class AB buffer includes an output stage and an input stage. The output stage includes a first output transistor and a second output transistor. The second output transistor is coupled to the first output transistor. The input stage is coupled to the output stage. The input stage includes a first cascode transistor, a first switch, a second cascode transistor, and a second switch. The first switch is coupled to the first cascode transistor and the first output transistor. The second switch is coupled to the first switch, the second cascode transistor, and the first output transistor.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: August 29, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nitin Agarwal, Aniruddha Roy
  • Patent number: 11705872
    Abstract: Embodiments of RF amplifiers and packaged RF amplifier devices each include an amplification path with a transistor die, and an output-side impedance matching circuit having a T-match circuit topology. The output-side impedance matching circuit includes a first inductive element (e.g., first wirebonds) connected between the transistor output terminal and a quasi RF cold point node, a second inductive element (e.g., second wirebonds) connected between the quasi RF cold point node and an output of the amplification path, and a first capacitance connected between the quasi RF cold point node and a ground reference node. The RF amplifiers and devices also include a baseband termination circuit connected to the quasi RF cold point node, which includes an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the quasi RF cold point node and the ground reference node.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: July 18, 2023
    Assignee: NXP USA, Inc.
    Inventors: Jeffrey Spencer Roberts, Ning Zhu, Olivier Lembeye, Damon G. Holmes, Jeffrey Kevin Jones
  • Patent number: 11699980
    Abstract: A transistor comprises a drain, a gate, a source, a body terminal and a body resistance. The drain is connected to a supply voltage line to receive a supply voltage. The gate is connected to a control voltage line to receive a control voltage. The source is connected to a input line to receive a input radio frequency signal. The body terminal is connected to the drain. The body resistance is disposed between the drain and the body terminal. By the foregoing configuration, the leakage current of the substrate is reduced and the threshold voltage of the transistor is reduced to conform to the present low power design.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: July 11, 2023
    Assignee: FENG CHIA UNIVERSITY
    Inventors: Jin-Fa Chang, Yo-Sheng Lin
  • Patent number: 11664768
    Abstract: An amplification circuit includes: a power supply terminal that is connected to a power supply; a first transistor that has a first source terminal, a first drain terminal, and a first gate terminal to which a high-frequency signal is inputted; a second transistor that has a second source terminal that is connected to the first drain terminal, a second drain terminal that outputs a high frequency signal, and a second gate terminal that is grounded; a capacitor that is serially arranged on a second path that connects the second gate terminal and the power supply terminal; and a switch that is serially arranged on a first path, which connects the second drain terminal and the power supply terminal, or the second path. The second drain terminal and the second gate terminal are connected to each other via the switch and the capacitor.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: May 30, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Daisuke Watanabe
  • Patent number: 11611319
    Abstract: A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: March 21, 2023
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner
  • Patent number: 11610916
    Abstract: A semiconductor structure for RF applications comprises: a first ?TP GaN transistor on an SOI wafer or die; and a first resistor connected to the gate of said first transistor.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: March 21, 2023
    Assignee: X-FAB France SAS
    Inventors: Imène Lahbib, Jérôme Loraine, Frédéric Drillet, Albert Kumar, Gregory U'ren
  • Patent number: 11606089
    Abstract: A decoupling capacitance (decap) system which includes: a decap circuit electrically coupled between a first or second reference voltage rail and a first node; and a biasing circuit coupled between the first node and correspondingly the second or first reference voltage rail. Due to the series connection between the decap circuit and the biasing circuit, the voltage drop across the biasing circuit effectively reduces the voltage drop across the decap circuit so that the voltage drop across the decap circuit is less than a voltage drop across the decap system as whole.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: March 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Szu-Lin Liu, Yi-Hsiang Wang, Jaw-Juinn Horng
  • Patent number: 11601152
    Abstract: An electronic device may include wireless circuitry with a processor, a transceiver, an antenna, and a front-end module coupled between the transceiver and the antenna. The front-end module may include one or more power amplifiers for amplifying a signal for transmission through the antenna. A power amplifier may include a phase distortion compensation circuit. The phase distortion compensation circuit may include one or more n-type metal-oxide-semiconductor capacitors configured to receive a bias voltage. The bias voltage may be set to provide the proper amount of phase distortion compensation.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: March 7, 2023
    Assignee: Apple Inc.
    Inventor: Saihua Lin
  • Patent number: 11601098
    Abstract: Methods and devices for reducing gate node instability of a differential cascode amplifier are presented. Ground return loops, and therefore corresponding parasitic inductances, are eliminated by using voltage symmetry at nodes of two cascode amplification legs of the differential cascode amplifier. Series connected capacitors are coupled between gate nodes of pairs of cascode amplifiers of the two cascode amplification legs so to create a common node connecting the two capacitors. In order to reduce peak to peak voltage variation at the common node under large signal conditions, a shunting capacitor is connected to the common node.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: March 7, 2023
    Assignee: pSemi Corporation
    Inventor: Dan William Nobbe
  • Patent number: 11563460
    Abstract: Described herein are methods for amplifying radio-frequency signals using a variable-gain amplifier with a plurality of input nodes. The methods provide a plurality of gain modes with a low gain mode or bypass mode that follows a bypass path through the variable-gain amplifier and a plurality of higher gain modes that take advantage of tailored impedances for particular gain modes. The tailored impedances can be configured to improve linearity of the amplification process in targeted gain modes. The methods can selectively couple the bypass path to a reference potential node in the plurality of higher gain modes and can selectively decouple the input nodes from a degeneration switching block in the bypass mode.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: January 24, 2023
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Johannes Jacobus Emile Maria Hageraats, Junhyung Lee, Joshua Haeseok Cho, Aravind Kumar Padyana, Bipul Agarwal
  • Patent number: 11552599
    Abstract: Embodiments of the present disclosure include a harmonic power amplifying circuit with high efficiency and high bandwidth and a radio-frequency power amplifier. The circuit comprises an input matching network (11), a transistor (M), and an output matching network (12); a gate of the transistor (M) connected to an output end of the input matching network (11), a drain thereof connected to an input end of the output matching network (12), and a source thereof being grounded; wherein the output matching network (12) enables a lower sideband of the harmonic power amplifying circuit to work in a continuous inverse F amplification mode and an upper sideband of the harmonic power amplifying circuit to work in a continuous F amplification mode; wherein the output matching network (12) and a parasitic network of the transistor (M) form a low pass filter.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: January 10, 2023
    Assignees: CHINA COMMUNICATION MICROELECTRONICS TECHNOLOGY CO., LTD., CHINA COMMUNICATION TECHNOLOGY CO., LTD.
    Inventors: Shoukui Zhu, Qing Ding, Guangsheng Wu, Jianguo Ma
  • Patent number: 11552601
    Abstract: A power amplifier circuit includes an input-stage power amplifier configured to receive a radio-frequency input signal, an output-stage power amplifier configured to output an amplified radio-frequency output signal, and an intermediate-stage power amplifier disposed between the input-stage power amplifier and the output-stage power amplifier. The intermediate-stage power amplifier includes a first transistor, a second transistor, and a capacitor having a first end connected to an emitter of the first transistor and a second end connected to a collector of the second transistor. The intermediate-stage power amplifier receives a signal at a base of the second transistor thereof and outputs an amplified signal from a collector of the first transistor thereof.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: January 10, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shingo Yanagihara, Satoshi Tanaka
  • Patent number: 11522500
    Abstract: An embodiment of a dual-path amplifier includes a power splitter connected to first and second power amplifiers respectively connected to first and second transmission lines connected to a power combiner having a phase-offset deficit at the second harmonic frequency 2f0, where the first and second transmission lines are designed to provide a complementary phase offset at 2f0 substantially equal to the phase-offset deficit such that the two amplified signals will be combined at the power converter with a total phase offset at 2f0 of about 180 degrees in order to reduce harmonic distortion in the amplified output signal, without substantially diminishing the output power at the fundamental frequency f0. In certain PCB-based implementations, the transmission lines include metal traces and lumped elements providing different impedance transformations that achieve the complementary phase offset, where the metal traces may have significantly different physical and electrical characteristics.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: December 6, 2022
    Assignee: NXP USA, Inc.
    Inventors: Arturo Roiz, Justin Nelson Annes, Terry L. Thomas
  • Patent number: 11513165
    Abstract: A power semiconductor module including at least first and second power semiconductor elements, includes a first terminal, a first gate terminal, a second terminal, a second gate terminal, a third terminal and a common terminal. The first terminal connected to a first electrode of the first power semiconductor element. The first gate terminal connected to a gate of the first power semiconductor element. The second terminal connected to a first electrode of the second power semiconductor element. The second gate terminal connected to a gate of the second power semiconductor element. The third terminal connected to a second electrode of the first power semiconductor element and a second electrode of the second power semiconductor element. The common terminal that is connected to the first gate terminal through a first resistor and is connected to the second gate terminal through a second resistor.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: November 29, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tadahiko Sato
  • Patent number: 11515841
    Abstract: A dc coupled amplifier includes a pre-driver, and amplifier and a bias control circuit. The pre-driver is configured to receive one or more input signals and amplify the one or more input signals to create one or more pre-amplified signals. The amplifier has cascode configured transistors configured to receive and amplify the one or more pre-amplified signals to create one or more amplified signals, the amplifier further having an output driver termination element. The bias control circuit is connected between the pre-driver and the amplifier, the bias control circuit receiving at least one bias current from the output driver termination element of the amplifier, wherein the pre-driver, the amplifier and the bias control circuit are all formed on a same die.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: November 29, 2022
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Wayne Kennan, Baotoan Nguyen
  • Patent number: 11509270
    Abstract: Systems, methods and apparatus for practical realization of an integrated circuit comprising a stack of transistors operating as an RF amplifier are described. As stack height is increased, capacitance values of gate capacitors used to provide a desired distribution of an RF voltage at the output of the amplifier across the stack may decrease to values approaching parasitic/stray capacitance values present in the integrated circuit which may render the practical realization of the integrated circuit difficult. Coupling of an RF gate voltage at the gate of one transistor of the stack to a gate of a different transistor of the stack can allow for an increase in the capacitance value of the gate capacitor of the different transistor for obtaining an RF voltage at the gate of the different transistor according to the desired distribution.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: November 22, 2022
    Assignee: pSemi Corporation
    Inventor: Jaroslaw Adamski
  • Patent number: 11502653
    Abstract: A power amplifier module can be formed that includes metamaterial matching circuits. This power amplifier module can be included as part of a front-end module of a wireless device. The front-end module can replace a passive duplexer with an active duplexer that uses the power amplifier module in combination with a low noise amplifier circuit that can include a metamaterial matching circuit. The combination of PA and LNA circuits that utilize metamaterials can provide the functionality of a duplexer without including a stand-alone or passive duplexer. Thus, in certain cases, the front-end module can provide duplexer functionality without including a separate duplexer. Advantageously, in certain cases, the size of the front-end module can be reduced by eliminating the passive duplexer. Further, the loss introduced into the signal path by the passive duplexer is eliminated improving the performance of the communication system that includes the active duplexer.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: November 15, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventor: Hanseung Lee
  • Patent number: 11482501
    Abstract: Example embodiments relate to amplifiers having improved stability.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: October 25, 2022
    Assignee: Ampleon Netherlands B.V.
    Inventors: Yi Zhu, Josephus Henricus Bartholomeus Van Der Zanden, Rob Mathijs Heeres
  • Patent number: 11451202
    Abstract: A signal output circuit includes an inverting amplifier circuit, a feedback capacitor and a low pass filter. The inverting amplifier circuit includes an input terminal and an output terminal. The inverting amplifier circuit executes an inverting amplification based on an input signal to output a signal to the output terminal at a pull-up state. An output stage of the inverting amplifier circuit is an open collector or an open drain. The feedback capacitor is connected between the input terminal and the output terminal of the inverting amplifier circuit. The low pass filter has an input and an output. The input of the low pass filter is connected to the output terminal of the inverting amplifier. The output of the low pass filter is connected to the feedback capacitor.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: September 20, 2022
    Assignee: DENSO CORPORATION
    Inventor: Takahisa Koyasu
  • Patent number: 11431311
    Abstract: A variable gain amplifier and an electronic apparatus. The variable gain amplifier includes a first transconductance stage circuit and a second transconductance stage circuit, where the first transconductance stage circuit includes a first amplifying circuit and a second amplifying circuit, the second transconductance stage circuit includes a third amplifying circuit and a fourth amplifying circuit, the first amplifying circuit and the fourth amplifying circuit form a differential input pair, and the second amplifying circuit and the third amplifying circuit form a differential input pair, and where each amplifying circuit of the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit includes a plurality of parallel transistors, and bias control of the plurality of transistors is independent of each other.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: August 30, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Cheng Yuan, Rong Peng, Qingyou Zheng
  • Patent number: 11329613
    Abstract: An amplifier, including: an amplifying element, having a voltage input across a first terminal and a third terminal and a voltage controlled current path between a second terminal and the third terminal; and a trifilar transformer having a primary winding, a secondary winding and a tertiary winding; wherein the primary winding is connected to the third terminal, the secondary winding is connected to the first terminal and the tertiary winding is connected to the second terminal; wherein the primary winding and the secondary winding are mutually coupled in inverting relationship; wherein the primary winding and the tertiary winding are mutually coupled in non-inverting relationship; wherein the secondary winding and the tertiary winding are mutually coupled in inverting relationship; and wherein the tertiary winding is between the amplifier output and the second terminal.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: May 10, 2022
    Assignee: NOVELDA AS
    Inventor: Sumit Bagga
  • Patent number: 11323080
    Abstract: An amplification circuit includes: an amplifier including a transistor that is connected between an input terminal and an output terminal; an input matching network that is connected between the input terminal and an input side of the amplifier and converts an impedance from a low impedance to a high impedance; a limiter circuit that is connected between a node between the input matching network and the input side of the amplifier, and ground and includes two diodes connected in opposite directions to each other; and a capacitor that is connected in series with the limiter circuit between the node and ground.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: May 3, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Masamichi Tokuda
  • Patent number: 11323079
    Abstract: Certain aspects of the present disclosure are directed to an amplifier. The amplifier may include a transistor coupled to an output of the amplifier, and a resonator coupled between the output of the amplifier and a reference potential node, a resonant frequency of the resonator being set to be at a subharmonic of a fundamental frequency of the amplifier, and an impedance of the resonator being greater than a load impedance of the amplifier at the fundamental frequency of the amplifier.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: May 3, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Jing-Hwa Chen, Junzhi Yu, Yan Kit Gary Hau, Guoqing Fu, Xinwei Wang, Xiangdong Zhang
  • Patent number: 11283409
    Abstract: In certain aspects, a receiver includes first amplifiers, wherein each one of the first amplifiers comprises an input and an output. The receiver also includes second amplifiers, wherein each one of the second amplifiers comprises an input and an output, and the outputs of the second amplifiers are coupled to a combining node. The receiver also includes transmission lines, wherein each one of the transmission lines is coupled between the output of a respective one of the first amplifiers and the input of a respective one of the second amplifiers. The receiver further includes a load coupled to the combining node, and receiver elements, wherein each one of the receiver elements comprises an input and an output, and the output of each one of the receiver elements is coupled to the input of a respective one of the first amplifiers.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: March 22, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Lai Kan Leung, Xinmin Yu, Chirag Dipak Patel, Rajagopalan Rangarajan
  • Patent number: 11228281
    Abstract: A calibration apparatus is used for calibrating characteristics of a power amplifier (PA) in a transmitter. The calibration apparatus includes an adaptive bias generator circuit that is used to track an envelope of an input signal received by control terminals of transistors of the PA and generate an adaptive bias voltage to the control terminals of the input transistors in response to the envelope of the input signal.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: January 18, 2022
    Assignee: MEDIATEK INC.
    Inventors: Yu-Hsien Chang, Yu-Ming Lai, Ching-Chia Cheng, Wei-Kai Hong, Yi-Chu Chen, Tsung-Ming Chen, Shih-Chieh Yen
  • Patent number: 11223331
    Abstract: An amplifier includes a Field Effect Transistor (FET) or a Bipolar Junction Transistor (BJT) with “hard saturation.”; where the FET or the BJT to has a nearly constant drain or collector current when the drain or collector voltage is greater than the pinchoff voltage. The amplifier further includes a bias network, configured to provide a DC voltage to the FET or the BJT, a means for isolating the DC voltage from the matching network, an electrical load, and a matching network which transforms the electrical load to a resistance between the drain and the source or the collector and emitter which causes the drain or collector voltage to be greater than the pinchoff voltage over the entire cycle of the sinusoidal voltage applied to the gate, whereby the amplifier is linear.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: January 11, 2022
    Inventor: Alfred Ira Grayzel
  • Patent number: 11196412
    Abstract: Apparatus and associated methods relate to an input buffer having a source follower connected in series with a push-pull driver to generate a shield reference node that provides conductive traces extending from the shield reference node and disposed between gate traces of the input buffer and a corresponding nearest reference potential node. In an illustrative example, the push-pull driver and the source follower may be capacitively coupled, via the gate traces, to receive an input signal from an input node. In some examples, the shield reference node may also include conductive traces disposed between the input node and/or the gate traces and a corresponding nearest reference potential node such that parts of parasitic capacitances in the input buffer may be shielded. Accordingly, the bandwidth of the input buffer may be advantageously improved. The high frequency return loss (S11) may also be improved accordingly.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: December 7, 2021
    Assignee: XILINX, INC.
    Inventors: Roswald Francis, Bruno Miguel Vaz
  • Patent number: 11183984
    Abstract: Variable-phase amplifier circuits and devices. In some embodiments, an amplifier can include a variable-gain stage having a plurality of switchable amplification branches, with each being capable of being activated, such that a combination of one or more activated amplification branches provides respective gain level and phase shift. The plurality of switchable amplification branches can be configured such that the phase shift provided by each combination of one or more activated amplification branches compensates for a phase shift associated with the amplifier operating with the respective gain level of the variable-gain stage.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: November 23, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Junhyung Lee, Johannes Jacobus Emile Maria Hageraats, Joshua Haeseok Cho
  • Patent number: 11176983
    Abstract: Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a magnetic tunnel junction (MTJ); and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the MTJ. An asynchronous, delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The asynchronous, delay-sensing element is configured to sense a timing delay between a first rising or falling edge voltage on the active current path and a second rising or falling edge voltage on the reference current path. The asynchronous, delay-sensing element is further configured to determine a data state stored in the MTJ based on the timing delay.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jack Liu, Charles Chew-Yuen Young
  • Patent number: 11171663
    Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a first plurality of digital-to-analog converter cells configured to generate a first analog signal. Further, digital-to-analog converter includes a second plurality of digital-to-analog converter cells configured to generate a second analog signal. The first analog signal and the second analog signal form a differential signal pair. Further, the digital-to-analog converter includes a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells, a second input node coupled to the second plurality of digital-to-analog converter cells, and a first output node. The transmission line transformer is configured to present a first impedance at the first and second input nodes and to present a second impedance at the first output node.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: November 9, 2021
    Assignee: Intel Corporation
    Inventors: Daniel Gruber, Ramon Sanchez, Kameran Azadet, Martin Clara
  • Patent number: 11139790
    Abstract: A distributed amplifier with low supply voltage and low power consumption is provided. The distributed amplifier includes an input terminal inputting an input signal; an output terminal outputting an output signal; an amplifier unit; a gate line circuit connected to the input terminal, a first load circuit and the amplifier unit; a second load circuit; a drain line circuit connected to the second load circuit, the amplifier unit and the output terminal; and a bias voltage circuit connected between the drain line circuit and the output terminal, wherein the bias voltage circuit includes a voltage source; an inductor connected to the voltage source and a terminal of the drain line circuit; and a capacitor multiplier connected to the inductor, the drain line circuit and the output terminal.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: October 5, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jie Zhang, Tai-Hsing Lee
  • Patent number: 11106229
    Abstract: A semiconductor integrated circuit includes an output transistor, an error amplifier, a replica transistor, a current-limiting circuit, and a potential regulation circuit. The output transistor is electrically connected between a power supply-side first node and an output-side second node. The replica transistor is electrically connected between the first node and a fourth node. The replica transistor constitutes a circuit that is configured to operate to correspond to the output transistor. The current-limiting circuit has an input node, that is electrically connected to a fifth node between the fourth node and a first current source, and an output node that is electrically connected to a gate of the output transistor and a gate of the replica transistor. The potential regulation circuit is electrically connected to the second node and the fourth node.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 31, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroyuki Ideno
  • Patent number: 11063586
    Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: July 13, 2021
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, Jerod F. Mason, David Scott Whitefield, Paul T. DiCarlo
  • Patent number: 11063562
    Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: July 13, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Rajendrakumar Joish
  • Patent number: 11055463
    Abstract: Systems and method are provided for automating design of an integrated circuit. In an embodiment, an integrated circuit design file is received that specifies logic elements. A plurality logic elements are identified that share a common input signal. A determination is made that the each of plurality of logic elements include a series of transistors. Upon said determining, the integrated circuit design is modified by identifying first and second transistors for a first of the logic elements, identifying first and second transistors for a second of the logic elements, deleting the second transistor of the second logic element, and routing an output of the first transistor of the second logic element to an input of the second transistor of the first logic element. The modified integrated circuit design is stored in a non-transitory computer-readable medium.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Guru Prasad, Osamu Takahashi, Yu Wang
  • Patent number: 11025209
    Abstract: A power amplifier layout can include multiple cascoded devices each having a radio-frequency transistor coupled to a cascode transistor. An orientation of a radio-frequency transistor of a first cascoded device relative to a cascode transistor of the first cascoded device can be configured to be different than an orientation of a radio-frequency transistor of a second cascoded device relative to a cascode transistor of the second cascoded device.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: June 1, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventor: Philip John Lehtola
  • Patent number: 11018643
    Abstract: A signal amplifier device is provided to ensure the continuity of the gain of an amplifier. The signal amplifier device includes a main path and a sub path connected in parallel to the main path. A main path first amplifier circuit amplifies an input signal on the main path. A main path second amplifier circuit includes a common-gate transistor connected in series with an output of the main path first amplifier circuit without sharing a DC current. On the main sub path, the sub path amplifier circuit amplifies the input signal by using a gain lower than the maximum gain in the main path.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: May 25, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Yoshikatsu Jingu
  • Patent number: 10998307
    Abstract: An analog signal buffer is disclosed. The analog signal buffer may include a transconductance cell and an active load. The active load may load the current from the transconductance cell with a PMOS transistor and an NMOS transistor and provide a feedback resistance. A transimpedance amplifier is disclosed. The transimpedance amplifier may include a first cell configured to receive a first signal and output a second signal and a second cell coupled to the first cell. The second cell may include an active feedback structure configured to couple an output of the second cell to an input of the second cell.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: May 4, 2021
    Assignee: Xilinx, Inc.
    Inventors: Kevin Zheng, Chuen-Huei Chou, Hsung Jai Im
  • Patent number: 10978411
    Abstract: An RF power package includes a substrate having a metallized part and an insulating part, an RF power transistor die embedded in or attached to the substrate, the RF power transistor die having a die input terminal, a die output terminal, an input impedance and an output impedance, a package input terminal formed in the metallized part or attached to the insulating part of the substrate, a package output terminal formed in the metallized part or attached to the insulating part of the substrate, and a first plurality of planar tuning lines formed in the metallized part of the substrate and electrically connecting the die output terminal to the package output terminal. The first plurality of planar tuning lines is shaped so as to transform the output impedance at the die output terminal to a higher target level at the package output terminal.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: April 13, 2021
    Assignee: Infineon Technologies AG
    Inventor: Michael Simcoe
  • Patent number: 10971494
    Abstract: A semiconductor device includes: element isolation regions; a projecting semiconductor region; a plurality of first gate electrodes each formed on both side surfaces and a top surface of a portion of the projecting semiconductor region, the plurality of first gate electrodes being formed between a pair of opposed end portions of the element isolation regions and being component elements of a plurality of transistors; at least one second gate electrode formed between the first gate electrodes, in the same layer as a layer where the plurality of first gate electrodes are formed, and applied with a voltage for turning off the transistor.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: April 6, 2021
    Assignee: SOCIONEXT, INC.
    Inventor: Masanori Yoshitani