Including Field Effect Transistor Patents (Class 330/277)
  • Patent number: 11329613
    Abstract: An amplifier, including: an amplifying element, having a voltage input across a first terminal and a third terminal and a voltage controlled current path between a second terminal and the third terminal; and a trifilar transformer having a primary winding, a secondary winding and a tertiary winding; wherein the primary winding is connected to the third terminal, the secondary winding is connected to the first terminal and the tertiary winding is connected to the second terminal; wherein the primary winding and the secondary winding are mutually coupled in inverting relationship; wherein the primary winding and the tertiary winding are mutually coupled in non-inverting relationship; wherein the secondary winding and the tertiary winding are mutually coupled in inverting relationship; and wherein the tertiary winding is between the amplifier output and the second terminal.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: May 10, 2022
    Assignee: NOVELDA AS
    Inventor: Sumit Bagga
  • Patent number: 11323079
    Abstract: Certain aspects of the present disclosure are directed to an amplifier. The amplifier may include a transistor coupled to an output of the amplifier, and a resonator coupled between the output of the amplifier and a reference potential node, a resonant frequency of the resonator being set to be at a subharmonic of a fundamental frequency of the amplifier, and an impedance of the resonator being greater than a load impedance of the amplifier at the fundamental frequency of the amplifier.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: May 3, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Jing-Hwa Chen, Junzhi Yu, Yan Kit Gary Hau, Guoqing Fu, Xinwei Wang, Xiangdong Zhang
  • Patent number: 11323080
    Abstract: An amplification circuit includes: an amplifier including a transistor that is connected between an input terminal and an output terminal; an input matching network that is connected between the input terminal and an input side of the amplifier and converts an impedance from a low impedance to a high impedance; a limiter circuit that is connected between a node between the input matching network and the input side of the amplifier, and ground and includes two diodes connected in opposite directions to each other; and a capacitor that is connected in series with the limiter circuit between the node and ground.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: May 3, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Masamichi Tokuda
  • Patent number: 11283409
    Abstract: In certain aspects, a receiver includes first amplifiers, wherein each one of the first amplifiers comprises an input and an output. The receiver also includes second amplifiers, wherein each one of the second amplifiers comprises an input and an output, and the outputs of the second amplifiers are coupled to a combining node. The receiver also includes transmission lines, wherein each one of the transmission lines is coupled between the output of a respective one of the first amplifiers and the input of a respective one of the second amplifiers. The receiver further includes a load coupled to the combining node, and receiver elements, wherein each one of the receiver elements comprises an input and an output, and the output of each one of the receiver elements is coupled to the input of a respective one of the first amplifiers.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: March 22, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Lai Kan Leung, Xinmin Yu, Chirag Dipak Patel, Rajagopalan Rangarajan
  • Patent number: 11228281
    Abstract: A calibration apparatus is used for calibrating characteristics of a power amplifier (PA) in a transmitter. The calibration apparatus includes an adaptive bias generator circuit that is used to track an envelope of an input signal received by control terminals of transistors of the PA and generate an adaptive bias voltage to the control terminals of the input transistors in response to the envelope of the input signal.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: January 18, 2022
    Assignee: MEDIATEK INC.
    Inventors: Yu-Hsien Chang, Yu-Ming Lai, Ching-Chia Cheng, Wei-Kai Hong, Yi-Chu Chen, Tsung-Ming Chen, Shih-Chieh Yen
  • Patent number: 11223331
    Abstract: An amplifier includes a Field Effect Transistor (FET) or a Bipolar Junction Transistor (BJT) with “hard saturation.”; where the FET or the BJT to has a nearly constant drain or collector current when the drain or collector voltage is greater than the pinchoff voltage. The amplifier further includes a bias network, configured to provide a DC voltage to the FET or the BJT, a means for isolating the DC voltage from the matching network, an electrical load, and a matching network which transforms the electrical load to a resistance between the drain and the source or the collector and emitter which causes the drain or collector voltage to be greater than the pinchoff voltage over the entire cycle of the sinusoidal voltage applied to the gate, whereby the amplifier is linear.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: January 11, 2022
    Inventor: Alfred Ira Grayzel
  • Patent number: 11196412
    Abstract: Apparatus and associated methods relate to an input buffer having a source follower connected in series with a push-pull driver to generate a shield reference node that provides conductive traces extending from the shield reference node and disposed between gate traces of the input buffer and a corresponding nearest reference potential node. In an illustrative example, the push-pull driver and the source follower may be capacitively coupled, via the gate traces, to receive an input signal from an input node. In some examples, the shield reference node may also include conductive traces disposed between the input node and/or the gate traces and a corresponding nearest reference potential node such that parts of parasitic capacitances in the input buffer may be shielded. Accordingly, the bandwidth of the input buffer may be advantageously improved. The high frequency return loss (S11) may also be improved accordingly.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: December 7, 2021
    Assignee: XILINX, INC.
    Inventors: Roswald Francis, Bruno Miguel Vaz
  • Patent number: 11183984
    Abstract: Variable-phase amplifier circuits and devices. In some embodiments, an amplifier can include a variable-gain stage having a plurality of switchable amplification branches, with each being capable of being activated, such that a combination of one or more activated amplification branches provides respective gain level and phase shift. The plurality of switchable amplification branches can be configured such that the phase shift provided by each combination of one or more activated amplification branches compensates for a phase shift associated with the amplifier operating with the respective gain level of the variable-gain stage.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: November 23, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Junhyung Lee, Johannes Jacobus Emile Maria Hageraats, Joshua Haeseok Cho
  • Patent number: 11176983
    Abstract: Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a magnetic tunnel junction (MTJ); and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the MTJ. An asynchronous, delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The asynchronous, delay-sensing element is configured to sense a timing delay between a first rising or falling edge voltage on the active current path and a second rising or falling edge voltage on the reference current path. The asynchronous, delay-sensing element is further configured to determine a data state stored in the MTJ based on the timing delay.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jack Liu, Charles Chew-Yuen Young
  • Patent number: 11171663
    Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a first plurality of digital-to-analog converter cells configured to generate a first analog signal. Further, digital-to-analog converter includes a second plurality of digital-to-analog converter cells configured to generate a second analog signal. The first analog signal and the second analog signal form a differential signal pair. Further, the digital-to-analog converter includes a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells, a second input node coupled to the second plurality of digital-to-analog converter cells, and a first output node. The transmission line transformer is configured to present a first impedance at the first and second input nodes and to present a second impedance at the first output node.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: November 9, 2021
    Assignee: Intel Corporation
    Inventors: Daniel Gruber, Ramon Sanchez, Kameran Azadet, Martin Clara
  • Patent number: 11139790
    Abstract: A distributed amplifier with low supply voltage and low power consumption is provided. The distributed amplifier includes an input terminal inputting an input signal; an output terminal outputting an output signal; an amplifier unit; a gate line circuit connected to the input terminal, a first load circuit and the amplifier unit; a second load circuit; a drain line circuit connected to the second load circuit, the amplifier unit and the output terminal; and a bias voltage circuit connected between the drain line circuit and the output terminal, wherein the bias voltage circuit includes a voltage source; an inductor connected to the voltage source and a terminal of the drain line circuit; and a capacitor multiplier connected to the inductor, the drain line circuit and the output terminal.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: October 5, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jie Zhang, Tai-Hsing Lee
  • Patent number: 11106229
    Abstract: A semiconductor integrated circuit includes an output transistor, an error amplifier, a replica transistor, a current-limiting circuit, and a potential regulation circuit. The output transistor is electrically connected between a power supply-side first node and an output-side second node. The replica transistor is electrically connected between the first node and a fourth node. The replica transistor constitutes a circuit that is configured to operate to correspond to the output transistor. The current-limiting circuit has an input node, that is electrically connected to a fifth node between the fourth node and a first current source, and an output node that is electrically connected to a gate of the output transistor and a gate of the replica transistor. The potential regulation circuit is electrically connected to the second node and the fourth node.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 31, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroyuki Ideno
  • Patent number: 11063562
    Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: July 13, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Rajendrakumar Joish
  • Patent number: 11063586
    Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: July 13, 2021
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, Jerod F. Mason, David Scott Whitefield, Paul T. DiCarlo
  • Patent number: 11055463
    Abstract: Systems and method are provided for automating design of an integrated circuit. In an embodiment, an integrated circuit design file is received that specifies logic elements. A plurality logic elements are identified that share a common input signal. A determination is made that the each of plurality of logic elements include a series of transistors. Upon said determining, the integrated circuit design is modified by identifying first and second transistors for a first of the logic elements, identifying first and second transistors for a second of the logic elements, deleting the second transistor of the second logic element, and routing an output of the first transistor of the second logic element to an input of the second transistor of the first logic element. The modified integrated circuit design is stored in a non-transitory computer-readable medium.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Guru Prasad, Osamu Takahashi, Yu Wang
  • Patent number: 11025209
    Abstract: A power amplifier layout can include multiple cascoded devices each having a radio-frequency transistor coupled to a cascode transistor. An orientation of a radio-frequency transistor of a first cascoded device relative to a cascode transistor of the first cascoded device can be configured to be different than an orientation of a radio-frequency transistor of a second cascoded device relative to a cascode transistor of the second cascoded device.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: June 1, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventor: Philip John Lehtola
  • Patent number: 11018643
    Abstract: A signal amplifier device is provided to ensure the continuity of the gain of an amplifier. The signal amplifier device includes a main path and a sub path connected in parallel to the main path. A main path first amplifier circuit amplifies an input signal on the main path. A main path second amplifier circuit includes a common-gate transistor connected in series with an output of the main path first amplifier circuit without sharing a DC current. On the main sub path, the sub path amplifier circuit amplifies the input signal by using a gain lower than the maximum gain in the main path.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: May 25, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Yoshikatsu Jingu
  • Patent number: 10998307
    Abstract: An analog signal buffer is disclosed. The analog signal buffer may include a transconductance cell and an active load. The active load may load the current from the transconductance cell with a PMOS transistor and an NMOS transistor and provide a feedback resistance. A transimpedance amplifier is disclosed. The transimpedance amplifier may include a first cell configured to receive a first signal and output a second signal and a second cell coupled to the first cell. The second cell may include an active feedback structure configured to couple an output of the second cell to an input of the second cell.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: May 4, 2021
    Assignee: Xilinx, Inc.
    Inventors: Kevin Zheng, Chuen-Huei Chou, Hsung Jai Im
  • Patent number: 10978411
    Abstract: An RF power package includes a substrate having a metallized part and an insulating part, an RF power transistor die embedded in or attached to the substrate, the RF power transistor die having a die input terminal, a die output terminal, an input impedance and an output impedance, a package input terminal formed in the metallized part or attached to the insulating part of the substrate, a package output terminal formed in the metallized part or attached to the insulating part of the substrate, and a first plurality of planar tuning lines formed in the metallized part of the substrate and electrically connecting the die output terminal to the package output terminal. The first plurality of planar tuning lines is shaped so as to transform the output impedance at the die output terminal to a higher target level at the package output terminal.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: April 13, 2021
    Assignee: Infineon Technologies AG
    Inventor: Michael Simcoe
  • Patent number: 10971494
    Abstract: A semiconductor device includes: element isolation regions; a projecting semiconductor region; a plurality of first gate electrodes each formed on both side surfaces and a top surface of a portion of the projecting semiconductor region, the plurality of first gate electrodes being formed between a pair of opposed end portions of the element isolation regions and being component elements of a plurality of transistors; at least one second gate electrode formed between the first gate electrodes, in the same layer as a layer where the plurality of first gate electrodes are formed, and applied with a voltage for turning off the transistor.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: April 6, 2021
    Assignee: SOCIONEXT, INC.
    Inventor: Masanori Yoshitani
  • Patent number: 10951169
    Abstract: An amplifier with two parallel coupled amplifier units with inverse characteristics and in particular to the parallel coupling of a sourcing limited amplifier unit and a sinking limited amplifier unit.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: March 16, 2021
    Assignee: Sonion Nederland B.V.
    Inventor: Adrianus Maria Lafort
  • Patent number: 10938350
    Abstract: A multi-mode envelope tracking (ET) target voltage circuit is provided. In an ET amplifier apparatus, an amplifier circuit is configured to amplify a radio frequency (RF) signal based on a time-variant ET voltage, which is generated based on a time-variant ET target voltage configured to track a time-variant power envelope of the RF signal. Notably, when the ET amplifier apparatus operates in a fifth-generation (5G) standalone (SA) or non-standalone (NSA) mode, the amplifier circuit may experience interference creating a reverse intermodulation product (rIMD) that can degrade efficiency and performance of the amplifier circuit. In examples discussed herein, the multi-mode ET target voltage circuit is configured to generate the ET target voltage based on a reduced slew rate to help suppress the rIMD at the amplifier circuit, thus making it possible to improve efficiency and performance of the ET amplifier apparatus in the SA and the NSA modes.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: March 2, 2021
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat
  • Patent number: 10931244
    Abstract: A common gate amplifier circuit configured to provide decreased voltage transients in the input voltage due to reverse gain. A second FET transistor is connected in series with a first FET of the common gate amplifier to function as an additional capacitive voltage divider between the amplifier output and the amplifier input without influencing the input or output currents. The first FET transistor, coupled to the amplifier input, may be a low voltage FET and smaller than the second FET transistor, which is coupled to the amplifier output. Both FET transistors are preferably enhancement mode GaN FET transistors and may be integrated into a single semiconductor chip with a single internal bias voltage divider.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: February 23, 2021
    Assignee: Efficient Power Conversion Corporation
    Inventors: John S. Glaser, Michael A. de Rooij
  • Patent number: 10931246
    Abstract: High-frequency amplifier circuitry has a common-source first transistor to amplify a high-frequency input signal, a common-gate second transistor to amplify a signal amplified by the first transistor to generate an output signal, a first inductor connected between a source of the first transistor and a first reference potential node, a second inductor connected between a drain of the second transistor and a second reference potential, a first switch to select whether to connect a first attenuator on an input signal path, a second switch to select whether to connect a first resistor between the input signal path and the first reference potential node, a third switch to select at least one of second resistors connected in parallel to the second inductor, and a fourth switch to select at least one of first capacitors connected in parallel on an output signal path connected to the drain of the second transistor.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: February 23, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Toshiki Seshita, Yasuhiko Kuriyama
  • Patent number: 10911002
    Abstract: A multistage power amplifier includes a first amplification circuit disposed in a front stage of the multistage power amplifier, a first bias circuit configured to output a first bias current, a bias path circuit, an envelope detection circuit, and an alternating current (AC) path circuit. The envelope detection circuit is configured to output a direct current (DC) detection voltage based on an envelope signal of a radio frequency (RF) signal input to the first amplification circuit. The AC path circuit is configured to branch an AC signal from an input terminal of the first amplification circuit and transfer the AC signal to the first bias circuit, upon the first amplification circuit operating in a high power driving region based on the DC detection voltage. The first bias circuit is configured to compensate for the first bias current based on the AC signal transferred through the AC path circuit.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: February 2, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Kyu Jin Choi
  • Patent number: 10903800
    Abstract: A power amplifier system having a power amplifier with a signal input and a signal output, bias circuitry coupled to the signal input, and a radio frequency (RF) peak detector having an input coupled to the signal output is disclosed. The RF peak detector is configured to generate a peak voltage signal. Temperature-compensated overvoltage protection circuitry coupled between an output of the RF peak detector and a control input of the bias circuitry is configured to respond to the peak voltage signal crossing over a predetermined peak voltage threshold and to provide an overvoltage protection control signal to cause the bias circuitry to adjust biasing for the power amplifier to reduce an overvoltage condition at the RF peak detector input.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: January 26, 2021
    Assignee: Qorvo US, Inc.
    Inventors: George Maxim, Stephen James Franck, Michael F. Zybura, Baker Scott
  • Patent number: 10886880
    Abstract: Apparatus and methods for LNAs with mid-node impedance networks are provided herein. In certain configurations, an LNA includes a mid-node impedance circuit including a resistor and a capacitor electrically connected in parallel, a cascode device electrically connected between an output terminal and the mid-node impedance circuit, and a transconductance device electrically connected between the mid-node impedance circuit and ground. The transconductance device amplifies a radio frequency signal received from an input terminal. The LNA further includes a feedback bias circuit electrically connected between the output terminal and the input terminal and operable to control an input bias voltage of the transconductance device.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: January 5, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventor: Engin Ibrahim Pehlivanoglu
  • Patent number: 10854259
    Abstract: Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a magnetic tunnel junction (MTJ); and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the MTJ. An asynchronous, delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The asynchronous, delay-sensing element is configured to sense a timing delay between a first rising or falling edge voltage on the active current path and a second rising or falling edge voltage on the reference current path. The asynchronous, delay-sensing element is further configured to determine a data state stored in the MTJ based on the timing delay.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jack Liu, Charles Chew-Yuen Young
  • Patent number: 10855231
    Abstract: A temperature compensation circuit for a radio frequency power amplifier includes: a temperature control circuit and a negative feedback circuit; the temperature control circuit is configured to generate a first electrical signal corresponding to a temperature, and according to the first electrical signal, adjust a second electrical signal at a first node; the negative feedback circuit is configured to provide, on the basis of the second electrical signal, a negative feedback signal to the radio frequency power amplifier by means of a second node; the second electrical signal is used to change the resistance value of the negative feedback circuit so as to adjust a negative feedback signal that is associated with the resistance value; the negative feedback signal is used to be inputted into the radio frequency power amplifier such that the gain of the radio frequency power amplifier changes.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: December 1, 2020
    Assignee: SMARTER MICROELECTRONICS (GUANG ZHOU) CO., LTD.
    Inventors: Qiang Su, Baiming Xu, Jiangtao Yl
  • Patent number: 10847629
    Abstract: A semiconductor device includes: a first transistor that includes a first gate stack; a second transistor that includes a second gate stack having a narrower width than the first gate stack; and a dummy gate stack disposed around the first gate stack and the second gate stack, wherein the dummy gate stack includes an oxygen sink layer for capturing oxygen atoms that are diffused from an exterior into the first gate stack and the second gate stack.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventor: Eun-Sung Lee
  • Patent number: 10840860
    Abstract: A device (100) for driving a self-conducting n-channel output stage field effect transistor (V1) comprising a control signal input (110), a control signal output (120) for connection to a gate electrode (V1G) of the output stage field effect transistor (V1), a first node (N1) connected to the control signal output (120), a second node (N2), and a first transistor (V4). A source electrode (V4S) of the first transistor (V4) is connected to the first node (N1), a gate electrode (V4G) of the first transistor (V4) is connected to the second node (N2) and a drain electrode (V4D) of the first transistor (V4) is either connected to the source electrode of the output field effect transistor (V1) or connected to a supply voltage (+Vdd). A resistor (R1) is connected with one end to the second node (N2). The device (100) is characterized in that the resistor (R1) is connected at the other end to the first node (N1).
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: November 17, 2020
    Assignee: FORSCHUNGSVERBUND BERLIN E.V.
    Inventor: Thomas Hoffmann
  • Patent number: 10826446
    Abstract: A power amplifier. The power amplifier includes a plurality of parallel coupled transistors. Each transistor has a control terminal coupled to receive a signal to be amplified and an output terminal coupled to a node. The power amplifier also includes a matching network having an input coupled to the node and an output coupleable to a load. The power amplifier further includes a first circuit branch forming a choke and harmonic trap of the power amplifier. The first circuit branch includes a first inductance, a second inductance and a first capacitor. The first inductance has a first terminal coupled to the node and a second terminal coupled to a first terminal of the second inductance. A second terminal of the second inductance is coupled to AC ground. The first capacitor is coupled in parallel with the second inductance.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: November 3, 2020
    Assignee: NXP B.V.
    Inventors: Amin Hamidian, Mark Pieter van der Heijden, Jozef Reinerus Maria Bergervoet
  • Patent number: 10784818
    Abstract: A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: September 22, 2020
    Assignee: pSemi Corporation
    Inventors: Simon Edward Willard, Chris Olson, Tero Tapio Ranta
  • Patent number: 10769511
    Abstract: Disclosed include methods and devices for enabling a battery free Bluetooth low energy communication. Some embodiments include a transmitter and a reference voltage generator supplying a voltage to an oscillator circuit. Further, some embodiments include an oscillator circuit including two pairs of semiconductor devices, wherein each pair of a semiconductor device includes a device with a gate node coupled to an antenna positive node interface (Vop) via a capacitor and a drain connected to an antenna negative node interface (Von) and a device with a gate node coupled to an antenna positive node interface (Von) via a capacitor and a drain connected to an antenna negative node interface (Vop). Additionally, some embodiments include an oscillator circuit connected to a common mode feedback circuit.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: September 8, 2020
    Assignee: Wiliot, Ltd
    Inventors: Sagi Kupferman, Alon Yehezkely
  • Patent number: 10771019
    Abstract: A radio frequency (RF) power transistor circuit includes a power transistor and at least one decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, and a current electrode for providing an RF output signal at an output terminal. A decoupling circuit is coupled between the control electrode and a ground terminal, and/or between the current electrode and the ground terminal. The decoupling circuit includes a resistor coupled in series with components of a resonant circuit having a resonance that is lower than an RF frequency (e.g., lower than 20 megahertz). The resistor is for dampening the resonance of the resonant circuit.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: September 8, 2020
    Assignee: NXP USA, Inc.
    Inventors: Hussain H. Ladhani, Gerard J. Bouisse, Jeffrey K. Jones
  • Patent number: 10763847
    Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FETs coupled in series and an auxiliary FET coupled in parallel with an interior FET of the plurality of main FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: September 1, 2020
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, Jerod F. Mason, David Scott Whitefield, Paul T. DiCarlo
  • Patent number: 10721552
    Abstract: A novel phantom-powered FET (field effect transistor) circuit for audio application is disclosed. In one embodiment of the invention, a novel phantom-powered FET preamplifier gain circuit can minimize undesirable sound distortions and reduce the cost of producing a conventional preamplifier gain circuit. Moreover, in one embodiment of the invention, one or more novel rounded-edge magnets may be placed close to a ribbon of a ribbon microphone, wherein the one or more novel rounded-edge magnets reduce or minimize reflected sound wave interferences with the vibration of the ribbon during an operation of the ribbon microphone. Furthermore, in one embodiment of the invention, a novel backwave chamber operatively connected to a backside of the ribbon can minimize acoustic pressure, anomalies in frequency responses, and undesirable phase cancellation and doubling effects.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: July 21, 2020
    Assignee: Cloud Microphones, LLC
    Inventors: Rodger Cloud, Stephen Sank
  • Patent number: 10715090
    Abstract: A bias circuit includes a replica circuit for an amplifier circuit using a cascode type inverter, and a generation circuit that generates a bias voltage that causes a drain voltage of an input stage transistor of the amplifier circuit to be a saturation drain voltage, based on an output voltage of the replica circuit, and supplies the generated bias voltage to a cascode element of the amplifier circuit and a cascode element of the replica circuit.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: July 14, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Yasufumi Sakai, Yoshiyasu Doi
  • Patent number: 10693516
    Abstract: An electronic device may include control circuitry, sensors, and wireless circuitry having antennas. The sensors may generate sensor data that is used by the control circuitry to identify an operating environment for the device. The sensor data may include a grip map generated by a touch-sensitive display, infrared facial recognition image signals or other image signals, an angle of arrival of sound received by a set of microphones, impedance data from an impedance sensor, and any other desired sensor data. The control circuitry may use the sensor data, radio-frequency spatial ranging data, information about whether audio is being played over an ear speaker, and/or information about communications protocols in use to identify the operating environment. The control circuitry may adjust antenna settings for the wireless circuitry based on the identified operating environment to ensure that the antennas operate with satisfactory antenna efficiency regardless of operating conditions.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: June 23, 2020
    Assignee: Apple Inc.
    Inventors: Liang Han, Matthew A. Mow, Mattia Pascolini, Ruben Caballero, Thomas E. Biedka, Yuancheng Xu, Iyappan Ramachandran
  • Patent number: 10666201
    Abstract: A power amplifier module includes a first power amplifier circuit configured to output a first amplified signal obtained by amplifying an input signal; a second power amplifier circuit configured to output a second amplified signal obtained by amplifying the first amplified signal; and a matching network connected between the first power amplifier circuit and the second power amplifier circuit. The matching network includes a first capacitor connected in series between the first power amplifier circuit and the second power amplifier circuit, a second capacitor connected in series between the first capacitor and the second power amplifier circuit, a first inductor connected between a point between the first capacitor and the second capacitor and a ground, and a second inductor connected in series between the first power amplifier circuit and the first capacitor.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: May 26, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hisanori Namie, Satoshi Goto, Satoshi Tanaka
  • Patent number: 10644659
    Abstract: A buffer amplifier comprises a source follower and a feedback amplifier. The feedback amplifier may be configured to control a drain current of the source follower to remain substantially constant independent of a load.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 5, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventors: Soo-Chang Choe, Craig S. Petrie
  • Patent number: 10620651
    Abstract: A metal oxide semiconductor field effect transistor (MOSFET) based voltage regulator circuit includes a first resistor, a second resistor, and a first MOSFET. A first gate terminal of the first MOSFET is connected to a second terminal of the first resistor and a first terminal of the second resistor. A first drain terminal of the first MOSFET is connected to a second terminal of the second resistor and a first output terminal of the voltage regulator circuit. The first MOSFET receives an input supply voltage at the first gate terminal of the first MOSFET, via the first resistor. The first MOSFET provides a first constant output voltage at the first output terminal based on a change in the input supply voltage.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: April 14, 2020
    Assignee: SONY CORPORATION
    Inventor: Bernard James Griffiths
  • Patent number: 10581399
    Abstract: The present invention is directed to an impedance matching network for use at a predetermined frequency.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: March 3, 2020
    Assignee: Anaren, Inc.
    Inventors: Chong Mei, Omar Eldaiki, Hans Peter Ostergaard
  • Patent number: 10574197
    Abstract: A first stabilizing circuit (7a) is disposed between a first transistor (5a) and a first output matching circuit (10a) in a first stage. A second stabilizing circuit (7b) is disposed between a second transistor (5b) and a second output matching circuit (10b) in a second stage. The first stabilizing circuit (7a) includes a first band-pass filter and a first resistor (103a) connected in parallel. The first band-pass filter allows a signal of a frequency f1 lower than a central frequency fc of the operation frequencies as an amplifier to pass through. The second stabilizing circuit (7b) includes a second band-pass filter and a second resistor (103b) connected in parallel. The second band-pass filter allows a signal of a frequency f2 higher than the central frequency fc to pass through.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: February 25, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takaaki Yoshioka, Shintaro Shinjo, Koji Yamanaka
  • Patent number: 10560060
    Abstract: The present disclosure relates to a power amplifier (PA) system provided in a semiconductor device and having feed forward gain control. The PA system comprises a transmit path and control circuitry. The transmit path is configured to amplify an input radio frequency (RF) signal and comprises a first tank circuit and a PA stage. The control circuitry is configured to detect a power level associated with the input RF signal and control a first bias signal provided to the PA stage based on a first function of the power level and control a quality factor (Q) of the first tank circuit based on a second function of the power level.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: February 11, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Stephen James Franck, Xin Wang, Alireza Oskoui
  • Patent number: 10554176
    Abstract: A power amplifier (100, 200, 500, 800, 1100) for amplifying an input signal into an output signal is disclosed. The power amplifier (100, 200, 500, 800, 1100) comprises an input port (110) for receiving the input signal and an output port (130) coupled to an output transmission line (140) for providing the output signal. The power amplifier (100, 200, 500, 800, 1100) further comprises multiple sets of sub-amplifiers (150, 160, 170, 180) distributed along the output transmission line, and inputs of the subamplifiers are coupled to the input port, outputs of the sub-amplifiers are coupled to the output transmission line. At least two different supply voltages are provided for the sub-amplifiers in the multiple sets of sub-amplifiers (150, 160, 170, 180).
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: February 4, 2020
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventor: Richard Hellberg
  • Patent number: 10530306
    Abstract: Hybrid power amplifier circuits, modules, or systems, and methods of operating same, are disclosed herein. In one example embodiment, a hybrid power amplifier circuit includes a preliminary stage amplification device, a final stage amplification device, and intermediate circuitry at least indirectly coupling the preliminary stage amplification device and the final stage amplification device. The intermediate circuitry includes a low-pass circuit and a high-pass circuit, and the hybrid power amplifier circuit is configured to amplify a first signal component at a fundamental frequency. Due at least in part to the intermediate circuitry, a phase of a second signal component at a harmonic frequency that is a multiple of the fundamental frequency is shifted.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: January 7, 2020
    Assignee: NXP USA, Inc.
    Inventors: Ramanujam Srinidhi Embar, Tushar Sharma, Joseph Staudinger
  • Patent number: 10511267
    Abstract: A multifinger transistor in which source fingers (201 to 206) and drain fingers (301 to 305) are arranged alternately with each of gate fingers (101 to 110) being sandwiched between one of the source fingers and one of the drain fingers is used. Line (10) and line (20) are attached to the source fingers (201 to 206) in an area on a gate side and causing a phase rotation such that the nearer to a central part a gate finger is, the more inductive the gate finger is.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: December 17, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuma Torii, Koji Yamanaka, Masaki Kono, Junichi Udomoto
  • Patent number: 10498329
    Abstract: Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in parallel with an auxiliary path. The circuit assembly also includes a first gate bias network connected to the main path. The circuit assembly also includes a second gate bias network connected to the auxiliary path, the second gate bias network configured to improve linearity of the switching function.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: December 3, 2019
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, Jerod F. Mason, David Scott Whitefield, Paul T. DiCarlo
  • Patent number: 10476447
    Abstract: A source follower with an input node and an output node includes a first transistor, a second transistor, and a DC (Direct Current) tracking circuit. The first transistor has a control terminal, a first terminal coupled to a first node, and a second terminal coupled to a second node. The second transistor has a control terminal, a first terminal coupled to a ground voltage, and a second terminal coupled to the first node. The DC tracking circuit sets the second DC voltage at the second node to a specific level. The specific level is determined according to the first DC voltage at the first node. The output node of the source follower is coupled to the first node.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: November 12, 2019
    Assignee: MEDIATEK INC.
    Inventor: Che-Hsun Kuo