Abstract: An amplifier with two parallel coupled amplifier units with inverse characteristics and in particular to the parallel coupling of a sourcing limited amplifier unit and a sinking limited amplifier unit.

Abstract: A multi-mode envelope tracking (ET) target voltage circuit is provided. In an ET amplifier apparatus, an amplifier circuit is configured to amplify a radio frequency (RF) signal based on a time-variant ET voltage, which is generated based on a time-variant ET target voltage configured to track a time-variant power envelope of the RF signal. Notably, when the ET amplifier apparatus operates in a fifth-generation (5G) standalone (SA) or non-standalone (NSA) mode, the amplifier circuit may experience interference creating a reverse intermodulation product (rIMD) that can degrade efficiency and performance of the amplifier circuit. In examples discussed herein, the multi-mode ET target voltage circuit is configured to generate the ET target voltage based on a reduced slew rate to help suppress the rIMD at the amplifier circuit, thus making it possible to improve efficiency and performance of the ET amplifier apparatus in the SA and the NSA modes.

Abstract: A common gate amplifier circuit configured to provide decreased voltage transients in the input voltage due to reverse gain. A second FET transistor is connected in series with a first FET of the common gate amplifier to function as an additional capacitive voltage divider between the amplifier output and the amplifier input without influencing the input or output currents. The first FET transistor, coupled to the amplifier input, may be a low voltage FET and smaller than the second FET transistor, which is coupled to the amplifier output. Both FET transistors are preferably enhancement mode GaN FET transistors and may be integrated into a single semiconductor chip with a single internal bias voltage divider.

Abstract: High-frequency amplifier circuitry has a common-source first transistor to amplify a high-frequency input signal, a common-gate second transistor to amplify a signal amplified by the first transistor to generate an output signal, a first inductor connected between a source of the first transistor and a first reference potential node, a second inductor connected between a drain of the second transistor and a second reference potential, a first switch to select whether to connect a first attenuator on an input signal path, a second switch to select whether to connect a first resistor between the input signal path and the first reference potential node, a third switch to select at least one of second resistors connected in parallel to the second inductor, and a fourth switch to select at least one of first capacitors connected in parallel on an output signal path connected to the drain of the second transistor.

Abstract: A multistage power amplifier includes a first amplification circuit disposed in a front stage of the multistage power amplifier, a first bias circuit configured to output a first bias current, a bias path circuit, an envelope detection circuit, and an alternating current (AC) path circuit. The envelope detection circuit is configured to output a direct current (DC) detection voltage based on an envelope signal of a radio frequency (RF) signal input to the first amplification circuit. The AC path circuit is configured to branch an AC signal from an input terminal of the first amplification circuit and transfer the AC signal to the first bias circuit, upon the first amplification circuit operating in a high power driving region based on the DC detection voltage. The first bias circuit is configured to compensate for the first bias current based on the AC signal transferred through the AC path circuit.

Abstract: A power amplifier system having a power amplifier with a signal input and a signal output, bias circuitry coupled to the signal input, and a radio frequency (RF) peak detector having an input coupled to the signal output is disclosed. The RF peak detector is configured to generate a peak voltage signal. Temperature-compensated overvoltage protection circuitry coupled between an output of the RF peak detector and a control input of the bias circuitry is configured to respond to the peak voltage signal crossing over a predetermined peak voltage threshold and to provide an overvoltage protection control signal to cause the bias circuitry to adjust biasing for the power amplifier to reduce an overvoltage condition at the RF peak detector input.

Abstract: Apparatus and methods for LNAs with mid-node impedance networks are provided herein. In certain configurations, an LNA includes a mid-node impedance circuit including a resistor and a capacitor electrically connected in parallel, a cascode device electrically connected between an output terminal and the mid-node impedance circuit, and a transconductance device electrically connected between the mid-node impedance circuit and ground. The transconductance device amplifies a radio frequency signal received from an input terminal. The LNA further includes a feedback bias circuit electrically connected between the output terminal and the input terminal and operable to control an input bias voltage of the transconductance device.

Abstract: A temperature compensation circuit for a radio frequency power amplifier includes: a temperature control circuit and a negative feedback circuit; the temperature control circuit is configured to generate a first electrical signal corresponding to a temperature, and according to the first electrical signal, adjust a second electrical signal at a first node; the negative feedback circuit is configured to provide, on the basis of the second electrical signal, a negative feedback signal to the radio frequency power amplifier by means of a second node; the second electrical signal is used to change the resistance value of the negative feedback circuit so as to adjust a negative feedback signal that is associated with the resistance value; the negative feedback signal is used to be inputted into the radio frequency power amplifier such that the gain of the radio frequency power amplifier changes.

Abstract: Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a magnetic tunnel junction (MTJ); and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the MTJ. An asynchronous, delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The asynchronous, delay-sensing element is configured to sense a timing delay between a first rising or falling edge voltage on the active current path and a second rising or falling edge voltage on the reference current path. The asynchronous, delay-sensing element is further configured to determine a data state stored in the MTJ based on the timing delay.

Abstract: A semiconductor device includes: a first transistor that includes a first gate stack; a second transistor that includes a second gate stack having a narrower width than the first gate stack; and a dummy gate stack disposed around the first gate stack and the second gate stack, wherein the dummy gate stack includes an oxygen sink layer for capturing oxygen atoms that are diffused from an exterior into the first gate stack and the second gate stack.

Abstract: A device (100) for driving a self-conducting n-channel output stage field effect transistor (V1) comprising a control signal input (110), a control signal output (120) for connection to a gate electrode (V1G) of the output stage field effect transistor (V1), a first node (N1) connected to the control signal output (120), a second node (N2), and a first transistor (V4). A source electrode (V4S) of the first transistor (V4) is connected to the first node (N1), a gate electrode (V4G) of the first transistor (V4) is connected to the second node (N2) and a drain electrode (V4D) of the first transistor (V4) is either connected to the source electrode of the output field effect transistor (V1) or connected to a supply voltage (+Vdd). A resistor (R1) is connected with one end to the second node (N2). The device (100) is characterized in that the resistor (R1) is connected at the other end to the first node (N1).

Abstract: A power amplifier. The power amplifier includes a plurality of parallel coupled transistors. Each transistor has a control terminal coupled to receive a signal to be amplified and an output terminal coupled to a node. The power amplifier also includes a matching network having an input coupled to the node and an output coupleable to a load. The power amplifier further includes a first circuit branch forming a choke and harmonic trap of the power amplifier. The first circuit branch includes a first inductance, a second inductance and a first capacitor. The first inductance has a first terminal coupled to the node and a second terminal coupled to a first terminal of the second inductance. A second terminal of the second inductance is coupled to AC ground. The first capacitor is coupled in parallel with the second inductance.

Abstract: A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.

Abstract: Disclosed include methods and devices for enabling a battery free Bluetooth low energy communication. Some embodiments include a transmitter and a reference voltage generator supplying a voltage to an oscillator circuit. Further, some embodiments include an oscillator circuit including two pairs of semiconductor devices, wherein each pair of a semiconductor device includes a device with a gate node coupled to an antenna positive node interface (Vop) via a capacitor and a drain connected to an antenna negative node interface (Von) and a device with a gate node coupled to an antenna positive node interface (Von) via a capacitor and a drain connected to an antenna negative node interface (Vop). Additionally, some embodiments include an oscillator circuit connected to a common mode feedback circuit.

Abstract: A radio frequency (RF) power transistor circuit includes a power transistor and at least one decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, and a current electrode for providing an RF output signal at an output terminal. A decoupling circuit is coupled between the control electrode and a ground terminal, and/or between the current electrode and the ground terminal. The decoupling circuit includes a resistor coupled in series with components of a resonant circuit having a resonance that is lower than an RF frequency (e.g., lower than 20 megahertz). The resistor is for dampening the resonance of the resonant circuit.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FETs coupled in series and an auxiliary FET coupled in parallel with an interior FET of the plurality of main FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: A novel phantom-powered FET (field effect transistor) circuit for audio application is disclosed. In one embodiment of the invention, a novel phantom-powered FET preamplifier gain circuit can minimize undesirable sound distortions and reduce the cost of producing a conventional preamplifier gain circuit. Moreover, in one embodiment of the invention, one or more novel rounded-edge magnets may be placed close to a ribbon of a ribbon microphone, wherein the one or more novel rounded-edge magnets reduce or minimize reflected sound wave interferences with the vibration of the ribbon during an operation of the ribbon microphone. Furthermore, in one embodiment of the invention, a novel backwave chamber operatively connected to a backside of the ribbon can minimize acoustic pressure, anomalies in frequency responses, and undesirable phase cancellation and doubling effects.

Abstract: A bias circuit includes a replica circuit for an amplifier circuit using a cascode type inverter, and a generation circuit that generates a bias voltage that causes a drain voltage of an input stage transistor of the amplifier circuit to be a saturation drain voltage, based on an output voltage of the replica circuit, and supplies the generated bias voltage to a cascode element of the amplifier circuit and a cascode element of the replica circuit.

Abstract: An electronic device may include control circuitry, sensors, and wireless circuitry having antennas. The sensors may generate sensor data that is used by the control circuitry to identify an operating environment for the device. The sensor data may include a grip map generated by a touch-sensitive display, infrared facial recognition image signals or other image signals, an angle of arrival of sound received by a set of microphones, impedance data from an impedance sensor, and any other desired sensor data. The control circuitry may use the sensor data, radio-frequency spatial ranging data, information about whether audio is being played over an ear speaker, and/or information about communications protocols in use to identify the operating environment. The control circuitry may adjust antenna settings for the wireless circuitry based on the identified operating environment to ensure that the antennas operate with satisfactory antenna efficiency regardless of operating conditions.

Abstract: A power amplifier module includes a first power amplifier circuit configured to output a first amplified signal obtained by amplifying an input signal; a second power amplifier circuit configured to output a second amplified signal obtained by amplifying the first amplified signal; and a matching network connected between the first power amplifier circuit and the second power amplifier circuit. The matching network includes a first capacitor connected in series between the first power amplifier circuit and the second power amplifier circuit, a second capacitor connected in series between the first capacitor and the second power amplifier circuit, a first inductor connected between a point between the first capacitor and the second capacitor and a ground, and a second inductor connected in series between the first power amplifier circuit and the first capacitor.

Abstract: A buffer amplifier comprises a source follower and a feedback amplifier. The feedback amplifier may be configured to control a drain current of the source follower to remain substantially constant independent of a load.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) based voltage regulator circuit includes a first resistor, a second resistor, and a first MOSFET. A first gate terminal of the first MOSFET is connected to a second terminal of the first resistor and a first terminal of the second resistor. A first drain terminal of the first MOSFET is connected to a second terminal of the second resistor and a first output terminal of the voltage regulator circuit. The first MOSFET receives an input supply voltage at the first gate terminal of the first MOSFET, via the first resistor. The first MOSFET provides a first constant output voltage at the first output terminal based on a change in the input supply voltage.

Abstract: The present invention is directed to an impedance matching network for use at a predetermined frequency.

Abstract: A first stabilizing circuit (7a) is disposed between a first transistor (5a) and a first output matching circuit (10a) in a first stage. A second stabilizing circuit (7b) is disposed between a second transistor (5b) and a second output matching circuit (10b) in a second stage. The first stabilizing circuit (7a) includes a first band-pass filter and a first resistor (103a) connected in parallel. The first band-pass filter allows a signal of a frequency f1 lower than a central frequency fc of the operation frequencies as an amplifier to pass through. The second stabilizing circuit (7b) includes a second band-pass filter and a second resistor (103b) connected in parallel. The second band-pass filter allows a signal of a frequency f2 higher than the central frequency fc to pass through.

Abstract: The present disclosure relates to a power amplifier (PA) system provided in a semiconductor device and having feed forward gain control. The PA system comprises a transmit path and control circuitry. The transmit path is configured to amplify an input radio frequency (RF) signal and comprises a first tank circuit and a PA stage. The control circuitry is configured to detect a power level associated with the input RF signal and control a first bias signal provided to the PA stage based on a first function of the power level and control a quality factor (Q) of the first tank circuit based on a second function of the power level.

Abstract: A power amplifier (100, 200, 500, 800, 1100) for amplifying an input signal into an output signal is disclosed. The power amplifier (100, 200, 500, 800, 1100) comprises an input port (110) for receiving the input signal and an output port (130) coupled to an output transmission line (140) for providing the output signal. The power amplifier (100, 200, 500, 800, 1100) further comprises multiple sets of sub-amplifiers (150, 160, 170, 180) distributed along the output transmission line, and inputs of the subamplifiers are coupled to the input port, outputs of the sub-amplifiers are coupled to the output transmission line. At least two different supply voltages are provided for the sub-amplifiers in the multiple sets of sub-amplifiers (150, 160, 170, 180).

Abstract: Hybrid power amplifier circuits, modules, or systems, and methods of operating same, are disclosed herein. In one example embodiment, a hybrid power amplifier circuit includes a preliminary stage amplification device, a final stage amplification device, and intermediate circuitry at least indirectly coupling the preliminary stage amplification device and the final stage amplification device. The intermediate circuitry includes a low-pass circuit and a high-pass circuit, and the hybrid power amplifier circuit is configured to amplify a first signal component at a fundamental frequency. Due at least in part to the intermediate circuitry, a phase of a second signal component at a harmonic frequency that is a multiple of the fundamental frequency is shifted.

Abstract: A multifinger transistor in which source fingers (201 to 206) and drain fingers (301 to 305) are arranged alternately with each of gate fingers (101 to 110) being sandwiched between one of the source fingers and one of the drain fingers is used. Line (10) and line (20) are attached to the source fingers (201 to 206) in an area on a gate side and causing a phase rotation such that the nearer to a central part a gate finger is, the more inductive the gate finger is.

Abstract: Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in parallel with an auxiliary path. The circuit assembly also includes a first gate bias network connected to the main path. The circuit assembly also includes a second gate bias network connected to the auxiliary path, the second gate bias network configured to improve linearity of the switching function.

Abstract: A source follower with an input node and an output node includes a first transistor, a second transistor, and a DC (Direct Current) tracking circuit. The first transistor has a control terminal, a first terminal coupled to a first node, and a second terminal coupled to a second node. The second transistor has a control terminal, a first terminal coupled to a ground voltage, and a second terminal coupled to the first node. The DC tracking circuit sets the second DC voltage at the second node to a specific level. The specific level is determined according to the first DC voltage at the first node. The output node of the source follower is coupled to the first node.

Abstract: A single-stage amplifier circuit includes first and second transistors (e.g., BJTs or FETs) connected in parallel between the amplifier's input and output nodes. The first and second transistors are configured differently using known fabrication techniques such that a (first) cutoff frequency of the first transistor is at least 1.5 times greater than a (second) cutoff frequency of the second transistor, and such that a ratio of the respective cutoff frequencies produces a significant cancellation of second derivative transconductance (Gm?) in the amplifier output signal, whereby the amplifier achieves significantly improved IIP3. Alternatively, the amplifier is configured using MOSFETs having respective different channel lengths to achieve the desired cutoff frequency ratio.

Abstract: According to some aspects, a circuit is provided comprising a plurality of Josephson junctions arranged in series in a loop, at least one magnetic element producing magnetic flux through the loop, a plurality of superconducting resonators, each resonator coupled to the loop between a different neighboring pair of Josephson junctions of the plurality of Josephson junctions, a plurality of ports, each port coupled to at least one of the plurality of resonators at ends of the resonators opposite to ends at which the resonators are coupled to the loop, and at least one controller configured to provide input energy to each of the plurality of ports that causes the circuit to function as a circulator between the plurality of ports.

Abstract: A low noise amplifier (LNA) device includes a first transistor on a semiconductor on insulator (SOI) layer. The first transistor includes a source region, a drain region, and a gate. The LNA device also includes a first-side gate contact coupled to the gate. The LNA device further includes a second-side source contact coupled to the source region. The LNA device also includes a second-side drain contact coupled to the drain region.

Abstract: An embodiment provides a variable gain amplifying method includes: on a signal path of a radio frequency input signal, amplifying a radio frequency input signal by a plurality of serially-coupled amplifiers; steering currents from the amplifiers and controlling respective gains of the amplifiers; performing gain match on the signal path of the radio frequency input signal; and performing phase compensation on the signal path of the radio frequency input signal. The signal path of the radio frequency input signal further has first and second phase variation trends which compensate each other.

Abstract: A device includes multiple ceramic capacitors and a current path structure. A first ceramic capacitor includes a first ceramic material between first and second electrodes. A second ceramic capacitor includes a second ceramic material between third and fourth electrodes. The second ceramic material has a higher Q than the first ceramic material. The current path structure includes a lateral conductor located between the first and second ceramic materials, and first and second vertical conductors that extend from first and second ends of the lateral conductor to a device surface. The device may be coupled to a substrate of a packaged RF amplifier device, which also includes a transistor. For example, the device may form a portion of an output impedance matching circuit coupled between a current carrying terminal of the transistor and an output lead of the RF amplifier device.

Abstract: A level shift regulator circuit comprises a level shift transistor (Mls) and an output transistor (Mreg) being arranged in series to the level shift transistor (Mls) in an output path (OP). The circuit comprises a feedback path (FP) being arranged between an input node (IN) of the output path (OP) and a gate connection of the output transistor (Mreg). A current splitter (CS) is provided to split a current of a current source (IS0) coupled to the input node (IN) to reduce the loop gain. A current mirror (CM) is arranged in series to the current splitter (CS) to reduce the signal current provided by the current splitter (CS) to the gate connection of the output transistor (Mreg) to further reduce the gain and to improve stability of the circuit. A first and second filter (F1, F2) may optionally be provided to improve the phase response.

Abstract: Apparatus and methods for a delay circuit are provided. In an example, a delay circuit can include a resistor configured to receive a compensation current, a capacitor configured to receive a charge current based on the compensation current, a first compensation circuit configured to provide a control signal, and a charge-current coupling circuit. The first compensation circuit can include an inverter circuit configured to track an inverter threshold voltage across process, voltage and temperature variations, wherein an output of the inverter circuit is directly coupled to an input of the inverter circuit, and an amplifier configured to receive the output of the inverter circuit an provide the control signal. The charge-current coupling circuit can be configured to receive the control signal and to provide the compensation current and the charge current.

Abstract: A driver circuit includes a first termination resistor and a distributed amplifier comprising a plurality of pairs of input transistors and comprising inductors coupled between each pair of input transistors. The driver circuit also includes a distributed current-mode level shifter coupled to the first termination resistor. The distributed current-mode level shifter includes a first plurality of inductors coupled in series between the first termination resistor and the distributed amplifier and a first plurality of capacitive devices. Each capacitive device is coupled to a power supply node and to a node interconnecting two of the series-coupled inductors.

Abstract: Aspects and examples described herein provide a radio-frequency switching circuit, switching device, and related methods. In one example, a radio-frequency switching device includes an input path configured to receive a radio-frequency signal, a plurality of output paths each configured to provide the radio-frequency signal, and a plurality of radio-frequency sub-networks each coupled to the input path and configured to direct the radio-frequency signal, each of the plurality of sub-networks including at least a first radio-frequency circuit having a first series of directly biased transistors, a second radio-frequency circuit having a second series of directly biased transistors, and a direct current blocking network interposed between the first radio-frequency circuit and the second radio-frequency circuit, each output path of the plurality corresponding to at least one of the plurality of radio-frequency sub-networks.

Abstract: A power amplifier includes a transistor operating in a range of frequencies from a lower operating frequency to a higher operating frequency to provide a relatively linear gain between the lower operating frequency and the higher operating frequency, an input transmission line circuit coupled to a gate terminal of the transistor, and an output transmission line circuit coupled to a drain terminal of the transistor. The input transmission line includes an inductor-capacitor (LC) circuit that resonates at a first resonant frequency equaled to or higher than the higher operating frequency. The output transmission line includes an inductor-capacitor-inductor (LCL) circuit and a capacitor-inductor-capacitor (CLC) circuit. The LCL circuit resonates at a second resonant frequency equaled to or lower than the lower operating frequency. The CLC circuit resonates at a third resonant frequency equaled to or higher than the higher operating frequency.

Abstract: Circuits, methods and devices are disclosed, related to fast turn-on of radio-frequency amplifiers. In some embodiments, a method for amplifying a radio-frequency signal includes providing an amplification path implemented to amplify an radio-frequency signal, where the amplification path includes a switch and an amplifier. In some embodiments, each of the switch and the amplifier are configured to be ON or OFF to thereby enable or disable the amplification path, respectively. In some embodiments, the method includes providing a compensation circuit coupled to the amplifier, where the compensation circuit is configured to compensate for a slow transition of the amplifier between its ON and OFF states resulting from a signal applied to the switch.

Abstract: The present disclosure provides a trans-impedance amplifier, comprising: an inverting amplifier circuit, having an input end and an output end. The input end is coupled to an optical diode and is used for accessing an input voltage signal, and the output end is used for outputting an amplified voltage signal. The inverting amplifier circuit comprises at least three sequentially-connected amplifier units. Each of the amplifier units comprises two mutually-coupled N-type transistors, wherein one N-type transistor is used for receiving an input voltage, and the other N-type transistor is used for receiving a DC voltage signal. A common connection end of the two N-type transistors is used for outputting an amplified voltage signal, and the N-type transistor used for receiving the DC voltage signal adopts a native NFET. The trans-impedance amplifier further comprises a feedback resistor coupled to the input end and the output end of the inverting amplifier circuit.

Abstract: A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.

Abstract: A novel microphone incorporates a phantom-powered JFET circuit for audio application. In one embodiment of the invention, a novel phantom-powered JFET preamplifier gain circuit can minimize undesirable sound distortions and reduce the cost of producing a conventional preamplifier gain circuit. Moreover, in one embodiment of the invention, one or more novel rounded-edge magnets may be placed close to a ribbon of a ribbon microphone, wherein the one or more novel rounded-edge magnets reduce or minimize reflected sound wave interferences with the vibration of the ribbon during an operation of the ribbon microphone. Furthermore, in one embodiment of the invention, a novel backwave chamber operatively connected to a backside of the ribbon can minimize acoustic pressure, anomalies in frequency responses, and undesirable phase cancellation and doubling effects.

Abstract: Power amplifier circuitry includes an amplifier stage, a non-linear compensation network, and non-linear compensation control circuitry. The amplifier stage includes an input and an output, and is configured to receive an input signal at the input and provide an amplified output signal at the output. The non-linear compensation network is coupled between the input and the output of the amplifier stage. The non-linear compensation control circuitry is coupled to the non-linear compensation network and one or more of the input and the output of the amplifier stage. The non-linear compensation control circuitry is configured to adjust a capacitance of the non-linear compensation network to cancel a parasitic capacitance associated with the amplifier stage and thus reduce AM-PM distortion.

Abstract: A differential amplifier comprises a first differential circuitry structure including a first part comprising at least one branch of transistors and a second part comprising at least one branch of transistors, and a second circuitry structure. The second circuitry structure has a first non-linear device and a second non-linear device. The non-linear devices each comprise a transistor having a control node connected to a differential output terminals of the differential amplifier. A common center node of the non-linear devices is connected to a control node of one of the transistors of each branch of the first part having a differential output terminal. Amplifier applications, communication devices and network nodes are also disclosed.

Abstract: Embodiments of the disclosure relate to calibrating a power amplifier. The power amplifier calibration circuit is configured to provide a plurality of bias signal combinations each including a respective first bias signal and a respective second bias signal to the power amplifier. Power amplifier performance parameters for each of the bias signal combinations can be measured and provided to a control circuit in the power amplifier calibration circuit. The control circuit is configured to rank the measured power amplifier performance parameters based on predefined ranking criteria and determines a selected bias signal combination that can optimize the power amplifier performance parameters of the power amplifier. As such, it is possible to calibrate the power amplifier to operate at a balanced performance level, thus helping to improve radio frequency (RF) coverage and performance of the remote unit in a wireless distribution system (WDS).

Abstract: A power amplifier includes a main amplifier, an auxiliary amplifier, and a control circuit. The main amplifier is configured to amplify input power, and the auxiliary amplifier is configured to amplify the input power when the input power exceeds a certain level. The control circuit, which is provided between a source of the main amplifier and a ground, is configured to control a source potential of the main amplifier so as to increase the source potential when the input power reaches at least a certain value.

Abstract: A system may include a radio frequency (RF) amplifier device that includes an input impedance matching network and first and second baseband decoupling circuits, which may remove intermodulation distortion products from signal energy input to the RF amplifier device at baseband frequencies. The input impedance matching network may act as a band-pass or low-pass filter. A gate bias voltage may be applied to the gate of a transistor in the RF amplifier device through one of the baseband decoupling circuits or, alternatively, at an input node of the RF amplifier device.

Abstract: This disclosure relates generally to continuous time linear equalization. In an example of a continuous time linear equalizer, a variable gain circuit includes transistors having gate nodes respectively as a first and a second input node. A first transimpedance circuit is connected between the first input node and a first output node. A second transimpedance circuit is connected between the second input node and a second output node. A source node of each of the first transistor and the second transistor are commonly connected to one another. In the same or another equalizer, output nodes of a first frequency peaking circuit are connected to input nodes of a second frequency peaking circuit. In such a same or another equalizer, an RC feedback circuit has tap-off nodes and summing nodes respectively connected at the output nodes of the first frequency peaking circuit.