Having Emitter Degeneration Patents (Class 330/283)
  • Patent number: 10020780
    Abstract: An amplifier including a first cascode circuit including a first transistor and a second transistor whose source or emitter is coupled to a drain or a collector of the first transistor, a second cascode circuit being a differential pair with the first cascode circuit, the second cascode circuit including a third transistor whose source or emitter is coupled to a source or an emitter of the first transistor and a fourth transistor whose source or emitter is coupled to a drain or collector of the third transistor, a first feedback path that couples between an output terminal of the third transistor and an input terminal of the first transistor, the first feedback path including a first capacitative element, and a second feedback path that couples between an output terminal of the first transistor and an input terminal of the third transistor, the second feedback path including a second capacitative element.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: July 10, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Toshihiro Shimura
  • Patent number: 9985592
    Abstract: A radio frequency (RF) power amplifier circuit includes an input and an output. A power amplifier transistor has a first terminal connected to the input, a second terminal connected to the output, and a third terminal defined by a degeneration inductance. A first capacitor is connected to the third terminal of the power amplifier transistor, along with a negative capacitance circuit connected in series with the first capacitor. The negative capacitance and the first capacitor define a series resonance at a predefined operating frequency band, which shunts the degeneration inductance of the third terminal.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: May 29, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventors: Oleksandr Gorbachov, Lisette L. Zhang, Lothar Musiol
  • Patent number: 9954493
    Abstract: A high-frequency semiconductor amplifier circuit includes a first transistor provided on a SOI (Silicon on Insulator) substrate having a grounded source, a second transistor provided on the SOI substrate and cascode-connected to the first transistor, and a bias generation circuit provided on the SOI substrate and generating a gate voltages for the first and second transistors, and a first voltage for a drain of the second transistor. The bias generation circuit sets the gate voltage of the first transistor to a voltage between a second voltage and a third voltage, wherein the gate voltage is smaller than a voltage between a drain-to-source voltage of the first transistor, and wherein the second voltage is a threshold voltage of the first transistor and the third voltage is a gate-to-source voltage at which a second derivative of a square root of the drain current with respect to the gate-to-source voltage becomes a maximum.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: April 24, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Seshita, Yasuhiko Kuriyama
  • Patent number: 9831838
    Abstract: A low noise amplifier includes a first input transistor coupled to an input signal and a second input transistor coupled to the input signal. The low noise amplifier also includes a first output transistor, coupled between the first input transistor and a first carrier aggregation load, configured to connect the first input transistor to the first carrier aggregation load. Additionally, the low noise amplifier includes a second output transistor, coupled between the first input transistor and a second carrier aggregation load, configured to connect the first input transistor to the second carrier aggregation load. Further, the low noise amplifier includes a third output transistor, coupled between the second input transistor and the second carrier aggregation load, configured to connect the second input transistor to the second carrier aggregation load. Also included are a method of operating a low noise amplifier and an extended carrier low noise amplifier.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: November 28, 2017
    Assignee: Nvidia Corporation
    Inventors: Sherif Abdelhalem, Frank Zhang, Abdellatif Bellaouar, Sherif Embabi
  • Patent number: 9608568
    Abstract: Disclosed are apparatuses and methods to overcome technology limitations to achieve linearity and efficiency performance suitable for practical wireless communications systems. In an embodiment, an amplifier is provided that superimposes the transconductance from a common source amplifier with inductor degeneration with the transconductance from a common source amplifier without degeneration. In an embodiment, an amplifier is provided having a feedback-balun-transformer that provides electro-magnetic coupling between primary, secondary, and negative feedback degeneration inductors and a differential to single-ended conversion output.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: March 28, 2017
    Assignee: Futurewei Technologies, Inc.
    Inventors: Yoonhyuk Ro, Xuya Qiu, Jamil Forrester
  • Patent number: 9461539
    Abstract: A voltage regulator includes a driving circuit, a feedback circuit, first and second control circuits and a resistor. The driving circuit is coupled to an input node and an output node and generates an output voltage at the output node from an input voltage at the input node. The feedback circuit is coupled to the output node and generates a feedback voltage based on the output voltage. The first control circuit is coupled to the feedback circuit and the driving circuit to control the output voltage based on the feedback voltage. The resistor has opposite first and second terminals. The first terminal of the resistor is coupled to the output node. The second control circuit is coupled to the second terminal of the output stage resistor and the feedback circuit to control the feedback voltage based on a regulated voltage at the second terminal of the resistor.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 4, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin, Tsung-Ching (Jim) Huang
  • Patent number: 9407215
    Abstract: Disclosed are circuits and methods related to low-noise amplifiers (LNAs) having improved linearity. In some embodiments, a radio-frequency (RF) amplifier circuit can include a first amplifying transistor configured to amplify an RF signal. The RF amplifier circuit can further include a switchable inductance circuit that couples the first amplifying transistor to a signal ground. The switchable inductance circuit can be configured to be capable of providing at least two different inductance values that yield different linearity levels for the RF amplifier circuit. A high linearity performance can be obtained with a higher inductance and a lower bias voltage, thereby reducing power consumption of the RF amplifier. Examples of methods and devices related to such an RF amplifier circuit are disclosed.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: August 2, 2016
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Bharatjeet Singh Gill
  • Patent number: 9397623
    Abstract: A transadmittance amplifier stage is coupled to a transimpedance amplifier stage to form a continuous time linear equalizer. The transadmittance amplifier stage has first and second gain paths and is configured to input a first signal and output a second signal. The first gain path is configured to provide a DC gain recovery and a first high frequency gain to the first signal. The second gain path is configured to provide a second high frequency gain to the first signal. The second signal is generated by the transadmittance amplifier stage based on the gain recovery of the first signal and the high frequency gains of the first signal. The transimpedance amplifier stage is configured to input the second signal from the transadmittance amplifier stage and convert the second signal to an output voltage signal.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: July 19, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Marc-Andre Lacroix
  • Patent number: 9374042
    Abstract: An embodiment described herein includes a low noise amplifier (LNA) including a plurality of separate input terminals, a plurality of transistors, and an output network coupled to a first reference terminal and a single output of the LNA. Each transistor includes a conduction path and a control terminal coupled to one of the plurality of separate input terminals. The output network is also coupled to the conduction path of each of the plurality of transistors.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: June 21, 2016
    Assignee: Infineon Technologies AG
    Inventors: Daniel Kehrer, Paulo Oliveira, Thomas Leitner
  • Patent number: 9231529
    Abstract: A low-noise amplifier is provided that includes an input amplifier stage coupled to a plurality of independently switchable output amplifier stages. The input amplifier stage is operative to amplify an input communications signal, and it provides both an amplified communications signal and a feedforward signal. The amplified communications signal and the feedforward signal both include a distortion component. Each of the switchable output stages is operative to provide an output that combines the feedforward signal with the amplified communications signal in such a way that the distortion components of the signals at least partially cancel one another. In some embodiments, the switching of the output amplifier stages is performed by circuitry that also serves to improve reverse isolation of the separate output amplifier stages.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: January 5, 2016
    Assignee: Motorola Solutions, Inc.
    Inventors: Shafiullah Syed, Jiun How Ng
  • Patent number: 9154087
    Abstract: Amplifiers with configurable mutually-coupled source degeneration inductors are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit) includes a gain transistor and a plurality of inductors, which may implement an amplifier. The gain transistor receives an input signal and provides an amplified signal. The plurality of inductors are mutually coupled, are coupled to the gain transistor, and provide a programmable source degeneration inductance for the gain transistor. The inductors may have a positive coupling coefficient and may provide a larger source degeneration inductance. Alternatively, the inductors may have a negative coupling coefficient and may provide a smaller source degeneration inductance.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: October 6, 2015
    Assignee: Qualcomm Incorporated
    Inventors: Zhang Jin, Ahmed A. Youssef, Li-Chung Chang
  • Patent number: 8912845
    Abstract: An integrated circuit includes a radio frequency (RF) amplifier having a trifilar transformer coupled to a gain device in two negative feedback paths. The trifilar transformer includes a first winding, a second winding and a third winding, a first dielectric core is disposed between the first winding and the second winding, and a second dielectric core is disposed between the second winding and the third winding. A first winding ratio between the first winding and the second winding combined with a second winding ratio between the second winding and the third winding affects a total gain of the RF amplifier. In a specific embodiment, the gain device is a transistor, the first winding is coupled to a base of the transistor, the second winding is coupled to a collector of the transistor, and the third winding is coupled to an emitter of the transistor.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: December 16, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Edward Perry Jordan
  • Publication number: 20140320207
    Abstract: Variable feedback architecture and control techniques for variable gain amplifiers (VGAs) concurrently maintain, across a wide range of VGA gain settings, minimal input and output impedance variations, a low noise figure, low rates of change in noise figure, high signal-to-noise ratio (SNR), high quality of service (QoS), low distortion, high and relatively constant output third order intercept point (i.e., IP3 or TOI). Variable feedback counteracts impedance variations caused by gain variations. Compared to conventional high performance VGAs, noise figure is lower (e.g. 3 dB lower at maximum gain and 12 dB lower at minimum gain) and relatively constant, IP3 is higher and relatively constant, small signal third order intermodulation signal (IM3) tone slope is relatively constant and input and output impedances are relatively constant. As gain decreases, the noise figure advantage is nearly dB per dB compared to conventional high performance VGAs.
    Type: Application
    Filed: April 25, 2013
    Publication date: October 30, 2014
    Inventors: Feng-Jung Huang, Jean-Marc Mourant
  • Patent number: 8797098
    Abstract: A method may include applying an input differential voltage to input terminals of an amplifier, a first input terminal coupled to a gate of a first transistor and a second input terminal coupled to a gate of a second transistor. The method may also include varying a gain of the amplifier by varying at least one of: a resistance of a first resistor, the first resistor coupled between a source of the first transistor and a source of the second transistor; and a resistance of a second resistor, the second resistor coupled between a source of a third transistor and a source of a fourth transistor; wherein: the third transistor is coupled at its drain to the drain of the first transistor; and the fourth transistor is coupled at its drain to the drain of the second transistor and a gate of the third transistor and coupled at its gate to the drain of the third transistor.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: August 5, 2014
    Assignee: Fujitsu Limited
    Inventors: Shuo-Chun Kao, Nikola Nedovic
  • Patent number: 8773204
    Abstract: Techniques for reducing undesired source degeneration inductance are disclosed. In an exemplary design, an apparatus includes first and second connections. The first connection includes a first parasitic inductance acting as a source degeneration inductance of an amplifier. The second connection includes a second parasitic inductance magnetically coupled to the first parasitic inductance to reduce the source degeneration inductance of the amplifier. The amplifier (e.g., a single-ended power amplifier) may be coupled to circuit ground via the first connection. An impedance matching circuit may be coupled to the amplifier and may include a circuit component coupled to circuit ground via the second connection. The first connection may be located sufficiently close to (e.g., within a predetermined distance of) the second connection in order to obtain the desired magnetic coupling between the first and second parasitic inductances.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: July 8, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Jose Cabanillas, Calogero D Presti, Norman L Frederick, Jr.
  • Patent number: 8729966
    Abstract: A variable gain amplifier circuit with a small-sized configuration can accurately adjust the gain without causing a transmission loss of an input signal. A plurality of amplification portions are connected with each other between an amplification coupling line and a grounding line in parallel. The amplification portion includes a switching device and an amplification transistor, which induces a current corresponding to an input signal to flow between the amplification coupling line and the grounding line via the switching device when the switching device is in the on state. The amplitude gain is varied by, according to a gain control signal, separately switching on and off the switching devices of the respective amplification portions.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: May 20, 2014
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Katsuyuki Takagi
  • Patent number: 8665059
    Abstract: An ultra wideband frequency compensated resistor and related methodologies for frequency compensation are disclosed. In exemplary configuration, a resistive layer is provided over a substrate, and a frequency compensating structure is provided over at least a portion of the resistive layer and separated therefrom by an insulative layer. In certain embodiments, the insulating layer may be an adhesive that may also be effective to secure a protective cover over the resistive material and supporting substrate. In selected embodiments, the frequency compensating structure corresponds to a plurality of conductive layers, one or more of which may be directly electrically connected to terminations for the resistive material while one or more of the conductive layers are not so connected.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: March 4, 2014
    Assignee: AVX Corporation
    Inventors: Gheorghe Korony, Kevin D. Christian
  • Patent number: 8629720
    Abstract: The disclosure relates to a driving method for obtaining a linear gain variation of a transconductance amplifier that includes a first differential transistor cell, with adjustment of a driving voltage value of a degenerative driving transistor of the transconductance amplifier The method includes generating an output current signal of a second differential cell corresponding to the first differential transistor cell of the transconductance amplifier, the output current signal having a linear relationship with a transconductance value of the second differential cell as the driving voltage varies; generating a reference current signal having a linear relationship with a differential input voltage; comparing the output current signal and the reference current signal for adjusting the driving voltage value; and modifying the transconductance value of the second differential cell up to a balance of the current signals.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: January 14, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Matteo Albertini, Daniele Ronchi, Sandro Rossi, Giulio Ricotti
  • Patent number: 8576008
    Abstract: An RF receiver is described comprising a common gate common source LNA with a variable resistor in the source of the common gate transistor, a variable resistor in the source of the common source transistor, and a variable resistor in the RF input. A Smart Gain Control varies the resistance in the resistors to produce linear amplification in the LNA while maintaining input matching. Further, a broad dynamic range RSSI is described that implements a feedback control loop to maintain signal power within a sensitivity range of the power detector in the RSSI.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: November 5, 2013
    Assignee: SiTune Corporation
    Inventors: Saeid Mehrmanesh, Vahid Mesgarpour Toosi
  • Patent number: 8514021
    Abstract: Embodiments of the invention are concerned with configurable RFICs. In an exemplary embodiment there is provided a configurable radio-frequency integrated circuit (RFIC) including one or more configurable low noise amplifier circuits, each of said one or more configurable low noise amplifier circuits being configurable between: an internal input impedance matching topology in which the respective low noise amplifier circuit includes one or more internal input impedance matching components adapted to match the input impedance of the respective low noise amplifier to a given input, said one or more internal input impedance matching components being located internally to the respective low noise amplifier circuit; and a topology different from said internal input impedance matching topology.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: August 20, 2013
    Assignee: Renesas Mobile Corporation
    Inventors: Jari Johannes Heikkinen, Jonne Juhani Riekki, Jouni Kristian Kaukovuori
  • Patent number: 8432217
    Abstract: A configurable low noise amplifier circuit which is configurable between a first topology in which the low noise amplifier circuit includes a degeneration inductance stage whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit includes a common-gate low noise amplifier stage whereby the low noise amplifier circuit operates as a common-gate low noise amplifier. The second topology includes one or more internal input impedance matching components and the first topology does not include the one or more internal input impedance matching components.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: April 30, 2013
    Assignee: Renesas Mobile Corporation
    Inventors: Jonne Juhani Riekki, Jari Johannes Heikkinen, Jouni Kristian Kaukovuori
  • Patent number: 8378748
    Abstract: The invention relates to a configurable low noise amplifier circuit which is configurable between a first topology in which the low noise amplifier circuit includes a degeneration inductance whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit includes a feedback resistance whereby the low noise amplifier circuit operates as a resistive feedback low noise amplifier.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: February 19, 2013
    Assignee: Renesas Mobile Corporation
    Inventors: Jari Johannes Heikkinen, Jonne Juhani Riekki, Jouni Kristian Kaukovuori
  • Patent number: 8324969
    Abstract: A variable gain amplifier device (100) with improved gain resolution is achieved. The device includes a programmable gain amplifier (PGA) (110), an analog-to-digital converter (ADC) (160), an automatic level control (ALC) algorithm means (176), and a delta-sigma modulator (180). The PGA (110) is capable to receive and to amplify an analog input signal (154) to thereby generate an analog output signal (164). The PGA (110) includes an amplifier (160) and a switchable resistor network (120). The ADC (170) is coupled to the PGA (110) and is capable to convert the analog output signal (164) to a digital signal (174). The ALC algorithm means (176) is coupled to the ADC (170) and is capable to generate a control code (178) by processing the digital signal (174). The delta-sigma modulator (186) is coupled to the ALC algorithm means (186) and is capable to generate a pulse-density modulated (PDM) signal (182) by processing the control code (178).
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: December 4, 2012
    Assignee: Dialog Semiconductor GmbH
    Inventors: Sebastian Loeda, Alisdair Muir
  • Patent number: 8319555
    Abstract: The invention relates to a configurable low noise amplifier circuit which is configurable between a first topology in which the low noise amplifier circuit includes a degeneration inductance whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit includes a feedback resistance whereby the low noise amplifier circuit operates as a resistive feedback low noise amplifier.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: November 27, 2012
    Assignee: Renesas Mobile Corporation
    Inventors: Jari Heikkinen, Jonne Riekki, Jouni Kaukovuori
  • Patent number: 8294515
    Abstract: A configurable low noise amplifier circuit which is configurable between a first topology in which the low noise amplifier circuit comprises a degeneration inductance stage whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit comprises a common-gate low noise amplifier stage whereby the low noise amplifier circuit operates as a common-gate low noise amplifier. The second topology comprises one or more internal input impedance matching components and the first topology does not comprise the one or more internal input impedance matching components.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: October 23, 2012
    Assignee: Renesas Mobile Corporation
    Inventors: Jonne Juhani Riekki, Jari Johannes Heikkinen, Jouni Kristian Kaukovuori
  • Patent number: 8264282
    Abstract: Embodiments provide a configurable low noise amplifier circuit including a gain stage coupled to the input of the low noise amplifier circuit, the low noise amplifier circuit being configurable between one of a first topology in which the low noise amplifier circuit includes a degeneration inductance whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit includes an impedance matching stage coupled to an input of the configurable low noise amplifier circuit, the output of the impedance matching stage providing an input bias voltage for the impedance matching stage, and a feedback stage coupled to an output of the impedance matching stage and a voltage source, the feedback stage providing a compensated operating voltage for the impedance matching stage.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: September 11, 2012
    Assignee: Renesas Mobile Corporation
    Inventors: Jonne Juhani Riekki, Jari Johannes Heikkinen, Jouni Kristian Kaukovuori
  • Patent number: 8258871
    Abstract: The invention relates to a configurable low noise amplifier circuit which is configurable between a first topology in which the low noise amplifier circuit includes a degeneration inductance whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit includes a feedback resistance whereby the low noise amplifier circuit operates as a resistive feedback low noise amplifier.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: September 4, 2012
    Assignee: Renesas Mobile Corporation
    Inventors: Jari Heikkinen, Jonne Riekki, Jouni Kaukovuori
  • Patent number: 8203388
    Abstract: An amplifier having multiple gain modes comprises a plurality of cascoded input transistors connected to an input and arranged in parallel, a degeneration stage connected to the input transistors and having a variable impedance, and switching means for switching between different modes of the amplifier by switching off one or more of the input transistors and varying the impedance of the degeneration stage.
    Type: Grant
    Filed: January 15, 2007
    Date of Patent: June 19, 2012
    Assignee: Future Waves UK Limited
    Inventors: Ganesh Kathiresan, Kritsapon Leelavattananon
  • Patent number: 8154343
    Abstract: A low-power high dynamic range RF input stage (200) with a noiseless degeneration component, such as a capacitor (201), is provided. High dynamic range means a combination of low noise contribution by the stage (200) and a low level of intermodulation products occurring especially at high input levels. Low power means that the power consumption of a conventional input stage is about 5 times higher than the power consumption of the stage according to the invention, for the same noise, gain and distortion level. This new stage can be used in amplifiers, but also in the lower stage of double balanced mixers (300-400) commonly used in RF receivers, examples of which are applications, are provided.
    Type: Grant
    Filed: January 16, 2006
    Date of Patent: April 10, 2012
    Assignee: NXP B.V.
    Inventors: Oswald Josef Moonen, Marc Lambertus Vlemmings, Arnold Hendrik Neelen
  • Patent number: 8102213
    Abstract: A multi-mode low noise amplifier (LNA) with transformer source degeneration is described. In an exemplary design, the multi-mode LNA includes first, second, and third transistors and first and second inductors. The first transistor has its source coupled to the first inductor, amplifies an input signal, and provides a first amplified signal in a first mode. The second transistor has its source coupled to the second inductor, amplifies the input signal, and provides a second amplified signal in a second mode. The third transistor has its source coupled to the second inductor. The first and third transistors receive the input signal and conduct current through the first and second inductors, respectively, in a third mode. The first transistor observes source degeneration from a transformer formed by the first and second inductors, amplifies the input signal, and provides a third amplified signal in the third mode.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: January 24, 2012
    Assignee: QUALCOMM, Incorporated
    Inventors: Aleksandar Tasic, Junxiong Deng, Zhang Jin
  • Patent number: 8031005
    Abstract: Techniques for designing a low-noise amplifier (LNA) for operation over a wide range of input power levels. In an exemplary embodiment, a first gain path is provided in parallel with a second gain path. The first gain path includes a differential cascode amplifier with inductor source degeneration. The second gain path includes a differential cascode amplifier without inductor source degeneration. The cascode transistors of the gain paths may be selectively biased to enable or disable the first and/or second gain path. By selectively biasing the cascode transistors and input transistors, various combinations of the first and second gain paths may be selected to provide an optimized gain configuration for any input power level.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: October 4, 2011
    Assignee: QUALCOMM, Incorporated
    Inventors: Zhijie Xiong, Harish S. Muthali
  • Patent number: 8008973
    Abstract: A transistor is provided to amplify a high frequency signal. A gate/base of the transistor receives the high frequency input signal. A variable capacitor is connected between the gate and a source/between the base and an emitter of the transistor. A variable inductor is connected with the source/the emitter of the transistor.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: August 30, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryuichi Fujimoto
  • Patent number: 7978011
    Abstract: Systems and methods which implement degeneration circuitry in a single-ended amplifier circuit to mitigate distortion associated with one or more amplifier components are disclosed. A degeneration circuit of embodiments adds an impedance to cancel the second-order distortion of an amplifier transistor of a single-ended amplifier circuit. A bias circuit may be provided to minimize bias offset between an amplifier transistor and a corresponding degeneration transistor.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: July 12, 2011
    Assignee: Zoran Corporation
    Inventor: Jan-Michael Stevenson
  • Patent number: 7969246
    Abstract: Systems and methods are provided for positive and negative feedback of cascode transistors for a power amplifier. The systems and methods may include a first cascode stage comprising a first common-source device and a first common-gate device; a second cascode stage comprising a second common-source device and a second common-gate device; a first degenerative element or block provided for the first common-source device; a second degenerative element or block provided for the second common-source device; a first positive feedback block or element that connects a first gate of the first common-source device with a second drain of the second common-source device; and a second positive feedback block or element that connects a second gate of the second common-source device with a first drain of the first common-source device.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: June 28, 2011
    Assignee: Samsung Electro-Mechanics Company
    Inventors: Kyu Hwan An, Yunseo Park, Chang-Ho Lee
  • Patent number: 7948319
    Abstract: One embodiment of the invention includes a current-mirror system. The system includes a current-mirror circuit configured to conduct an input current through a first current path that includes a first degeneration resistance device and to generate an output current that flows through a second current path that includes a second degeneration resistance device. The output current can be substantially proportional to the input current. The system also includes a degeneration control circuit configured to maintain a substantially constant degeneration voltage across each of the first and second degeneration resistance devices.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: May 24, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Rajarshi Mukophadhyay, Sharifi Reza
  • Patent number: 7948323
    Abstract: Various amplifier configurations having increased bandwidth, linearity, dynamic range, and less distortion are shown and disclosed. To increase bandwidth in a transimpedance amplifier, a replica circuit is created to replicate a degeneration resistance, or the resistance or value that relates to a feedback resistance. From the replica circuit, the replicated values are mirrored and processed to control a FET switch which modifies a degeneration resistance. The FET switch control signal is related to the feedback resistance and modifies the degeneration resistance to thereby maintain the product of the feedback resistance and the degeneration resistance as a constant. In another embodiment, a second switch controlled by an automatic gain control signal is established between a first stage amplifier and a second stage amplifier to improve dynamic range and bandwidth without degrading other amplifier specifications.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: May 24, 2011
    Assignee: Mindspeed Technologies, Inc.
    Inventors: Krishna Shivaram, Kashif A. Ahmed
  • Patent number: 7944287
    Abstract: A programmable offset amplifier includes first (M1) and second (M2) input transistors having differentially connected sources and gates coupled to first (Vin+) and second (Vin?) input voltages. A tail current (Itail1) is shared between the first and second input transistors. First (M3) and second (M4) load devices are coupled between a reference voltage and drains of the first and second input transistors, respectively. An output stage (13) has a first input (+) coupled to the drain of the second input transistor and a second input (?) coupled to the drain of the first input transistor. Programmable voltage changes are produced on input elements of programmable input offset circuitry to cause changes in offset voltages associated with electrodes of the input transistors which are reflected back to the amplifier input to provide a large programmable input-referred offset voltage.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: May 17, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Tony R. Larson, Dimitar T. Trifonov, Jerry L. Doorenbos
  • Patent number: 7944298
    Abstract: A differential low noise amplifier (LNA) involves two main amplifying transistors biased in saturation, and two cancel transistors biased in sub-threshold. In one example, the gates of the cancel transistors are coupled to the drains of main transistors, in a symmetrical and cross-coupled fashion. The main transistors are source degenerated. Because the gates of cancel transistors are not coupled to the differential input leads of the LNA, the input capacitance of the LNA is reduced. Noise introduced into the LNA output due to the cancel transistors being biased in the sub-threshold region is reduced because there are two stages. The first stage involves the main transistors, and the second stage involves the cancel transistors. By increasing the gain of the first stage and decreasing the gain of the second stage, overall LNA gain is maintained while reducing the noise that the sub-threshold biased transistors contribute to the LNA output.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: May 17, 2011
    Assignee: QUALCOMM, Incorporated
    Inventors: Jose Cabanillas, Prasad S. Gudem, Namsoo Kim, Cristian Marcu, Anup Savla
  • Patent number: 7902925
    Abstract: An amplifier, which has good linearity and noise performance, includes first, second, third, and fourth transistors and an inductor. The first and second transistors are coupled as a first cascode pair, and the third and fourth transistors are coupled as a second cascode pair. The third transistor has its gate coupled to the source of the second transistor, and the fourth transistor has its drain coupled to the drain of the second transistor. The first transistor provides signal amplification. The second transistor provides load isolation and generates an intermediate signal for the third transistor. The third transistor generates distortion components used to cancel third order distortion component generated by the first transistor. The inductor provides source degeneration for the first transistor and improves distortion cancellation. The sizes of the second and third transistors are selected to reduce gain loss and achieve good linearity for the amplifier.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: March 8, 2011
    Assignee: QUALCOMM, Incorporated
    Inventors: Namsoo Kim, Kenneth Charles Barnett, Vladimir Aparin
  • Patent number: 7847636
    Abstract: A low noise amplifier (LNA) for ultra wide band receives and amplifies identical RF signals in different frequency bands, and includes more than one pair of narrow band LNAs coupled in parallel, and a load circuit which increases load impedance of the entire circuit of the narrow band LNAs. The LNA can not only amplify the RF signal in the UWB but also obtain the low noise and the high gain that are features of the conventional narrow band LNA.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: December 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choong-yul Cha, Hoon-tae Kim, Sang-gug Lee
  • Publication number: 20100283542
    Abstract: Various amplifier configurations having increased bandwidth, linearity, dynamic range, and less distortion are shown and disclosed. To increase bandwidth in a transimpedance amplifier, a replica circuit is created to replicate a degeneration resistance, or the resistance or value that relates to a feedback resistance. From the replica circuit, the replicated values are mirrored and processed to control a FET switch which modifies a degeneration resistance. The FET switch control signal is related to the feedback resistance and modifies the degeneration resistance to thereby maintain the product of the feedback resistance and the degeneration resistance as a constant. In another embodiment, a second switch controlled by an automatic gain control signal is established between a first stage amplifier and a second stage amplifier to improve dynamic range and bandwidth without degrading other amplifier specifications.
    Type: Application
    Filed: May 6, 2009
    Publication date: November 11, 2010
    Inventors: Krishna Shivaram, Kashif A. Ahmed
  • Patent number: 7737785
    Abstract: An amplifier circuit has an amplifier element having an amplifier element input and an amplifier element input impedance, an amplification adjuster adapted to adjust an amplification of the amplifier element, an amplifier circuit input coupled to the amplifier element input, an impedance element having a alterable impedance value and being coupled to the amplifier circuit input, and an impedance adjuster adapted to adjust the impedance value of the impedance element as a function of the amplification of the amplifier element.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: June 15, 2010
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Thomas Stuecke, Niels Christoffers, Stephan Kolnsberg, Rainer Kokozinski
  • Patent number: 7705682
    Abstract: Two or more low noise amplifiers are configured to amplify received radio frequency input signals and one or more shared load or source degeneration inductors are configured to be used for each of the two or more low noise amplifiers. Further, the one or more shared inductors can be configured to be used for processing two or more signal bands in a multi-band communication system.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: April 27, 2010
    Assignee: NanoAmp Mobile, Inc.
    Inventors: Minzhan Gao, Ann P. Shen, Chien-Meen Hwang
  • Patent number: 7701288
    Abstract: Variable gain amplifiers with wider linear range are provided, in which first and second loads are coupled to a power voltage, and a transconductor cell comprises first and second transistors, a gain control transistor, and first and second current sources. The first and second transistors comprise control terminals receiving a set of input signals, first terminals coupled to the first and second loads respectively, and second terminal coupled to first and second nodes respectively. The first and second current sources are coupled between the first node and a first voltage and between the second node and the first voltage respectively. The first gain control transistor is coupled between the first node and second node, receiving a gain control voltage, in which the grain control transistor has a threshold voltage lower than that of the first and second transistors.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: April 20, 2010
    Assignee: Mediatek Inc.
    Inventors: Chun-Chih Hou, Wei-Hsuan Tu
  • Patent number: 7696828
    Abstract: A modified derivative superposition (MDS) low noise amplifier (LNA) includes a main current path and a cancel current path. Third-order distortion in the cancel path is used to cancel third-order distortion in the main path. In one novel aspect, there is a separate source degeneration inductor for each of the two current paths, thereby facilitating tuning of one current path without affecting the other current path. In a second novel aspect, a deboost current path is provided that does not pass through the LNA load. The deboost current allows negative feedback to be increased without generating headroom problems. In a third novel aspect, the cancel current path and/or deboost current path is programmably disabled to reduce power consumption and improve noise figure in operational modes that do not require high linearity.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: April 13, 2010
    Assignee: QUALCOMM, Incorporated
    Inventor: Li-Chung Chang
  • Patent number: 7667539
    Abstract: An improved low-voltage, low-power, wide range, and linear Gm Cell is disclosed. In one embodiment, a method of linearizing output current with an input voltage using a Gm Cell includes receiving an input differential voltage by an emitter degenerated input stage and outputting a current including a linear part and a nonlinear part at signal output terminals Iout_P and Iout_M, converting the non-linear part of the output current to a voltage difference via a compression stage, converting the voltage difference to a linear output current by a linear voltage to current converter stage, outputting the linear output current using a current mirror output stage to the signal output terminals Iout_P and Iout_M, and summing the output currents of the emitter degenerated input stage and the current mirror output stage at the signal output terminals Iout_P and Iout_M to obtain a linear output current with the input differential voltage.
    Type: Grant
    Filed: January 21, 2008
    Date of Patent: February 23, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Shengyuan Li
  • Patent number: 7626457
    Abstract: An Automatic Gain Control (AGC) module for controlling Noise Figure (NF) and IM characteristics therein is disclosed. The AGC module comprises a plurality of AGC stages. Each AGC stage comprises a differential amplifier circuit, an input signal transistor and a current-steering circuit. Differential amplifier circuits of the plurality of AGC stages receive control signals at their differential inputs and their output is connected to a common load. The input signal transistors of the plurality of AGC stages receive a common input signal and is further coupled to the differential amplifier circuit and the current-steering circuit. The current-steering circuits and the control signals at the differential amplifier circuits control gain of the each AGC stage of the plurality of AGC stage, which is used to control the NF and the IM characteristics.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: December 1, 2009
    Assignee: Intel Corporation
    Inventors: Mark Mudd, Isaac Ali, Ruiyan Zhao, Nick Cowley, Colin Perry, Richard Goldman
  • Patent number: 7616059
    Abstract: The invention relates to an differential amplifier circuit comprising an amplifier stage comprising a first and a second transistor, the gates of which are connected to differential input terminals of the amplifier stage. The differential amplifier further comprises a temperature compensation circuit comprising a third and fourth transistor. The third transistor is connected to the source of the first transistor and the fourth transistor is connected to the source of the second transistor. Further, the temperature compensation circuit comprises a constant current source connected to the respective sources of the third and fourth transistors. Thereby the temperature compensation circuit is arranged to provide a feedback resistance in dependence on the operating temperature so as to compensate for variations of the resistance of the first and second transistors.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: November 10, 2009
    Assignee: Infineon Technologies AG
    Inventors: Christian Grewing, Detlev Theil, Stefan Van Waasen
  • Patent number: 7616061
    Abstract: A low noise amplifier (LNA) for ultra wide band receives and amplifies identical RF signals in different frequency bands, and includes more than one pair of narrow band LNAs coupled in parallel, and a load circuit which increases load impedance of the entire circuit of the narrow band LNAs. The LNA can not only amplify the RF signal in the UWB but also obtain the low noise and the high gain that are features of the conventional narrow band LNA.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: November 10, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choong-yul Cha, Hoon-tae Kim, Sang-gug Lee
  • Publication number: 20090256634
    Abstract: An output distortion circuit includes a first transistor arrangement receiving a nonlinear current associated with a nonlinear differential error signal. The first transistor arrangement produces a reflected base current that is applied to one side of a differential input pair. A second transistor arrangement eliminates the nonlinear differential error signal by producing a replicated base current that replicates the reflected base current. The replicated base current is applied to an opposite side of the differential input pair thus the output distortion cancellation circuit creating a deflection of approximately equal magnitude to the reflected base current so as to eliminate the nonlinear differential error signal.
    Type: Application
    Filed: April 15, 2008
    Publication date: October 15, 2009
    Inventors: Moshe Gerstenhaber, James Bundock