Abstract: A multi-stage amplifier includes a first, a second, and a third sub-amplifier, each with respective input and output ports. The multi-stage amplifier also includes a common output port. The output port of the second sub-amplifier is connected to the output port of the first sub-amplifier as well as to the common output port of the multi-stage amplifier, and the output port of the third sub-amplifier is connected to the common output port. The electrical lengths of the connections from the second sub-amplifier's output port both to the first amplifier's output port and to the common output port are longer or shorter than one quarter of a wavelength (?) of the frequency for which the multi-stage amplifier is intended to operate.

Abstract: A high power amplifier architecture is disclosure. One example configuration includes a first plurality of distributed amplification stages operatively coupled in a first string. A conductive trace associated with the first string provides a stepped structure, such that the associated inductance successively decreases from input to output of the first string. A second plurality of distributed amplification stages is operatively coupled in a second string, and a conductive trace associated therewith provides a stepped structure, such that the associated inductance successively decreases from input to output of the second string. In one example case, each of the first and second strings comprises gallium nitride transistor amplification stages formed on silicon carbide. The module may further include a heat spreader material that thermally and electrically couples to the amplification stages. The conductive trace associated with one string can be shared with another string.

Abstract: A power amplifier device that satisfies both delivering a high output and reducing the chip area occupied by the power amplifier device. Over a substrate, are primary inductors arranged in a generally circular geometry, a ground pattern, transistor pairs, and a secondary inductor. The ground pattern extends from a portion of a region inside the circular primary inductor into regions outside the primary inductor, and grounded at a plurality of points in the regions outside the primary inductor. The primary inductors are coupled to the ground pattern through transistors.

Abstract: A circuit topology in accordance with a system, method and device for an active power splitter with an input and at least two outputs which allows the use of negative feedback and thus improving stability and linearity without substantially increasing the noise figure of the system is provided.

Abstract: The radio frequency power amplifier is connected between an other end of the first switching element and an other end of the second switching element, supplies power to a second amplifier via the first switching element and a second matching circuit, and includes a first power supply line for supplying power to the third amplifier via a second switching element and a third matching circuit, and the other end of the first switching element is connected to an input node of the first matching circuit, the other end of the second switching element is connected to the input node of the first matching circuit via the first power supply line, and an impedance of an output side of the RF power amplifier as viewed from an output node of the third amplifier is higher than an impedance of the RF power amplifier as viewed from an output node of the second amplifier.

Abstract: Doherty and distributed amplifier (DA) designs are combined to achieve, wideband amplifiers with high efficiency dynamic range. A modified Doherty amplifier includes a wideband phase shifter providing first and second outputs, a main amplifier coupled to the first output, an auxiliary amplifier coupled to the second output, and a wideband combining network combining the outputs in phase. A multi-stage DA has a main output and a termination port, and a phase delay module and transforming network allowing power at the termination port to be combined in phase with power at the main output. In one combination, one or more stages of the DA may comprise a Doherty amplifier. In another combination, a modified series-type Doherty amplifying system is achieved by cascading main and auxiliary DAs. In any combination, Doherty topology may include a bias control module.

Abstract: A power amplifier using N-way Doherty structure with adaptive bias supply power tracking for extending the efficiency region over the high peak-to-average power ratio of the multiplexing modulated signals such as wideband code division multiple access and orthogonal frequency division multiplexing is disclosed. In an embodiment, the present invention uses a dual-feed distributed structure to an N-way Doherty amplifier to improve the isolation between at least one main amplifier and at least one peaking amplifier and, and also to improve both gain and efficiency performance at high output back-off power. Hybrid couplers can be used at either or both of the input and output. In at least some implementations, circuit space is also conserved due to the integration of amplification, power splitting and combining.

Abstract: A Doherty amplifier includes a first amplifier, a second amplifier, a transmission line, a synthesizer, and an output load. The first amplifier amplifies an RF input signal according to a voltage applied to a supply terminal thereof. The second amplifier amplifies a peak component of the RF input signal according to a voltage applied to a supply terminal thereof. The transmission line is coupled to an output terminal of the first amplifier. The synthesizer is coupled to an output terminal of the transmission line and an output terminal of the second amplifier. It is set such that the voltage applied to the supply terminal of the first amplifier is lower than the voltage applied to the supply terminal of the second amplifier, and that an impedance value of the transmission line is smaller than a value twice an impedance value of the output load.

Abstract: Method for setup of parameter values in a RF power amplifier circuit arrangement (200), wherein the amplifier circuit arrangement (200) comprises a first (210) and a second (220) amplification branch and is operated in an out-phasing configuration for amplification of RF input signals with modulated amplitude and modulated phase and respective circuit arrangements are disclosed. According to a first aspect a re-optimization of the dead-time or conversely the duty-cycle, respectively, the phase of the output signal after the combiner can be kept linear with respect to the out-phasing angle. Further, according to a second aspect, additionally to introduction of an optimally chosen dead-time, a non-coherent combiner (Lx, Lx*) can reduce crowbar current and switching losses due the output capacitance (Cds). Furthermore, according to a third aspect the reactive compensation can, additionally or alternatively, be controlled by operating both amplification branches at different duty-cycles.

Abstract: A method for cancelling magnetic coupling in an amplifier is disclosed. The amplifier includes a first path and a second path for outputting a first signal and a second signal, respectively, and the first signal and the second signal have a specific phase difference. The method includes forming a first LC tank and a second LC tank in the first path, and forming a third LC tank and a forth LC tank in the second path.

Abstract: There is a need to provide a high-frequency power amplifier capable of reducing a talk current and reducing a phase deviation in output. The high-frequency power amplifier includes differently sized first through fifth power amplification transistors and impedance matching circuits for example. The high-frequency power amplifier changes a signal path to be used in accordance with a power specification signal. The high-frequency power amplifier uses a signal path from the first transistor to the second transistor in high power mode. The high-frequency power amplifier uses a signal path from the first transistor to the third transistor in medium power mode. The high-frequency power amplifier uses a signal path from the fourth transistor to the fifth transistor in low power mode. The high-frequency power amplifier is configured so that each of the signal paths includes the same number of stages of power amplification transistors and impedance matching circuits.

Abstract: An amplifier is realized by a distributed-constant-type amplifier including an input-side transmission line and an output-side transmission line, and a plurality of unit circuits coupled between the input-side transmission line and the output-side transmission line, in which each of the plurality of unit circuits is formed by including an amplification circuit having a gain equal to or greater than one.

Abstract: Various aspects of the disclosure provide high power and high efficiency power amplifier systems that can be integrated on a chip using integrated circuit processes such as a standard CMOS and SiGe process. A power amplifier system is disclosed according to one aspect. The power amplifier system comprises a first power amplifier, a Wilkinson power splitter, second-stage amplifiers, and a Wilkinson power combiner. The first power amplifier pre-amplifies an RF input signal. The Wilkinson power splitter then splits the power of the amplified RF signal outputted by the first power amplifier among the second-stage amplifiers. Each of the second-stage amplifiers amplifies the respective RF signal from the Wilkinson power splitter. The Wilkinson power combiner then sums the powers of the amplified RF signals outputted by the second-stage amplifiers and outputs the resulting combined RF signal.

Abstract: A three-stage GaN HEMT Doherty power amplifier for high frequency applications includes: a carrier amplifier; first and second peaking amplifier; a 10-dB power divider configured to divide an input signal to the carrier amplifier and the first and second peaking amplifiers; a first path for controlling input power of the carrier amplifier; and a second path for maintaining an efficiency of 40% or more in an output range of 40 dBm to 50 dBm.

Abstract: A combination amplifier (1,1a) is provided which comprises a carrier amplifier (7,7a) and a series connection of a first peak amplifier (9,9a) and a second peak amplifier (11,11a) which are provided with a phase-shifted input signal relative to the input signal supplied to the carrier amplifier, wherein a transfer characteristics of the combination amplifier may be optimized by independently adjusting transfer characteristics of the carrier amplifier, the first peak amplifier and the second peak amplifier. Thereby, a linearity and/or an efficiency of the combination amplifier may be improved compared to a conventional Doherty amplifier.

Abstract: A semiconductor package device comprises a first amplifier block, at least one further amplifier block operably coupled in parallel with the first amplifier block between a common input and a common output, and at least one stabilization network operably coupled between a node of the first amplifier block and a corresponding node of the at least one further amplifier block. The at least one stabilization network comprises an inductance operably coupled between the corresponding nodes of the first and at least one further amplifier blocks, and a capacitance operably coupling a mid-point of the inductance to a ground plane.

Abstract: An integrated power combiner is disclosed. The power combiner includes a first circular geometry primary winding having one or more inductive elements, such as an active winding with one or more driver stages. A circular geometry secondary winding is disposed adjacent to the first primary winding, such as an active winding with one or more driver stages. A second circular geometry primary winding is disposed adjacent to the secondary winding and has one or more inductive elements. One or more connections are provided between one or more of the inductive elements of the first circular geometry primary winding and one or more of the inductive elements of the second circular geometry primary winding.

Abstract: There is provided a power amplifier capable of improving harmonics characteristics of an output signal of an amplifier circuit by compensating a phase of the output signal. A power amplifier according to an aspect of the invention may include: an amplification section having a plurality of amplification units each amplifying a radio frequency (RF) signal according to a gain being controlled; a phase correction section performing phase correction by removing harmonic components of respective output signals from the plurality of amplification units of the amplification section; and a coupling section coupling the respective output signals phase-corrected by the phase correction section.

Abstract: Aspects of the disclosure provide an amplifier. The amplifier includes a first path configured to generate a first current that has a first polarity third-order coefficient corresponding to an input signal, a swing adjustor configured to adjust a swing of the input signal, and a second path configured to generate a second current based on the swing-adjusted input signal. The second current has a second polarity third-order coefficient corresponding to the swing-adjusted input signal. The first current and the second current are combined to drive a load, such that a third-order inter-modulation (IM3) in the combined current is reduced. In addition, in a power amplifier example, parameters of the amplifier, such as a ratio of the swing adjustor, biases of transistors, a number of additional paths, are adjusted based on a detected power of the input signal, such that the IM3 reduction is achieved across a wide input power range.

Abstract: An amplifier having a Doherty-type architecture and a method for operation thereof are provided. The amplifier comprises a main amplifier path comprising a main amplifier, an auxiliary amplifier path comprising an auxiliary amplifier, and an signal preparation unit configured to develop a main amplifier input signal for the main amplifier path and an auxiliary amplifier input signal for the auxiliary amplifier path based on an amplifier input that is to be amplified and a transition threshold associated with the amplifier input. By driving the main and auxiliary amplifiers as a function of the transition threshold, the gain of the Doherty-type amplifier may be increased.

Abstract: According to an embodiment, a Doherty amplifier system has a first Doherty amplifier and a second Doherty amplifier. The first Doherty amplifier operates in a SISO communication mode and in a MIMO communication mode. The first Doherty amplifier comprises a first carrier amplifier and a first peak amplifier. The second Doherty amplifier operates in the MIMO communication mode but not operates in the SISO communication mode. The second Doherty amplifier comprises a second carrier amplifier and a second peak amplifier. A distance between the first carrier amplifier and the second carrier amplifier is less than any of a distance between any of the first carrier amplifier and the second peak amplifier and any of the first peak amplifier and the second peak amplifier. In the SISO communication mode, heat generated by the first Doherty amplifier is conducted to the second Doherty amplifier to warm up the second Doherty amplifier.

Abstract: A power amplifier includes an input module. The input module includes a transformer and is configured to receive a radio frequency signal and generate output signals. Impedance transformation modules each of which having an output impedance and configured to receive a respective one of the output signals from the transformer. Switch modules each of which comprising a transistor and connected to an output of one of the impedance transformation modules. The transistor has an input impedance and outputs an amplified signal. Each of the output impedances is mismatched relative to a respective one of the input impedances.

Abstract: Disclosed is a switching amplifier having an enhanced supply rejection. The switching amplifier comprises a digital modulator that provides a modulated signal. The switching amplifier further comprises a closed-loop analog driver that is coupled to the digital modulator. As disclosed, the closed-loop analog driver is configured to re-modulate a modulation signal that corresponds to the modulated signal. An output stage of the switching amplifier is driven by the re-modulated signal, thereby providing enhanced supply rejection. In one embodiment, the modulated signal is produced by a digital pulse-width modulator (PWM) circuit of a Class-D amplifier, and has a pulse rate substantially less than a clock rate of the digital PWM circuit. In one embodiment, the switching amplifier is implemented as an audio amplifier in a mobile communication device such as a cellular telephone.

Abstract: An output stage (1) for a digital RF transmitter is provided. The output stage comprises: an input adapted to receive an input signal (RFin, b7-b0) to be transmitted; a plurality N of power amplification sections (S1, S2, S3, S4); and an output (A, B) providing an output voltage signal. Each of the N power amplification sections (S1, S2, S3, S4) is arranged to receive the input signal (RFin, b7-b0) and comprises a transformer (T1, T2, T3, T4) adapted to provide a respective output signal. Each transformer comprises a primary stage and a secondary stage; the secondary stages of the transformers (T1, T2, T3, T4) of the N power amplification sections (S1, S2, S3, S4) are combined such that a combined output voltage signal of the output stage is provided. The N power amplification sections (S1, S2, S3, S4) are adapted such that the input signal (RFin, b7-b0) is latched by clock signals (clock1, clock2, clock3, clock4) comprising different phases.

Abstract: Doherty and distributed amplifier (DA) designs are combined to achieve, wideband amplifiers with high efficiency dynamic range. A modified Doherty amplifier includes a wideband phase shifter providing first and second outputs, a main amplifier coupled to the first output, an auxiliary amplifier coupled to the second output, and a wideband combining network combining the outputs in phase. A multi-stage DA has a main output and a termination port, and a phase delay module and transforming network allowing power at the termination port to be combined in phase with power at the main output. In one combination, one or more stages of the DA may comprise a Doherty amplifier. In another combination, a modified series-type Doherty amplifying system is achieved by cascading main and auxiliary DAs. In any combination, Doherty topology may include a bias control module.

Abstract: Systems and methods for increasing amplifier supply power on demand for a plurality of xDSL signals is provided. In an embodiment, circuitry may be used to detect the signal or signals having the highest voltage. In different embodiments, the signal(s) with the highest absolute voltage or highest combined voltage between complementary signal pairs may be compared to a threshold voltage, such as an existing amplifier supply voltage. In different embodiments, when these highest voltage(s) exceed the threshold voltage, the corresponding amplifier supply voltages may be increased to meet the increased amplification demand. In some embodiments when these highest voltage(s) do not exceed the threshold voltage, the amplifier supply voltage may not be increased and the existing amplifier supply voltage may be used to amplify the xDSL signals.

Abstract: The invention relates to an integrated Doherty amplifier with an input network connecting the input to the main stage and to the peak stage, and with an output network connecting the main stage and the peak stage to the output. The output network has a shunt capacitor to signal-ground in parallel to a parasitic capacitance of the main stage, and has a shunt inductor between the main stage and signal ground. The shunt configuration enables to use the MMIC Doherty amplifier in a wide frequency range. At least some of the inductors of the input network and/or output network are implemented using bond wires. Their orientations and locations provide minimal mutual electromagnetic coupling between the wires and the return RF current paths.

Abstract: An amplifying device and a signal processing method based on an amplifying device are provided, capable of reducing performance requirements of modules and reducing design difficulty of the modules. The amplifying device includes at least one amplifying module, including two receiving paths, in which a first receiving path is configured to attenuate and amplify an input signal after the input signal is pre-amplified, and a second receiving path is configured to amplify the input signal when the input signal is not pre-amplified. The signal processing method based on the amplifying device is further provided. The amplifying device and the signal processing method may be applied in a communication network system.

Abstract: A buffer stage includes a flipped voltage follower and an emitter follower. The flipped voltage follower is connected between a high voltage rail and a low voltage rail and includes an input and an output. The emitter follower is also connected between the high voltage rail and the low voltage rail and includes an input and an output. A resistor connects the output of the flipped voltage follower to the output of the emitter follower. The input of the flipped voltage follower and the input of the emitter follower are connected together and provide an input of the buffer stage. The output of the emitter follower provides an output of the buffer stage. A differential buffer stage can be implemented using a pair of such buffer stages. Such a differential buffer stage can provide the output stage for a fully differential operational amplifier.

Abstract: A high frequency power amplifier includes first and second transistors connected in parallel and amplifying a high frequency signal; a first switch connected to outputs of the first and second transistors and which connects an input terminal selectively to first and second output terminals; a third transistor amplifying a signal output from the first output terminal of the first switch; and a second switch having a first input terminal connected to the third transistor, a second input terminal connected to the second output terminal of the first switch, and which selectively connects the first and the second input terminals to an output terminal of the second switch.

Abstract: Apparatus and methods for oscillation suppression are disclosed. In one embodiment, a power amplifier system includes a plurality of power amplifiers for amplifying an input radio frequency (RF) signal to generate an output RF signal. The plurality of power amplifiers include a first power amplifier, a second power amplifier, and a third power amplifier, each of which are configured to be individually switchable between an enabled state and a disabled state so as to control a power amplification of the power amplifier system. A first capacitor is electrically connected between the outputs of the first and second power amplifiers, and a second capacitor is electrically connected between the outputs of the second and third power amplifiers. The first and second capacitors are configured to allow signals generated using the first, second, and third power amplifiers to combine constructively to generate the output RF signal.

Abstract: Various embodiments relate to a reconfigurable integrated digital Chireix out-phasing power amplifier for use in high power base stations is described and a related method of said design. The power amplifier may include a power transistor circuitry having plurality of power transistors and shunt-series circuitry (L1C1, L2C2), a broadband combiner having Chireix compensation elements, and an impedance matching filter. The power transistor circuitry, the broadband combiner, and the impedance matching filter are integrated in a unified package. In one embodiment, the power amplifier is implemented in a real switch-mode to facilitate integration of the Chireix compensation elements so as to make the Chireix power amplifier tunable. A method of driving Chireix power amplifier structure is also described.

Abstract: A Doherty amplifier has a distributor for branching an input signal into two signals, a carrier amplifier to which one of the signals is inputted from the distributor, a peak amplifier to which another signal of the signals is inputted from the distributor, and a synthesizer for synthesizing output signals from the carrier amplifier and the peak amplifier. The carrier amplifier has a compound semiconductor device with at least two terminals. The peak amplifier has a single element semiconductor device. Bias voltages having the same polarity are applied to the two terminals of the compound semiconductor device.

Abstract: Apparatus and methods for capacitive load reduction are disclosed. In one embodiment, a power amplifier system includes a plurality of power amplifiers and an envelope tracking module for generating a supply voltage for the power amplifiers. The power amplifier system further includes a switch and a decoupling capacitor operatively associated with a first power amplifier of the system. The switch is configured to electrically float an end of the decoupling capacitor when the first power amplifier is disabled so as to reduce capacitive loading of the envelope tracker and to operate as a dampening resistor when the power amplifier is enabled so as to improve the stability of the system.

Abstract: A broadband power amplifier is embodied by realizing a substantially two-section output matching circuit or a substantially two-section input matching circuit using a quarter wave transformer itself as the input matching circuit or the output matching circuit. The broadband power amplifier is advantageous in view of integration and miniaturization due to the low characteristic impedance of the quarter wave transformer and enables both reduction of sizes of chips and circuits due to its simple circuit structure and reduction in cost due to the reduced number of passive devices.

Abstract: Apparatus and methods for capacitive load reduction are disclosed. In one embodiment, a power amplifier system includes an envelope tracker configured to provide a supply voltage to a plurality of power amplifiers. The power amplifiers include power supply inputs electrically connected in a star configuration so as to reduce a capacitive load of the envelope tracker. The distributed capacitance of the power amplifiers is used to provide RF grounding so as to reduce the size of or eliminated the use of bypass capacitors.

Abstract: A bond wire transformer comprises a plurality of primary bond wires coupled in parallel; and a plurality of secondary bond wires coupled in parallel, each secondary bond wire being spaced apart from and oriented relative to a corresponding primary bond wire so as to achieve a desired mutual inductance between the corresponding primary and secondary bond wires, thereby providing magnetic coupling between the primary and secondary bond wires.

Abstract: An amplifier circuit includes a signal summing node, a first amplifier configured to operate in a first mode, an impedance inverter, a second amplifier configured to operate in a second mode and a wideband impedance transformer. The impedance inverter couples an output of the first amplifier to the signal summing node. The impedance inverter is configured to provide impedance transformation and load modulation to the first amplifier. The second amplifier has an output coupled to the signal summing node. The wideband impedance transformer has a first end coupled to the signal summing node and a second end forming a terminal node. The wideband impedance transformer is configured to present a real impedance to the first amplifier over at least 25% of a radio frequency bandwidth of the amplifier circuit.

Abstract: An integrated radiofrequency amplifier with an operational frequency includes first and second Doherty amplifiers each having a main device, and a peak device connected at respective inputs and outputs by respective phase shift elements configured to provide a 90 degree phase shift at the operational frequency. An input of the amplifier is connected to the input of the main device of the first Doherty amplifier, an output of the amplifier is connected to the outputs of the peak devices of the first and second Doherty amplifiers and the input of the peak device of the first Doherty amplifier is connected to the input of the main device of the second Doherty amplifier by a phase shift element providing a 90 degree phase shift at the operational frequency.

Abstract: Systems and methods are provided for discrete resizing of power devices. The systems and methods can include a plurality of unit power amplifiers arranged in parallel, where each unit power amplifier includes at least one first input port, at least one first output port, and a plurality of sub-power-device cells configured in parallel between the at least one first input port and the at least one first output port; a switch controller, where the controller is operative to activate or deactivate at least one of the plurality of sub-power-device cells of a respective unit power amplifier; and an output matching network, where the matching network is configured to combine respective outputs from the respective plurality of unit power amplifiers to generate a system output, wherein during an operational state, all of the plurality of unit power amplifiers contribute outputs to the matching network to generate the system output.

Abstract: A method and apparatus improve the performance of a carrier amplifier in a Doherty amplifier. The Doherty amplifier includes a power divider, a carrier amplifier, at least one peaking amplifier, offset lines, and a Doherty circuit. The power divider provides a power signal to each of the carrier amplifier and the at least one peaking amplifier. The carrier amplifier amplifies power of a signal inputted from the power divider. The at least one peaking amplifier amplifies power of a signal inputted from the power divider. The offset lines control a load impedance when the at least one peaking amplifier does not operate. When the at least one peaking amplifier does not operate, the Doherty circuit generates the load impedance of the carrier amplifier that is larger than twice a load impedance at the maximum output power of the carrier amplifier.

Abstract: This invention provides a power amplifier device that satisfies both of delivering a high output and reducing the chip area occupied by the power amplifier device. The power amplifier device formed over a substrate comprises primary inductors arranged in a generally circular geometry, a ground pattern, transistor pairs, and a secondary inductor. The ground pattern is provided to extend from a portion of a region inside the circular primary inductor into regions outside the primary inductor, when viewed from the direction perpendicular to the substrate, and grounded at a plurality of points in the regions outside the primary inductor. To both ends of each primary inductor, first main electrodes of first and second transistors forming a transistor pair in linkage with the primary inductor are coupled respectively.

Abstract: In accordance with an exemplary embodiment of the present invention, a Doherty amplifier is provided for applications in radio frequency, microwave, and other electronic systems. An exemplary Doherty amplifier comprises a first MMIC having a first power detector, and a second MMIC having a second power detector. The first MMIC and the second MMIC are structurally identical. Furthermore, the first MMIC is configured as a carrier amplifier and the second MMIC is configured as a peaking amplifier. In the exemplary embodiment, an amplifier control bias of the carrier amplifier is a function of the power detected by the first power detector and an amplifier control bias of the peaking amplifier is a function of the power detected by the second power detector. The ability to assemble a Doherty amplifier using a single MMIC product results in a simple and less expensive manufacturing process.

Abstract: Current-feedback instrumentation amplifiers that include dynamic element matching for the input transconductance amplifiers by periodically swapping the transconductance amplifiers between the instrumentation amplifier input and the feedback input. The instrumentation amplifiers may include a gain error reduction loop, which loop corrects differences in the gains of the input transconductance amplifiers and eliminates the ripple in the instrumentation amplifier output caused by the dynamic element matching. If chopper stabilization is used, the amplifiers may also include an offset reduction loop. Various embodiments are disclosed.

Abstract: Implementations and examples of power amplifier devices, systems and techniques for amplifying RF signals, including power amplifier systems based on Composite Right and Left Handed (CRLH) metamaterial (MTM) structures.

Abstract: In a portable radio transceiver, a power amplifier system includes a saturation detector that detects power amplifier saturation in response to duty cycle of the amplifier transistor collector voltage waveform. The saturation detection output signal can be used by a power control circuit to back off or reduce the amplification level of the power amplifier to avoid power amplifier control loop saturation.

Abstract: Various embodiments relate to a reconfigurable integrated digital Chireix out-phasing power amplifier for use in high power base stations is described and a related method of said design. The power amplifier may include a power transistor circuitry having plurality of power transistors and shunt-series circuitry (L1C1, L2C2), a broadband combiner having Chireix compensation elements, and an impedance matching filter. In one embodiment, the power amplifier is implemented in a real switch-mode to facilitate integration of the Chireix compensation elements so as to make the Chireix power amplifier tunable. A method of driving Chireix power amplifier structure is also described. In some embodiments, a variable supply voltage may power the transistor circuitry based on the desired output power of the Chireix power amplifier. In some embodiments, the variable supply voltage may depend upon an out-phasing angle between the two drivers in the transistor circuitry.

Abstract: Doherty and distributed amplifier (DA) designs are combined to achieve, wideband amplifiers with high efficiency dynamic range. A modified Doherty amplifier includes a wideband phase shifter providing first and second outputs, a main amplifier coupled to the first output, an auxiliary amplifier coupled to the second output, and a wideband combining network combining the outputs in phase. A multi-stage DA has a main output and a termination port, and a phase delay module and transforming network allowing power at the termination port to be combined in phase with power at the main output. In one combination, one or more stages of the DA may comprise a Doherty amplifier. In another combination, a modified series-type Doherty amplifying system is achieved by cascading main and auxiliary DAs. In any combination, Doherty topology may include a bias control module.

Abstract: An apparatus and method for a switched capacitor architecture for multi-band Doherty power amplifiers are provided. The apparatus is for amplifying Radio Frequency (RF) signals, and the apparatus includes a multi-band Power Amplifier (PA) including a plurality of input matching circuits including switchable capacitors, and a plurality of output matching circuits including the switchable capacitors, wherein the multi-band PA is tunable to more than one RF frequency band.

Abstract: A RF power amplifying device is constituted by a system of a balanced amplifier including first phase shifters, a first RF power amplifier, a second RF power amplifier, second phase shifters, and a power combiner. Transmitting power Pout is detected by a first power level detector connected to an output of the first RF power amplifier, a second power level detector connected to an output of the second RF power amplifier, and an adder. A level control signal from a level control circuit controls transmitting power in response to a transmitting signal with wanted power level and a detected signal of the adder.