Including Particular Biasing Arrangement Patents (Class 330/296)
  • Patent number: 12015382
    Abstract: An apparatus and method for a linearized RF and microwave amplifier current source by feedback of a sampled RF amplifier output signal into a current mirror amplifier bias, to modulate the amplifier bias and produce an increase in a linearized amplifier output. The linearized RF and microwave amplifier is operable over a large bandwidth extending over multiple microwave frequency octaves.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: June 18, 2024
    Assignee: Scientific Components Corporation
    Inventors: Fuad Haji Mokhtar, Norizwani Mohd Nazari
  • Patent number: 11996832
    Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.
    Type: Grant
    Filed: June 13, 2023
    Date of Patent: May 28, 2024
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, Jerod F. Mason, David Scott Whitefield, Paul T. DiCarlo
  • Patent number: 11996810
    Abstract: A digital compensation system for a radio frequency (RF) power amplifier module is disclosed. The digital compensation system includes an RF power amplifier having a first input, a first output, and a first bias input, wherein the RF power amplifier is configured to receive an RF signal at the first input and generate an amplified version of the RF signal at the first output. The digital compensation system also includes compensation circuitry coupled between the first input and the first output and a bias output coupled to the RF power amplifier, wherein the compensation circuitry is configured, in response to the RF signal, to generate or adjust a bias signal at the first bias input to correct dynamic bias errors caused by amplification variations that have time constants.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: May 28, 2024
    Assignee: Qorvo US, Inc.
    Inventors: Frederick L. Martin, Gangadhar Burra, Nikolaus Klemmer, Paul Edward Gorday, Bror Peterson
  • Patent number: 11977404
    Abstract: An example circuit includes a first source follower input stage having a reference voltage input and a first output. A second source follower input stage has a feedback voltage input and a second output, in which second source follower input stage is configured to receive a feedback voltage at the feedback voltage input. The feedback voltage is representative of an output voltage at an output terminal of the circuit. A common gate differential gain stage has first and second differential inputs and first and second drive outputs. The first differential input is coupled to the first output, and the second differential input is coupled to the second output. The common gate differential gain stage is configured to control the output voltage at the output terminal by controlling at least one of the first or second drive outputs.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: May 7, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Ramesh Mosur Chandrasekaran
  • Patent number: 11973467
    Abstract: Multi-level envelope trackers with an analog interface are provided herein. In certain embodiments, an envelope tracking system for generating a power amplifier supply voltage for a power amplifier is provided. The envelope tracking system includes a multi-level supply (MLS) DC-to-DC converter that outputs multiple regulated voltages, and an MLS modulator that controls selection of the regulated voltages over time based on an analog envelope signal corresponding to an envelope of the RF signal amplified by the power amplifier.
    Type: Grant
    Filed: April 14, 2023
    Date of Patent: April 30, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventors: Florinel G. Balteanu, Serge Francois Drogi, Shayan Farahvash, David Richard Pehlke
  • Patent number: 11949411
    Abstract: A semiconductor device (1) according to the present disclosure includes: an n-channel depletion-mode transistor (10); an input matching circuit inside which the gate terminal (11) and the ground terminal (22) are DC-connected; a self-bias circuit (26) including a resistor (14) biasing the transistor (10) by a voltage drop due to a current flowing through the resistor (14), and a capacitor (15) connected in parallel to the resistor 14) and regarded as short-circuit at a frequency of the high-frequency power; and a diode (31) having an endmost anode connected to the source terminal (12) and an endmost cathode connected to the ground terminal (22), and connected in one stage or connected in series in a plurality of stages in the same direction.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: April 2, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hitoshi Kurusu
  • Patent number: 11942912
    Abstract: This disclosure describes amplifiers that include impedance circuits that are configured to adapt to various contexts. For example, a variable-gain amplifier can include a gain circuit configured to amplify a signal and to operate in a plurality of gain modes, and an impedance circuit coupled to the gain circuit. The impedance circuit can include an inductor and a switching-capacitive arm coupled in parallel to the inductor. The impedance circuit can be configured to operate based at least in part on a gain mode from among the plurality of gain modes.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: March 26, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventor: Weiheng Chang
  • Patent number: 11942902
    Abstract: Methods related to power amplification systems with adjustable common base bias. A method of implementing a power amplification system can include providing a cascode amplifier coupled to a radio-frequency input signal and coupled to a radio-frequency output. The method can further include providing a biasing component configured to apply one or more biasing signals to the cascode amplifier, the biasing component including a bias controller and one or more bias components. Each respective bias component may be coupled to a respective bias transistor.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: March 26, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventors: Philip John Lehtola, Scott W. Coffin
  • Patent number: 11936350
    Abstract: A power amplifier circuit includes a first transistor having a first terminal to which a first signal inputs, a second transistor having a first terminal to which the first signal inputs, a first resistor having a first end to which a first bias current is supplied and a second end electrically connected to the first terminal of the first transistor, a second resistor having a first end to which a second bias current is supplied and a second end electrically connected to the first terminal of the second transistor, and a third resistor having a first end connected to the first end of the first resistor and a second end connected to the first end of the second resistor.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: March 19, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Makoto Itou, Satoshi Arayashiki, Satoshi Goto
  • Patent number: 11936345
    Abstract: An impedance adjustment circuit is connected in parallel with a bias current output end of a bias circuit. The bias circuit is configured to provide bias current to a first circuit unit. The impedance adjustment circuit is configured to adjust source impedance of the first circuit unit.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: March 19, 2024
    Assignee: SMARTER MICROELECTRONICS (GUANG ZHOU) CO., LTD.
    Inventors: Jinliang Deng, Ping Li
  • Patent number: 11894809
    Abstract: Methods and devices for amplifying an input RF signal according to at least two gain-states is described. According to one aspect, a multi gain amplifier circuit including a low noise amplifier having a stack of transistors is used for amplification of the input RF signal. When switching from a low gain-state to a high gain-state, the drain-to-source voltage of the output transistor of the stack is increased to affect region of operation of the output transistor, and thereby reduce non-linearity at the output of the amplifier. When switching from the high gain-state to the low gain-state, the drain-to-source voltage of the input transistor of the stack is increased to affect region of operation of the input transistor, and thereby reduce non-linearity at the output of the amplifier.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: February 6, 2024
    Assignee: pSemi Corporation
    Inventors: Rong Jiang, Haopei Deng
  • Patent number: 11876494
    Abstract: A protection circuit is provided. The protection circuit protects a power amplifier that includes a power transistor configured to receive a power voltage, and a bias circuit configured to supply a bias current to the power transistor. The protection circuit includes: a first transistor, connected between a terminal of the bias circuit and a ground, and configured to sink a first current from the terminal of the bias circuit; and a second transistor, comprising a first terminal connected to the power voltage, a second terminal connected to a control terminal of the first transistor, and a control terminal connected to a reference voltage.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: January 16, 2024
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Gyu-Suck Kim, Youngsik Hur, Geunyong Lee
  • Patent number: 11870401
    Abstract: A PA module includes: a multilayer substrate having a ground pattern layer connected to a ground of a power source; amplifier transistors disposed on the multilayer substrate; a bypass capacitor having one end connected to the collector of the amplifier transistor; a first wiring line connecting the emitter of the amplifier transistor and the ground pattern layer to each other; a second wiring line connecting the emitter of the amplifier transistor and the ground pattern layer to each other; a third wiring line connecting the other end of the bypass capacitor and the ground pattern layer to each other; and a fourth wiring line formed between the amplifier transistor and the ground pattern layer and between the bypass capacitor and the ground pattern layer and connecting the first wiring line and the third wiring line to each other.
    Type: Grant
    Filed: February 2, 2023
    Date of Patent: January 9, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Isao Takenaka
  • Patent number: 11863129
    Abstract: A bias circuit includes first to sixth transistors and first to fifth resistors. The collector of the fifth transistor is coupled to a node in a path connecting the collector of the fourth transistor and one end of the third resistor. The collector of the sixth transistor Tr6 is coupled to one end of the fifth resistor.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: January 2, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hideyo Yamashiro
  • Patent number: 11864295
    Abstract: Front end systems and related devices, integrated circuits, modules, and methods are disclosed. One such packaged module includes a multi-mode power amplifier circuit in an interior of a radio frequency shielding structure and an antenna external to the radio frequency shielding structure. The multi-mode power amplifier circuit includes a stacked output stage including a transistor stack of two or more transistors. The multi-mode power amplifier circuit also includes a bias circuit configured to control a bias of at least one transistor of the transistor stack based on a mode of the multi-mode power amplifier circuit. The radio frequency shielding structure can extend above a package substrate. The antenna can be on the package substrate. Other embodiments of front end systems are disclosed, along with related devices, integrated circuits, modules, methods, and components thereof.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: January 2, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventors: Yasser Khairat Soliman, Hoang Mong Nguyen, Anthony James LoBianco, Gregory Edward Babcock, Darren Roger Frenette, George Khoury, René Rodríguez, Leslie Paul Wallis
  • Patent number: 11863128
    Abstract: A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor that supplies a bias current based on a first current which is a part of a control current to the first transistor; a current output element in which a current flowing therethrough increases in accordance with a rise in temperature; and a wiring portion including a plurality of metal layers that are electrically connected to an emitter of the first transistor and that are stacked one on top of another so as to oppose the semiconductor substrate. At least one metal layer among the plurality of metal layers extends so as to overlap an area extending from at least a part of a first disposition area in which the first transistor is disposed to a second disposition area in which the current output element is disposed in plan view of the semiconductor substrate.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: January 2, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hideyuki Sato, Koshi Himeda
  • Patent number: 11855595
    Abstract: Composite cascode power amplifiers for envelope tracking applications are provided herein. In certain embodiments, an envelope tracking system includes a composite cascode power amplifier that amplifies a radio frequency (RF) signal and that receives power from a power amplifier supply voltage, and an envelope tracker that generates the power amplifier supply voltage based on an envelope of the RF signal. The composite cascode power amplifier includes an enhancement mode (E-MODE) field-effect transistor (FET) for amplifying the RF signal and a depletion mode (D-MODE) FET in cascode with the E-MODE FET.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: December 26, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: Aleksey A. Lyalin, Huiming Xu, Shayan Farahvash, Reinhard Ulrich Mahnkopf
  • Patent number: 11855586
    Abstract: A power amplifier module includes an amplifier transistor and a bias circuit. A first power supply voltage based on a first operation mode or a second power supply voltage based on a second operation mode is supplied to the amplifier transistor. The amplifier transistor receives a first signal and outputs a second signal obtained by amplifying the first signal. The bias circuit supplies a bias current to the amplifier transistor. The bias circuit includes first and second resistors and first and second transistors. The first transistor is connected in series with the first resistor and is turned ON by a first bias control voltage which is supplied when the first operation mode is used. The second transistor is connected in series with the second resistor and is turned ON by a second bias control voltage which is supplied when the second operation mode is used.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: December 26, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masao Kondo, Hidetoshi Matsumoto
  • Patent number: 11837998
    Abstract: A gain compression compensation circuit of a radio frequency power amplifier includes: a low-pass filtering module configured to receive a part of radio frequency signals output from a first power amplification transistor and to filter, from the part of radio frequency signals, radio frequency signals with a frequency above a fundamental wave to obtain a filtered signal; and a rectifying module configured to receive the filtered signal output by the low-pass filtering module and to rectify the filtered signal to obtain a rectified current; and to output the rectified current to a bias transistor and superimpose the rectified current with a bias current Ibias to flow into the bias transistor.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: December 5, 2023
    Assignee: SMARTER MICROELECTRONICS (GUANG ZHOU) CO., LTD.
    Inventors: Jiangtao Yi, Qiang Su, Huadong Wen
  • Patent number: 11831279
    Abstract: In accordance with an embodiment, a method for operating a millimeter-wave power amplifier including an input transistor having an output node coupled to a load path of a cascode transistor includes: receiving a millimeter-wave transmit signal at a control node of the input transistor; amplifying the millimeter-wave transmit signal to form an output signal; providing the output signal to a load coupled to an output node of the cascode transistor; and adjusting a first DC bias current of the input transistor to form a substantially constant second DC bias current of the cascode transistor.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: November 28, 2023
    Assignee: Infineon Technologies AG
    Inventors: David Seebacher, Matteo Bassi, Dmytro Cherniak, Fabio Padovan
  • Patent number: 11824503
    Abstract: A charge amplifier circuit is provided. The charge amplifier circuit is couplable to a transducer that generates an electrical charge that varies with an external stimulus. The charge amplifier circuit includes an amplification stage having an input node, couplable to the transducer, and an output node. The amplification stage biases the input node at a first direct current (DC) voltage. The charge amplifier circuit includes a feedback circuit, which includes a feedback capacitor, electrically coupled between the input and output nodes of the amplification stage. The feedback circuit includes a resistor electrically coupled to the input node, and a level-shifter circuit, electrically coupled between the resistor and the output node. The level-shifter circuit biases the output node at a second DC voltage and as a function of a difference between the second DC voltage and a reference voltage.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: November 21, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Danioni
  • Patent number: 11817837
    Abstract: A power amplifier circuit has an input node from which an input signal, which is a high-frequency signal, is inputted and an output node to which the input signal is amplified by a differential amplifier circuit to be outputted as an output signal. The power amplifier circuit includes a balun transformer (second balun transformer) including an input-side winding that has a substantially center to which a power-supply voltage is supplied and that is connected between differential outputs of the differential amplifier circuit, and an output-side winding that is coupled to the input-side winding via an electromagnetic field and that has one end connected to a reference potential; and a capacitive element (capacitor) provided between another end (node) of the output-side winding and the output node.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: November 14, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuri Honda, Satoshi Tanaka, Yasuhisa Yamamoto, Hiroki Shonai
  • Patent number: 11784613
    Abstract: Packaged RF transistor amplifiers are provided that include a flat no-lead overmold package that includes a die pad, a plurality of terminal pads and an overmold encapsulation that at least partially covers the die pad and the terminal pads and an RF transistor amplifier die mounted on the die pad and at least partially covered by the overmold encapsulation. These packaged RF transistor amplifiers may have an output power density of at least 3.0 W/mm2.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: October 10, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: Phil Saint-Erne, William Pribble, Warren Brakensiek, Bradley Millon
  • Patent number: 11784645
    Abstract: The present disclosure provides a technology for a level shifter that allows the selection of a single-stage level shifter or a two-stage level shifter by a simple alteration to wiring. When the single-stage level shifter is selected, some circuits may remain as dummy circuits.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: October 10, 2023
    Assignee: LX SEMICON CO., LTD.
    Inventors: Chung Min Lee, Hun Yong Lim
  • Patent number: 11777498
    Abstract: RF transistors manufactured using a bulk CMOS process exhibit non-linear drain-body and source-body capacitances which degrade the linearity performance of the RF circuits implementing such transistors. The disclosed methods and devices address this issue and provide solutions based on implementing two or more bias voltages in accordance with the states of the transistors. Various exemplary RF circuits benefiting from the described methods and devices are also presented.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: October 3, 2023
    Assignee: PSEMI CORPORATION
    Inventors: David Kovac, Joseph Golat
  • Patent number: 11777454
    Abstract: Disclosed is a bias circuit for a radio frequency power amplifier, including a resistor voltage divider network, a power amplifier coupled with the resistor voltage divider network and a bias voltage adjusting loop coupled to the resistor voltage divider network and including one voltage divider resistor and one transistor pair; one terminal of the voltage divider resistor is connected with a reference voltage, and an other terminal is coupled with a gate of the first metal oxide semiconductor transistor; the transistor pair includes a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor, where a gate of the second metal oxide semiconductor transistor is coupled to the gate of the first metal oxide semiconductor transistor.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: October 3, 2023
    Assignee: GUANGDONG UNIVERSITY OF TECHNOLOGY
    Inventors: Jianqiang Chen, Zhihao Zhang, Guohao Zhang
  • Patent number: 11764736
    Abstract: The present invention discloses a bias compensation circuit. The bias compensation circuit includes a detecting circuit, including a diode-connected transistor circuit, with a first end for receiving a first current, and a second end coupled to a first reference voltage end; and a first diode circuit, with a first end for receiving a second current, and a second end coupled to the first reference voltage end; wherein the detecting circuit provides a first voltage level according to the diode-connected transistor circuit, and provides a second voltage level according to the first diode circuit; a voltage-current converting circuit, coupled to the detecting circuit, for generating a first reference current according to the first voltage level and the second voltage level; and a bias circuit, coupled to the voltage-current converting circuit, for receiving the first reference current, to provide a bias voltage level according to the first reference current.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: September 19, 2023
    Assignee: RichWave Technology Corp.
    Inventors: Chih-Sheng Chen, Tien-Yun Peng
  • Patent number: 11757477
    Abstract: An embodiment integrated electronic device comprises a mixer module including a voltage/current transconductor stage including first transistors and connected to a mixing stage including second transistors, wherein the mixing stage includes a resistive degeneration circuit connected to the sources of the second transistors and a calibration input connected to the gates of the second transistors and intended to receive an adjustable calibration voltage, and the sources of the first transistors are directly connected to a cold power supply point.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: September 12, 2023
    Assignee: STMICROELECTRONICS (ALPS) SAS
    Inventors: Frederic Rivoirard, Felix Gauthier
  • Patent number: 11757414
    Abstract: Multi-level envelope tracking systems with adjusted voltage steps are provided. In certain embodiments, an envelope tracking system for generating a power amplifier supply voltage for a power amplifier is provided. The envelope tracking system includes a multi-level supply (MLS) DC-to-DC converter that outputs multiple regulated voltages, an MLS modulator that controls selection of the regulated voltages over time based on an envelope signal corresponding to an envelope of a radio frequency (RF) signal amplified by the power amplifier, and a modulator output filter coupled between an output of the MLS modulator and the power amplifier supply voltage. The envelope tracking system further includes a switching point adaptation circuit configured to control the voltage level of the regulated voltages outputted by the MLS DC-to-DC converter based on a power level of the RF signal.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: September 12, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: Serge Francois Drogi, Florinel G. Balteanu
  • Patent number: 11750155
    Abstract: Aspects of the description provide for a circuit. In some examples, the circuit includes a input pair of transistors, a bias transistor having a bias transistor gate, a bias transistor drain, and a bias transistor source, the bias transistor drain coupled to the input pair of transistors and the bias transistor source coupled to ground, and a resistor coupled between the bias transistor gate and the input pair of transistors.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: September 5, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aniruddha Roy, Kunal Suresh Karanjkar
  • Patent number: 11734459
    Abstract: Physical Unclonable Functions, PUFs, are hardware devices designed to generate a number that is random (i.e., two identical PUFs should produce randomly different numbers from each other) and persistent (i.e., a PUF should consistently generate the same number over time). Over time, aspects of the PUF hardware may change or drift, which may ultimately cause the generated number to change, and therefore no longer be persistent. Failure to generate a persistent number may cause difficulties for other devices that rely on the persistence of the number generated by the PUF, for example as part of a cryptographic process. The present disclosure relates to monitoring over time the physical characteristics of the PUF that are used to generate its number, and thereby keep track of its reliability to generate a random number that is persistent.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: August 22, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventors: George Redfield Spalding, Jonathan Ephraim David Hurwitz, William Michael James Holland
  • Patent number: 11728773
    Abstract: Apparatus and methods for bias switching of power amplifiers are provided herein. In certain configurations, a power amplifier system includes a power amplifier that provides amplification to a radio frequency (RF) signal and a bias control circuit that biases the power amplifier. The power amplifier includes an amplification transistor that receives the RF signal at an input, and a first bias network and a second bias network each connected to the input. The bias control circuit includes a first switch, a first reference current source that provides the first reference current to the first bias network through the first switch, a second switch, and a second reference current source that provides the second reference current to the second bias network through the second switch.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: August 15, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: Netsanet Gebeyehu, Srivatsan Jayaraman, Edward James Anthony
  • Patent number: 11721523
    Abstract: This disclosure describes systems, methods, and apparatus for generating a multi-level pulsed waveform using a DC section and a power amplifier. To improve DC section efficiency, a master state is used to determine when the rail voltage can be lowered, and to only allow a state assigned as the master state to lower the rail voltage. Selection of the master state is based on (1) any state having to raise the rail voltage to meet a power demand or (2) a state having the highest drive voltage as determined at the end of each pulse cycle. Further, to avoid challenges from integrator controller, drive voltage is carried over from a last state of one pulse cycle to a first state of a next pulse cycle and assignment of master state in the first state of each pulse cycle is not important and can be arbitrarily selected.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: August 8, 2023
    Assignee: Advanced Energy Industries, Inc.
    Inventor: Chad S. Samuels
  • Patent number: 11722125
    Abstract: A bidirectional RF circuit, preferably including a plurality of terminals, a switch, a transistor, a coupler, and a feedback network. The circuit can optionally include a drain matching network, an input matching network, and/or one or more tuning inputs. In some variations, the circuit can optionally include one or more impedance networks, such as an impedance network used in place of the feedback network; in some such variations, the circuit may not include a coupler, switch, and/or input matching network. A method for circuit operation, preferably including operating in an amplifier mode, operating in a rectifier mode, and/or transitioning between operation modes.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: August 8, 2023
    Assignee: Reach Power, Inc.
    Inventors: Asmita Dani, Christopher Joseph Davlantes
  • Patent number: 11683062
    Abstract: A reconfigurable amplifier includes a first transistor having a gate coupled to an input of the reconfigurable amplifier, and a source coupled to a ground. The reconfigurable amplifier also includes a gate control circuit, and a second transistor having a gate coupled to the gate control circuit, a source coupled to a drain of the first transistor, and a drain coupled to an output of the reconfigurable amplifier, wherein the gate control circuit is configured to output a bias voltage to the gate of the second transistor in a cascode mode, and output a switch voltage to the gate of the second transistor in a non-cascode mode. The reconfigurable amplifier further includes a load coupled to the output of the reconfigurable amplifier.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: June 20, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Janakiram Sankaranarayanan, Jun Tan, Lai Kan Leung, Timothy Donald Gathman, Mehmet Ipek, Ojas Choksi
  • Patent number: 11677395
    Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: June 13, 2023
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, Jerod F. Mason, David Scott Whitefield, Paul T. DiCarlo
  • Patent number: 11677358
    Abstract: A power amplifier circuit includes a substrate and a semiconductor chip disposed on or above the substrate. The semiconductor chip includes a power amplifier unit that amplifies an RF signal, a ground terminal to which a ground of the power amplifier unit is coupled, and a first circuit element having a first end electrically coupled to the ground terminal without any portion outside the semiconductor chip interposed therebetween, and having a second end. The substrate includes a second circuit element having a first end electrically coupled to an output of the power amplifier unit and a second end electrically coupled to the second end of the first circuit element. The first and second circuit elements constitute a harmonic wave termination circuit. The harmonic wave termination circuit reflects, to the power amplifier unit, a harmonic wave component of the amplified RF signal output from the power amplifier unit.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: June 13, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masatoshi Hase, Satoshi Tanaka
  • Patent number: 11664771
    Abstract: A power amplifier includes a first transistor with a gate to which input power is applied and a drain from which output power is provided, a bias circuit configured to apply a bias to the gate of the first transistor, and a coupler configured to distribute the input power to the gate of the first transistor and to the bias circuit. The bias circuit includes a voltage generator circuit including a second transistor with a gate to which the power distributed to the bias circuit by the coupler is applied, the voltage generator circuit being configured to generate a first DC voltage increasing in accordance with an increase in the power distributed to the bias circuit. The bias circuit includes a level shifter circuit configured to generate a second DC voltage increasing in accordance with an increase in the first DC voltage.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: May 30, 2023
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Masahiro Tanomura
  • Patent number: 11658764
    Abstract: The disclosure relates to an apparatus including a receiver configured to process a radio frequency (RF) signal to generate a baseband signal; a radio frequency (RF) jammer detector configured to generate a signal indicative of whether an RF jammer is present at an input of the receiver; and a receiver bias circuit configured to generate a supply voltage for the receiver based on the RF jammer indication signal. In another aspect, the apparatus includes constant gain bias circuit to maintain the gain of the receiver constant in response to changes in the supply voltage. In other aspects, the receiver bias circuit may suspend the generating of the supply voltage based on the RF jammer indication signal if the power level of the target received signal is above a threshold. In other aspects, the receiver bias circuit changes the supply voltage during cyclic prefix (CP) intervals between downlink intervals.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: May 23, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Lai Kan Leung, Aleksandar Miodrag Tasic, Francesco Gatta, Chiewcharn Narathong, Kyle David Holland
  • Patent number: 11646704
    Abstract: A power amplifier circuit includes a first transistor that amplifies a first signal and outputs a second signal; a second transistor that amplifies the second signal and outputs a third signal; a bias circuit that supplies a bias current to a base of the second transistor; and a bias adjustment circuit that adjusts the bias current by subjecting the first signal to detection. The bias adjustment circuit controls the bias current such that a first current extracted from the bias circuit depends on a magnitude of the first signal.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: May 9, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takayuki Tsutsui, Masao Kondo, Satoshi Tanaka
  • Patent number: 11632090
    Abstract: A push-push frequency doubler based on complementary transistors is provided. The first differential amplifier circuit receives a differential input signal having an initial frequency, and amplifies the amplitude of the second harmonic of the differential input signal to obtain a first signal. The second differential amplifier circuit receives the differential input signal with the initial frequency and amplifies the amplitude of the second harmonic of the differential input signal to obtain the second signal. Where, the first signal and the second signal are a set of differential signals with the same amplitude and a phase difference of 180°. The output load circuit extracts the second harmonic signal in the first and second signal respectively to obtain and output a pair of differential output signal with first output frequency whose value is twice of the initial frequency. As a result, the frequency doubler with differential output signal is realized.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: April 18, 2023
    Assignee: THE CHINESE UNIVERSITY OF HONG KONG, SHENZHEN
    Inventors: Liang Wu, Xiaoping Wu, Yihui Wang
  • Patent number: 11621672
    Abstract: A circuit includes a field effect transistor (FET), a reference transistor having an output coupled to an output of the FET, an active bias circuit coupled to the reference transistor and configured to generate an input signal for the reference transistor in response to a change in drain current of the reference transistor due to carrier trapping and to apply the input signal to an input of the reference transistor, and a summing node coupled to an input of the FET and to the input of the reference transistor. The summing node adds the input signal to an input signal of the FET to compensate the carrier trapping effect.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: April 4, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: Young-Youl Song, Zulhazmi A. Mokhti, John Wood, Qianli Mu, Jeremy Fisher
  • Patent number: 11621681
    Abstract: A radio frequency power amplifier and a device are disclosed. A first microstrip line and a second microstrip line are coupled, one end of the second microstrip line is an open stub and another end of the second microstrip line is grounded; and the first microstrip line having a first width is connected to a first transmission line having a second width which is wider than the first width. Therefore, some harmonic bands suppression can be implemented independently. Furthermore, the harmonic termination is independent and may not impact one or more fundamental components during matching a network. In addition, it may not take up more space and is sufficiently compact. Furthermore, sufficient wide harmonic response bandwidth can be provided.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: April 4, 2023
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventors: Zhancang Wang, Shun Li
  • Patent number: 11611347
    Abstract: An integrator and an analog-to-digital converter are provided. The analog-to-digital converter includes the integrator, a comparison circuit and a control logic circuit. The integrator includes an operational amplifier, offset capacitors, input capacitors, integral capacitors and controllable switches. The input capacitors and the integral capacitors are connected to the operational amplifier via controllable switches, so that the integrator operates in various operation modes. Operation states of the offset capacitors in a first phase and a second phase of an operation cycle are controlled by switching on or off the controllable switches. Therefore, an offset voltage of the integrator is eliminated, and conversion efficiency and conversion accuracy of the analog-to-digital converter is improved.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: March 21, 2023
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD
    Inventors: Ying Huang, Di Gao, Kun Li, Jinyu Qin
  • Patent number: 11601100
    Abstract: The frequency detector includes a first impedance circuit and a second impedance circuit. The first impedance circuit has a first terminal for receiving an input signal, and a second terminal for outputting a divisional signal. The second impedance circuit has a first terminal coupled to the second terminal of the first impedance circuit, and a second terminal coupled to a first system voltage terminal. The frequency response of the first impedance circuit is different from a frequency response of the second impedance circuit. The resistance of the first impedance circuit, a resistance of the second impedance circuit, and the divisional signal change with a frequency of the input signal.
    Type: Grant
    Filed: August 2, 2020
    Date of Patent: March 7, 2023
    Assignee: RichWave Technology Corp.
    Inventors: Hwey-Ching Chien, Chih-Sheng Chen, Jhao-Yi Lin, Ching-Wen Hsu
  • Patent number: 11601102
    Abstract: A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor disposed on the semiconductor substrate and configured to supply a bias current based on a first current which is a part of a control current to the first transistor; a third transistor disposed on the semiconductor substrate and having a collector configured to be supplied with a second current which is a part of the control current and an emitter configured to output a third current based on the second current; a first bump electrically connected to an emitter of the first transistor and disposed so as to overlap a first disposition area in which the first transistor is disposed in plan view of the semiconductor substrate; and a second bump disposed so as to overlap a second disposition area in which the third transistor is disposed in the plan view.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: March 7, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hiroaki Tokuya, Hideyuki Sato, Fumio Harima, Kenichi Shimamoto, Satoshi Tanaka, Takayuki Kawano, Ryoki Shikishima, Atsushi Kurokawa
  • Patent number: 11601096
    Abstract: A PA module includes: a multilayer substrate having a ground pattern layer connected to a ground of a power source; amplifier transistors disposed on the multilayer substrate; a bypass capacitor having one end connected to the collector of the amplifier transistor; a first wiring line connecting the emitter of the amplifier transistor and the ground pattern layer to each other; a second wiring line connecting the emitter of the amplifier transistor and the ground pattern layer to each other; a third wiring line connecting the other end of the bypass capacitor and the ground pattern layer to each other; and a fourth wiring line formed between the amplifier transistor and the ground pattern layer and between the bypass capacitor and the ground pattern layer and connecting the first wiring line and the third wiring line to each other.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: March 7, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Isao Takenaka
  • Patent number: 11588513
    Abstract: A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: February 21, 2023
    Assignee: pSemi Corporation
    Inventors: Mark L. Burgener, James S. Cable
  • Patent number: 11581857
    Abstract: Components of a power amplifier controller may support lower voltages than the power amplifier itself. As a result, a surge protection circuit that prevents a power amplifier from being damaged due to a power surge may not effectively protect the power amplifier controller. Embodiments disclosed herein present an overvoltage protection circuit that prevents a charge-pump from providing a voltage to a power amplifier controller during a detected surge event. By separately detecting and preventing a voltage from being provided to the power amplifier controller during a surge event, the power amplifier controller can be protected regardless of whether the surge event results in a voltage that may damage the power amplifier. Further, embodiments of the overvoltage protection circuit can prevent a surge voltage from being provided to a power amplifier operating in 2G mode.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: February 14, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: Wendy Ng, Wei Long, Kevin Cho
  • Patent number: 11569784
    Abstract: A power amplifier includes a transistor, a temperature sensor and a filter. The transistor is used to receive a bias signal and amplify a radio frequency (RF) signal. The temperature sensor is arranged in proximity to the transistor, and is used to detect a temperature of the transistor to provide a voltage signal at a control node accordingly. The filter is coupled to the temperature sensor and is used to filter the voltage signal to generate a filtered voltage. The bias signal is adjusted according to the filtered voltage.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: January 31, 2023
    Assignee: RichWave Technology Corp.
    Inventors: Tien-Yun Peng, Chih-Sheng Chen