Including Particular Biasing Arrangement Patents (Class 330/296)
  • Patent number: 10263577
    Abstract: A gate drive circuit includes a lower limit clamping circuit, an upper limit clamping circuit, and an averaging circuit. The lower limit clamping circuit clamps the input node of a transistor at a minimum voltage with respect to the common node of the transistor, while the upper limit clamping circuit clamps the input node of the transistor at a maximum voltage with respect to the common node of the transistor and the averaging circuit sets the average voltage of the input node with respect to the common node over a specified period of time. The transistor including a common node, an output node and an input node receives the input signal. Controlling the upper limit, lower limit and average value in conjunction with fast transitions between the lower and upper limits controls the duty cycle of the input signal.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: April 16, 2019
    Assignee: Advanced Energy Industries, Inc.
    Inventor: Gideon Johannes Jacobus Van Zyl
  • Patent number: 10230336
    Abstract: A radio frequency (RF) power detector includes a first circuit having a first rectifying diode with a first terminal coupled to a first power supply voltage node. The first circuit also includes an input terminal coupled to a second terminal of the first rectifying diode, a first transistor having a first collector coupled to the second terminal of the first rectifying diode and a first emitter coupled to a reference voltage node, and a second transistor having a second emitter coupled to the reference voltage node and a second collector coupled to a second power supply voltage node. The first circuit further includes a low-pass filter network coupled between a first base of the first collector and a second base of the second transistor, and a first output terminal coupled to the second collector of the second transistor.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: March 12, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Bernd Schleicher
  • Patent number: 10164594
    Abstract: A circuit is formed on an SOI. The bias generator is connected to the gates of first and second transistors. In the bias generator, a first variable current source is connected to the power supply circuit via a power supply node. A third transistor is connected between the first variable current source and a ground-voltage source. A gate thereof is connected to the gate of the first transistor. A first operational amplifier controls a gate voltage of the third transistor so that a voltage at a second node between the first variable current source and the third transistor becomes almost equal to a reference-voltage. A first characteristics changer is connected to the gate of the third transistor or a second node, to change at least one loop gain characteristics and phase characteristics of a loop from the first operational amplifier, through the third transistor, to the first variable current source.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 25, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Maomi Katsumata
  • Patent number: 10122325
    Abstract: A distributed amplifier with improved stabilization includes an input transmission circuit, an output transmission circuit, at least one cascode amplifier coupled between said input and output transmission circuits. Each cascode amplifier includes a common-gate configured transistor coupled to the output transmission circuit, and a common-source configured transistor coupled between the input transmission circuit and the common-gate configured transistor. The distributed amplifier also includes a non-parasitic resistance and capacitance coupled in series between a drain and a gate of at least one of the common-gate configured transistors for increasing the amplifier stability.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: November 6, 2018
    Assignee: HITTITE MICROWAVE LLC
    Inventor: Keith Benson
  • Patent number: 10122179
    Abstract: Features and advantages of certain embodiments include a plurality of power supplies that work together to deliver power to a target circuit. In one embodiment, a downstream power supply provides a fast current delivery in response to load current transients and generates a feedback signal to control an upstream power supply so that the upstream and downstream power supplies work together to meet the current and voltage requirements of a target circuit across a wide range of loading conditions.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: November 6, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Todd Sutton, Charles Tuten
  • Patent number: 10116273
    Abstract: A current reuse FET amplifier according to the present invention provides an effect of reducing a variation of bias current of the amplifier, with gate voltage or a resistor for self-biasing of an FET of the amplifier changing in accordance with a process variation of saturation current Idss of the FET.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: October 30, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yoshihiro Tsukahara
  • Patent number: 10110169
    Abstract: Apparatus and methods for envelope tracking systems with automatic mode selection are provided herein. In certain configurations, a power amplifier system includes a power amplifier that amplifies a radio frequency signal and that receives power from a power amplifier supply voltage. The power amplifier system further includes an envelope tracker that generates the power amplifier supply voltage based on an envelope signal corresponding to an envelope of the radio frequency signal. The envelope tracker includes a signal bandwidth detection circuit that processes the envelope signal to generate a detected bandwidth signal, and a mode control circuit that controls a mode of the error amplifier based on the detected signal bandwidth.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: October 23, 2018
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Sabah Khesbak, Serge Francois Drogi, Florinel G. Balteanu
  • Patent number: 10097144
    Abstract: An electrical signal amplifier, having an amplifier input and an amplifier output is provided, which are set up to receive an electrical input signal and to output an amplified signal as electrical output signal, wherein an amplifier circuit arranged between the amplifier input and the amplifier output and amplifying the electrical input signal has a voltage divider circuit and a series circuit of gate-source paths in a transistor arrangement, which is assigned to an amplifier stage, the voltage divider circuit is connected downstream of the amplifier input, and an output of the voltage divider circuit is connected to gate contacts of the series circuit of gate-source paths, and a gate voltage supply circuit is connected to the gate contacts of the series circuit of gate-source paths. The disclosure furthermore relates to a method for amplifying an electrical signal by means of an electrical signal amplifier.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: October 9, 2018
    Assignee: BRANDENBURGISCHE TECHNISCHE UNIVERSITÄT COTTBUS—SENFTENBERG
    Inventors: Matthias Rudolph, Cristina Andreea Andrei
  • Patent number: 10090809
    Abstract: A multi-mode mobile power management circuit is provided. The multi-mode mobile power management circuit includes a dual-mode amplifier circuit(s) configured to amplify a radio frequency (RF) signal for transmission in a defined RF band(s), such as a long-term evolution (LTE) band(s) or a fifth-generation new radio (5G-NR) band(s). The multi-mode mobile power management circuit includes a pair of tracker circuitries coupled to the dual-mode amplifier circuit. Each tracker circuitry includes a charge pump circuitry configured to generate a voltage and a current. When the dual-mode amplifier circuit amplifies the RF signal for transmission in the 5G-NR band(s), both charge pump circuitries are controlled to provide two currents to the dual-mode amplifier circuit. As a result, the dual-mode amplifier circuit is able to amplify the RF signal to a higher power corresponding to a sum of the two currents for transmission in the 5G-NR band(s).
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: October 2, 2018
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat
  • Patent number: 10080190
    Abstract: A multi-band envelope tracking circuit is disclosed. The multi-band envelope tracking circuit includes a first radio frequency (RF) transceiver and a second RF transceiver, each configured to communicate one or more RF signals in one or more RF bands, and an envelope tracking signal corresponding to the one or more RF signals. The multi-band envelope tracking circuit includes a first envelope tracking signal path and a second envelope tracking signal path, each configured to amplify RF signal(s) in RF band(s) based on corresponding envelope tracking signal(s). Switching circuitry is provided and configured to provide the corresponding envelope tracking signal(s) to selected one or more of the first envelope tracking signal path and the second envelope tracking signal path. As such, the multi-band envelope tracking circuit can perform envelope tracking power amplification in various RF band combinations, thus supporting multi-band wireless communications with reduced power consumption and heat dissipation.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: September 18, 2018
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat
  • Patent number: 10056869
    Abstract: A control circuit of a power amplifier includes a peak detector, a first comparator, a first current source, a second comparator, a second current source and a bias circuit. The peak detector is arranged for detecting an amplitude of an input signal. The first comparator is arranged for comparing the amplitude of the input signal with a first threshold to generate a first comparing result. The first current source is arranged for generating a first current according to the first comparing result The second comparator is arranged for comparing the amplitude of the input signal with a second threshold to generate a second comparing result. The second current source is arranged for generating a second current according to the second comparing result. The bias circuit is arranged for generating a bias voltage according to the first current and the second current to the power amplifier.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: August 21, 2018
    Assignee: MEDIATEK INC.
    Inventors: Chien-Wei Tseng, Ming-Da Tsai
  • Patent number: 10050587
    Abstract: A power amplifier circuit includes unit amplifiers (unit PAs) whose output terminals are connected to one another, among which a number of unit PAs to be operated is controlled by an amplitude signal indicative of an amplitude of an input signal, and which output output signals based on a phase signal indicative of a phase of the input signal and an output current controller which controls an output current of each of the unit PAs. Each unit PA includes a first transistor and a second transistor connected in series between the output terminal and a ground. The first transistor receives the phase signal at a gate. The second transistor receives at a gate a control signal generated by the output current controller and determines the output current flowing to the output terminal on the basis of the control signal.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: August 14, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Kazuaki Oishi, Kouichi Kanda, Shiho Nakahara, Xiao-Yan Wang, Xiongchuan Huang
  • Patent number: 10020797
    Abstract: A phase shifter includes a first variable amplifier circuit configured to receive and amplify a first signal having a first phase; and a second variable amplifier circuit configured to receive and amplify a second signal having a second phase different from the first phase. The phase shifter is configured to generate an output signal having a desired phase by phase combination of an output of the first variable amplifier circuit and an output of the second variable amplifier circuit, and the first variable amplifier circuit and the second variable amplifier circuit each includes a plurality of amplifier circuit units. The amplifier circuit unit includes a first transistor with a grounded gate and a second transistor with a grounded source, and gains of the first variable amplifier circuit and the second variable amplifier circuit are specified according to the number of amplifier circuit units to be activated.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: July 10, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Ikuo Soga
  • Patent number: 10020786
    Abstract: Provided is a power amplification module that includes: an amplification transistor that has a constant power supply voltage supplied to a collector thereof, a bias current supplied to a base thereof and that amplifies an input signal input to the base thereof and outputs an amplified signal from the collector thereof; a first current source that outputs a first current that corresponds to a level control voltage that is for controlling a signal level of the amplified signal; and a bias transistor that has the first current supplied to a collector thereof, a bias control voltage connected to a base thereof and that outputs the bias current from an emitter thereof.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: July 10, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shota Ishihara, Yusuke Shimamune, Takashi Soga, Fuminori Morisawa, Seiko Ono, Tetsuaki Adachi
  • Patent number: 10009201
    Abstract: A wireless terminal and a receiver are provided that include a first amplifier configured to receive and amplify a first radio frequency (RF) input signal, and configured to output a first RF output signal corresponding to a first carrier included in a first frequency band. The receiver also includes a first sub amplifier configured to, when a mode signal indicates a first mode, receive a first internal signal from the first amplifier, amplify the first internal signal, and output a second RF output signal corresponding to a second carrier included in the first frequency band.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: June 26, 2018
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Young-min Kim, Pil-sung Jang, Thomas Byunghak Cho, Seung-chan Heo
  • Patent number: 9893686
    Abstract: Power amplifier with bias adjustment circuit. In some embodiments, a power amplifier can include an amplifying transistor configured to amplify a signal, and a bias circuit coupled to a bias node of the amplifying transistor and configured to provide a bias voltage at the bias node. The power amplifier can further include a bias adjustment circuit that couples an output node of the amplifying transistor and the bias circuit. The bias adjustment circuit can be configured to adjust the bias voltage in response to a potential difference between the output node and the bias node exceeding a threshold value.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: February 13, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventor: David Steven Ripley
  • Patent number: 9866959
    Abstract: A self-biasing output booster amplifier having an input amplifier stage, an output amplifier stage being operatively connected to an output of the input amplifier stage, and first and second current copying circuits. The second current copying circuit is biased from an output of the self-biasing output booster amplifier. The first and second current copying circuits are configured to copy at least a portion of the current through the output amplifier stage. The sum of the output of the second current copying circuit and the output of the output amplifier stage provides the output current of the self-biasing output booster amplifier, Finally, the input amplifier stage is biased from the output of the second current copying.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: January 9, 2018
    Assignee: Sonion Nederland B.V.
    Inventors: Michiel van Nieuwkerk, Yang Gao
  • Patent number: 9847765
    Abstract: A low noise amplifying system with adjustable gain. The low noise amplifier includes a plurality of gain stages, including a first stage and a last stage each having fixed gain, and an intermediate stage having adjustable gain. The intermediate stage is an inverting gain stage that includes a field effect transistor connected from the output to the input, to provide negative feedback, reducing the gain as a control voltage (applied to the gate of the field effect transistor) is adjusted to decrease the channel resistance of the field effect transistor. A control circuit measures the input and output signal power of the amplifying system and adjusts the gain of one or more intermediate stages to trade off linearity against noise figure.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: December 19, 2017
    Assignee: RAYTHEON COMPANY
    Inventors: Brian P. Helm, Brian L. Dillaman
  • Patent number: 9825594
    Abstract: A power amplification module includes: a first transistor that amplifies a first radio frequency signal and outputs a second radio frequency signal; a second transistor that amplifies the second radio frequency signal and outputs a third radio frequency signal; and first and second bias circuits that supply first and second bias currents to bases of the first and second transistors. The first bias circuit includes a third transistor that outputs the first bias current from its emitter or source, a capacitor that is input with the first radio frequency signal and connected to the base of the first transistor, a first resistor connected between the emitter or source of the third transistor and the base of the first transistor, a second resistor connected between the capacitor and the emitter or source of the third transistor, and a third resistor connected between the capacitor and the base of the first transistor.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: November 21, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazuo Watanabe, Satoshi Tanaka, Kazuhito Nakai, Takayuki Tsutsui
  • Patent number: 9800211
    Abstract: Methods and devices are described for compensating an effect of aging due to, for example, hot carrier injection, or other device degradation mechanisms affecting a current flow, in an RF amplifier. In one case a replica circuit is used to sense the aging of the RF amplifier and adjust a biasing of the RF amplifier accordingly.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: October 24, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Dan William Nobbe, Chris Olson, David Kovac
  • Patent number: 9780735
    Abstract: A high-frequency signal amplifier circuit is used in a front-end circuit configured to propagate a high-frequency transmission signal and a high-frequency reception signal, and includes an amplifier transistor configured to amplify the high-frequency transmission signal; a bias circuit configured to supply a bias to a signal input end of the amplifier transistor; and a ferrite bead, one end of which is connected to a bias output end of the bias circuit and the other end of which is connected to the signal input end of the amplifier transistor, having characteristics in which impedance in a difference frequency band between the high-frequency transmission signal and the high-frequency reception signal is higher than impedance in DC.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: October 3, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hidenori Obiya, Reiji Nakajima
  • Patent number: 9755594
    Abstract: A power amplifying circuit includes a switching circuit, an amplifier and a load. The switching circuit receives a first supply voltage and a second supply voltage. When the switching circuit is in a first operation mode, the first supply voltage is provided to a node. When the switching circuit is in a second operation mode, the second supply voltage is provided to the node. The amplifier receives a first input signal and a second input signal, and outputs a first output signal and a second output signal from a first output terminal and a second output signal, respectively. The load includes a first inductor and a second inductor. The first inductor is connected between the node and the first output terminal. The second inductor is connected between the node and the second output terminal.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: September 5, 2017
    Assignee: SHENZHEN SOUTH SILICON VALLEY MICROELECTRONICS CO., LIMITED
    Inventors: Pei-Si Wu, Hua-Yu Liao
  • Patent number: 9749119
    Abstract: Embodiments of a four-port isolation module are presented herein. In an embodiment, the isolation module includes a step-up autotransformer comprising a first and second winding that are electrically coupled in series at a center node. The first port of the isolation module is configured to couple an antenna to a first end node of the series coupled windings. The second port of the isolation module is configured to couple a balancing network to a second end node of the series coupled windings. The third port is configured to couple a transmit path to the center node. The fourth port is configured to couple a differential receive path across the first end node and the second end node. The isolation module effectively isolates the third port from the fourth port to prevent strong outbound signals received at the third port from saturating an LNA coupled to the fourth port.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: August 29, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Mohyee Mikhemar, Hooman Darabi
  • Patent number: 9742357
    Abstract: Embodiments of the disclosure may include a method and apparatus for improving the efficiency and extending the operation time between recharges or replacement batteries of a portable audio delivery system. The audio delivery system may include a processor, an audio processing device, a speaker, and a rechargeable power source. The audio delivery system is generally configured to generate and/or receive an audio input signal and efficiently deliver an amplified, high quality audio output signal to a user. In some embodiments of the disclosure, the audio processing device of the audio delivery system may include a switch mode power supply (SMPS), a signal delay element, an envelope detector, and a switching signal amplifier.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: August 22, 2017
    Assignee: Logitech Europe S.A.
    Inventors: Alan Olson, Sean Chiu, Jianhua Pan, Constantine Mouzakis, Jeffrey Anderson, Patrick Nicolet
  • Patent number: 9742364
    Abstract: In accordance with an embodiment, a circuit includes a low noise amplifier transistor disposed on a first integrated circuit, a single pole multi throw (SPMT) switch disposed on a second integrated circuit, and a bypass switch coupled between a control node of the low noise amplifier transistor and an output node of the low noise amplifier transistor. The SPMT switch couples a plurality of module input terminals to a control node of the low noise amplifier transistor, and the bypass switch including a first switch coupled between the control node of the low noise amplifier transistor and an intermediate node, a second switch coupled between the intermediate node and the output node of the low noise amplifier transistor, and a third switch coupled between the intermediate node and a first reference node. The first integrated circuit and the second integrated circuit are disposed on a substrate.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: August 22, 2017
    Assignee: Infineon Technologies AG
    Inventors: Nikolay Ilkov, Paulo Oliveira, Daniel Kehrer
  • Patent number: 9722552
    Abstract: A circuit that includes a Darlington transistor pair having an input transistor and an output transistor configured to generate an output signal at an output node in response to an input signal received through an input node is disclosed. The circuit has a feedback coupling network coupled between the output node and the input node for feeding back to the input node a portion of an amplified version of the input signal that passes through the input transistor. The circuit further includes a bias feedback network that includes a bias transistor and a resistive network that consists of only resistive elements such that no inductors and no capacitors are provided within the bias feedback network.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: August 1, 2017
    Assignee: Qorvo US, Inc.
    Inventor: Kevin Wesley Kobayashi
  • Patent number: 9722553
    Abstract: A high-frequency amplifier circuit comprising a first and a second amplification units connected in cascade structure and so on. The first amplification unit includes an FET of a first conductivity type having a source terminal supplied with a first potential, and a first inductor connected to an intermediate potential line, and the second amplification unit includes an FET of a second conductivity type having a source terminal supplied with a second potential, and a second inductor connected to the intermediate potential line. The intermediate potential line is supplied with an intermediate potential between the first and second potentials. The first and second amplification units are supplied with bias voltages by a first and a second bias units, respectively. An operating current for the second bias unit is controlled on the basis of the intermediate potential.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: August 1, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Tetsuaki Yotsuji
  • Patent number: 9705454
    Abstract: A circuit includes a bias circuit for a biased transistor. The bias circuit includes a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to the biased transistor and configured to provide a bias voltage. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. A signal ground circuit may be coupled between the biased transistor and one or more components of the bias circuit that do not generate significant return currents to a power supply ground. A method includes generating a current in a reference transistor according to a first voltage generated using a master source follower circuit, generating a second voltage substantially identical to the first voltage using a slave source follower circuit, and providing the second voltage to a biased transistor. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: July 11, 2017
    Assignee: Marvell World Trade, Ltd.
    Inventors: David M. Signoff, Ming He, Wayne A. Loeb
  • Patent number: 9692370
    Abstract: A biasing circuitry is disclosed. The biasing circuitry includes a biasing module, electrically connected to a power amplifier; and a control series, having an end electrically connected to a positive voltage, and another end electrically connected to the biasing module. The control series includes a switch unit, controlled by a control voltage to be on or off; and a voltage-drop unit, connected to the switch unit in series. The voltage-drop unit is configured to adjust a bias point of the power amplifier.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: June 27, 2017
    Assignee: WIN Semiconductors Corp.
    Inventors: Jui-Chieh Chiu, Fan-Hsiu Huang, Chih-Wen Huang
  • Patent number: 9673763
    Abstract: The present disclosure is to improve the power added efficiency of a power amplifier at high output power. The power amplifier includes: a first capacitor with a radio frequency signal input to one end thereof; a first transistor whose base is connected to the other end of the first capacitor to amplify the radio frequency signal; a bias circuit for supplying bias to the base of the first transistor; and a second capacitor with one end connected to the base of the first transistor and the other end connected to the emitter of the first transistor.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: June 6, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazuo Watanabe, Satoshi Tanaka, Norio Hayashi, Kazuma Sugiura
  • Patent number: 9667207
    Abstract: An apparatus for controlling a pulse width modulation (PWM) amplifier is disclosed. In one aspect, the apparatus includes a delay circuit configured to delay an input signal and provide the delayed input signal to the PWM amplifier. The apparatus also includes a controller configured to generate and provide a supply voltage to the PWM amplifier based at least in part on the input signal such that the PWM amplifier generates an output signal based at least partially on the delayed input signal and the supply voltage.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: May 30, 2017
    Assignee: KSC Industries, Inc.
    Inventor: Steven C. Moles
  • Patent number: 9654063
    Abstract: A bias circuit comprises: a first circuit that comprises a first resistor and a decoupling capacitor; a bias voltage generation circuit that comprises a first transistor being connected to the first circuit; one or more switches; a first replica circuit comprising a second circuit and a second transistor, the second circuit comprising a second resistor and a capacitor, the second transistor being connected to the second circuit; a second replica circuit comprising a third transistor; a comparator that makes a comparison between a pseudo-bias voltage and a reference voltage; and a control circuit that controls the one or more switches on the basis of the comparison result to reduce the amount of the current flowing through the first transistor.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: May 16, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yukio Okazaki, Masakatsu Maeda, Shigeki Nakamura, Akinori Daimo
  • Patent number: 9614477
    Abstract: The present disclosure is directed to an envelope tracking supply modulator for multiple PAs. The envelope tracking supply modulator is configured to provide, for each of the multiple PAs, a separate supply voltage that is modulated based on the envelope of the respective RF input signal to the PA. Each of the modulated supply voltages is constructed from a DC component and an alternating current (AC) component. The DC component for each modulated supply voltage is generated by a main switching regulator that is shared by the multiple PAs. In one embodiment, the AC component for each modulated supply voltage is generated by an auxiliary switching regulator that is shared by the multiple PAs and a separate linear regulator for each of the multiple PAs. In another embodiment, the AC component for each modulated supply voltage is generated by a separate buffer.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: April 4, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Dmitriy Rozenblit, Tirdad Sowlati, Ali Afsahi, Debopriyo Chowdhury, Sraavan R. Mundlapudi, Morteza Vadipour
  • Patent number: 9602056
    Abstract: An RF amplifier module that has a plurality of amplifiers wherein at least one of the amplifiers is powered via an envelope tracking module. The biasing input of at least one of the amplifiers is provided to the first amplifier to power the first amplifier to reduce power consumption. The first amplifier may also be powered via fixed biasing to provide greater stability of the module.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: March 21, 2017
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Philip John Lehtola
  • Patent number: 9590569
    Abstract: Systems, circuits and methods related to low power efficiency improvement in multi-mode multi-band power amplifiers. In some embodiments, a power-amplifier (PA) system can include a first amplification path having one or more PAs configured to generate a high power radio-frequency (RF) signal from an input RF signal when in a high power mode. The PA system can further include a second amplification path having one or more PAs configured to generate a low power RF signal from the input RF signal when in a low power mode. The PA system can further include a switching circuit coupled to the first amplification path and the second amplification path. The switching circuit can be configured to allow amplification of the input RF signal through the first amplification path in the high power mode or the second amplification path in the low power mode.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: March 7, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Philip H. Thompson, Michael Lynn Gerard, Ramanan Bairavasubramanian, David Anthony Sawatzky
  • Patent number: 9584072
    Abstract: An amplifier having a pair of transistors arranged in a cascode amplifier arrangement serially connected to a first voltage source. A DC bias regulator is provided having: a DC bias circuit for producing a reference voltage at a control electrode of a first one of the pair of transistors: and a voltage combiner having a pair of inputs, a first of the pair of inputs being coupled to the reference voltage and a second one of the pair of inputs being coupled to the first voltage source. The DC bias regulator produces a DC bias voltage at a control electrode of a second one of the pair of transistors related to a combination of the reference voltage and the first voltage source.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: February 28, 2017
    Assignee: RAYTHEON COMPANY
    Inventor: Valery S. Kaper
  • Patent number: 9577592
    Abstract: There is disclosed a method for controlling a power amplifier capable of utilizing nonlinearity correction in a nearly steady operation status of non-linearity correction, in a periodical fast switching system in time domain. The method may comprise receiving a periodic switch signal indicating switch time of the periodical fast switching system; and providing, based on the periodic switch signal, a pre-bias signal with a pre-determined voltage amplitude to the power amplifier for a pre-determined time period before each downlink time slot to preheat a transistor of the power amplifier so as to compensate a temperature change of a die inside the transistor.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 21, 2017
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Lei Liu, Linsheng Liu, Fan He, Wenjun Feng
  • Patent number: 9577626
    Abstract: Apparatus and methods for controlling radio frequency (RF) switches are disclosed. Provided herein are apparatus and methods for controlling RF switches. In certain configurations, an RF system includes a charge pump for generating a charge pump voltage, an RF switch, a level shifter for turning on or off the RF switch, and a level shifter control circuit for controlling the level shifter. The charge pump receives a mode signal used to enable or disable the charge pump. Additionally, the level shifter receives power in part from the charge pump voltage, and controls the RF switch based on a switch enable signal. The level shifter control circuit receives the mode signal and biases the level shifter with a bias voltage that changes based on a state of the mode signal.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: February 21, 2017
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Jonathan Christian Crandall, Kenneth Norman Warren, Philip H. Thompson
  • Patent number: 9559637
    Abstract: An envelope tracking power amplifier is disclosed herein. The envelope tracking power amplifier includes a multi-mode bias modulator and a power amplifier. The multi-mode bias modulator generates an envelope-modulated bias voltage from the envelope signal of an radio frequency (RF) signal whose power is to be amplified by using a linear amplifier and a switching amplifier each having varying current driving capability in response to an operation mode control signal that determines any one of low-level mode and high-level mode. The power amplifier is biased in response to the envelope-modulated bias voltage, amplifies the RF signal, and outputs the amplified RF signal to an antenna.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: January 31, 2017
    Assignee: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Youngoo Yang, Junghyun Ham
  • Patent number: 9548655
    Abstract: A differential dynamic charge pump circuit comprising; a first charging stage in series with a second charging stage; the first charging stage comprising a first circuit input for receiving an alternating clock signal; a second circuit input for receiving an inverted version of the alternating clock signal; a first output inverter arrangement configured to receive output voltages from upper and lower charge pump arrangements and having a first output and a second output for providing a dynamic differential output; the second charging stage comprising a first input and a second input configured to receive the output signal from the first stage; a second output inverter arrangement configured to receive output voltages from upper and lower charge pump arrangements and having a first output and a second output for providing a dynamic differential output of the circuit.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: January 17, 2017
    Assignee: NXP B.V.
    Inventors: Selcuk Ersoy, Robert Hendrikus Margaretha van Veldhoven
  • Patent number: 9525937
    Abstract: A circuit for suppressing audio output noise and an audio output circuit are provided. The circuit for suppressing audio output noise includes: a detecting circuit, configured to detect output voltages of output stages of an audio power amplifier; a control circuit, configured to output at least one control signal, the control signal is related to detection results of the detecting circuit; and a compensating circuit, configured to compensate at least one output stage of the audio power amplifier which includes a differential circuit based on the at least one control signal output by the control circuit, to make parameters of the differential circuit symmetrical or approach symmetrical. Based on detection results of the output stage voltages, the differential circuit in the output stages of the audio power amplifier is compensated. The circuit for suppressing audio output noise has a wider application scope and it is easy to design the circuit.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: December 20, 2016
    Assignee: SPREADTRUM COMMUNICATIONS (SHANGHAI) CO., LTD.
    Inventor: Xun Zhang
  • Patent number: 9496830
    Abstract: Various embodiments provide a radio frequency (RF) power amplifier (PA) circuit including an RF PA and a bias circuit. The bias circuit may provide a direct current (DC) bias voltage to the RF PA. The bias circuit may include a bias transistor, and the RF PA may include an amplifier transistor. The bias circuit may further include a diode coupled between a gate terminal of the amplifier transistor and a drain terminal of the bias transistor to pass the DC bias voltage to the gate terminal of the amplifier transistor and to level-shift the DC bias voltage at the gate terminal of the amplifier transistor to be higher than a DC voltage level at the drain terminal of the bias transistor.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: November 15, 2016
    Assignee: Qorvo US, Inc.
    Inventor: Kenneth W. Mays
  • Patent number: 9455670
    Abstract: A scalable periphery digital power control arrangement is presented. The scalable periphery digital power control arrangement comprises a plurality of PMOS transistors connected in parallel, where the plurality of transistors is operatively coupled to a voltage source. The plurality of PMOS transistors that is operatively coupled to the voltage source can operate as a controlled current source. Current flow from the voltage source can be controlled by a logic circuit, which sends a logic signal to enable or disable each individual PMOS transistor of the plurality of PMOS transistors connected in parallel. As more PMOS transistors are enabled, the current flow through the scalable periphery digital power control arrangement to the amplifier can increase.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: September 27, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventor: David Kovac
  • Patent number: 9444415
    Abstract: This disclosure relates generally to power amplification devices and methods of operating the same. The power amplification devices are capable of reducing (and possibly cancelling) modulation of a ripple variation of a supply voltage level of a supply voltage onto a radio frequency (RF) signal. In one embodiment, a power amplification device includes a power amplification circuit configured to amplify an RF signal with a supply voltage such that a ripple variation in a supply voltage level of the supply voltage is modulated onto the RF signal in accordance with a conversion gain. However, the power amplification device also includes a plurality of ripple rejection circuits. The plurality of ripple rejection circuits is configured to produce phase shifts and one or more amplitude shifts in the RF signal so as to reduce the conversion gain of the power amplification circuit.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: September 13, 2016
    Assignee: Qorvo US, Inc.
    Inventor: Andrew F. Folkmann
  • Patent number: 9407207
    Abstract: An radio frequency amplifying circuit includes an amplifying transistor configured to amplify a radio frequency signal input to a base of the amplifying transistor via a matching network to output the amplified radio frequency signal, a first bias transistor connected to the amplifying transistor based on a current-mirror connection to supply a bias to the amplifying transistor, and a second bias transistor connected to the base of the amplifying transistor based on an emitter-follower connection to supply a bias to the amplifying transistor.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: August 2, 2016
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takayuki Tsutsui, Satoshi Tanaka, Kenichi Shimamoto
  • Patent number: 9397618
    Abstract: A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: July 19, 2016
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kenichi Shimamoto, Satoshi Tanaka, Tadashi Matsuoka
  • Patent number: 9385901
    Abstract: A receiver front end architecture for intra band carrier aggregation is disclosed. In an exemplary embodiment, an apparatus includes a first transistor having a gate terminal to receive an input signal, drain terminal to output an amplified signal, and a source terminal connected to a signal ground by a source degeneration inductor. The apparatus also includes a second transistor having a source terminal connected to the drain terminal of the first transistor and a drain terminal connected to a first load. The apparatus also includes a third transistor having a gate terminal connected to the drain terminal of the first transistor, a drain terminal connected to a second load and a source terminal connected to a signal ground.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: July 5, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Gireesh Rajendran, Gurkanwal Singh Sahota, Rakesh Kumar
  • Patent number: 9362898
    Abstract: The invention provides an RF detection circuit and method using an envelope detector having an output connected to a first input of a differential amplifier and a reference storage capacitor to a second input of the differential amplifier. In a preferred implementation of the calibration mode, there is initial discharging of a reference storage capacitor, high speed charging of the reference storage capacitor until the differential amplifier output toggles, then slower discharging of the reference storage capacitor until the differential amplifier output toggles again. The resulting voltage is stored on the reference storage capacitor for use in a subsequent detection mode. This provides storage of an offset voltage which calibrates both the envelope detector differential amplifier functions.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: June 7, 2016
    Assignee: NXP B.V.
    Inventors: Lucie Chandernagor, Patrick Jean
  • Patent number: 9337787
    Abstract: Power amplifier circuitry includes a power amplifier including an input node and an output node, biasing circuitry, a selectable impedance network, and an input capacitor. The input capacitor is coupled to the input node of the power amplifier. The biasing circuitry is coupled to the input node of the power amplifier through the selectable impedance network. The power amplifier is operable in a low power operating mode and a high power operating mode. In the low power operating mode, the biasing circuitry delivers a first biasing current to the input node of the power amplifier, and a first impedance level of the selectable impedance is selected. In the high power operating mode, the biasing circuitry delivers a second biasing current to the input node of the power amplifier, and a second impedance level of the selectable impedance is selected.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: May 10, 2016
    Assignee: RF Micro Devices, Inc.
    Inventors: Derek Schooley, Alexander Wayne Hietala
  • Patent number: 9325360
    Abstract: A receiver for a wireless device is described. The receiver includes a low noise amplifier that includes differential inputs. The receiver also includes a mixer coupled to the low noise amplifier. The receiver further includes second-order intermodulation reduction circuitry coupled to a stage subsequent to the low noise amplifier. The second-order intermodulation reduction circuitry provides a biasing of the differential inputs.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: April 26, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Bahman Ahrari, I-Hsiang Lin