Abstract: An amplifying device includes a current generating circuit, a bias amplifying circuit, and a compensation circuit. The current generating circuit is configured to generate an internal current based on an internal voltage. The bias amplifying circuit, connected to the current generating circuit, is configured to output a bias current generated by amplifying the internal current to a power amplifying circuit. The compensation circuit, connected to the current generating circuit, is configured to adjust the internal voltage based on a bias voltage of the power amplifying circuit.

Abstract: A bias compensation circuit, coupled to an amplifying transistor, is disclosed. The bias compensation circuit comprises a voltage locking circuit, comprising a first terminal and a second terminal, wherein the first terminal is coupled to a third terminal the amplifying transistor, and the second terminal is coupled to a control terminal of the amplifying transistor; and a first resistor, coupled to the first terminal of the voltage locking circuit; wherein when the voltage locking circuit is conducted, a voltage difference between the first terminal and the second terminal is substantially constant.

Abstract: A power amplifier circuit includes an amplifier transistor having a first terminal supplied with a power supply voltage that changes in accordance with an amplitude level of an input signal, and a second terminal supplied with the input signal and a bias current, an amplified signal obtained by amplifying the input signal being outputted from the first terminal, a bias circuit that outputs the bias current from an output terminal thereof in accordance with a reference current supplied to an input terminal thereof, and a regulation circuit that generates a regulation current for regulating the bias current in accordance with a change in the power supply voltage. The regulation current increases with an increase in the power supply voltage, and decreases with a decrease in the power supply voltage. The regulation circuit extracts the regulation current from at least one of the reference current or the bias current.

Abstract: A bias circuit includes a bias current circuit and a temperature compensation circuit. The bias current circuit includes a first resistor and a first transistor, in a first current path connected between a current terminal of a reference current and a ground, and connected to each other in series, and a second transistor in a second current path connected between the current terminal and the ground, and having a base connected to a collector of the first transistor. The temperature compensation circuit includes a second resistor in the second current path, and connected between an emitter of the second transistor and a base of the first transistor and having a first thermal coefficient, and a third resistor included in the second current path, and connected between the base of the first transistor and the ground and having a second thermal coefficient, different from the first thermal coefficient.

Abstract: A filter includes a filter circuit, a first processing circuit, and a second processing circuit. The filter circuit receives an input signal from an input node of the filter, and converts the input signal into a voltage output. The first processing circuit provides a first control voltage to an output node of the filter according to the voltage output, wherein the first control voltage is derived from an alternating current (AC) component of the voltage output. The second processing circuit provides a second control voltage to the output node of the filter according to the voltage output, wherein the second control voltage is derived from applying DC level shift to a direct current (DC) component of the voltage output.

Abstract: A bias circuit includes a first branch circuit, a second branch circuit, a current amplifier and a switch, wherein the first branch circuit is configured to shunt an inputted first current, and input a first branch current of the first current to a power supply ground; the second branch circuit is configured to shunt the inputted first current, and input a second branch current of the first current to the current amplifier; the current amplifier is configured to receive the second branch current of the first current and amplify the second branch current of the first current to serve as a bias current of a power amplifier connected to the bias circuit for outputting; and the switch is configured to switch different resistance values for a resistor in the first branch circuit and/or switch different resistance values for a resistor in the second branch circuit.

Abstract: A power amplifier circuit includes a first transistor that amplifies a first signal and outputs a second signal, a second transistor that amplifies a signal corresponding to the second signal and outputs a third signal, a third transistor that supplies a first bias current or voltage to a base of the first transistor, and a fourth transistor that supplies a second bias current or voltage to a base of the second transistor. A ratio of an emitter area of the third transistor to an emitter area of the first transistor is larger than a ratio of an emitter area of the fourth transistor to an emitter area of the second transistor.

Abstract: A power amplifier circuit includes an amplifier transistor having a base, a collector, a bias circuit, and a first resistance element connected between the base of the amplifier transistor and the bias circuit. The bias circuit includes a voltage generation circuit, a first transistor having a base to which a first direct-current voltage is supplied, and an emitter from which the bias current or voltage is supplied, a second transistor having a base to which a second direct-current voltage is supplied, and an emitter connected to the emitter of the first transistor, a signal supply circuit disposed between the base of the amplifier transistor and the base of the second transistor, and an impedance circuit disposed between the base of the first transistor and the base of the second transistor.

Abstract: A bias circuit generates a bias current to an RF power amplifier used for transmitting RF signals, and the amount of the bias current supplied to the RF power amplifier can be configured in multiple modes through transistor switches that are controlled by mode control signals, so that the bias current supplied to the RF power amplifier can be adjusted according to the required power level of the transmitting RF signals. In addition, the bias current can be turned off by another transistor switch that is controlled by a power control signal for saving power while the RF power amplifier is not transmitting RF signals.

Abstract: Power conversion systems, disclosed examples include power conversion systems, ground fault detection apparatus and methods to detect and identify ground faults in a power conversion system using AC coupling to sense a system voltage to determine a leakage flux linkage, and to identify a faulted converter phase based on a phase shift angle of the leakage flux linkage.

Abstract: A radio frequency (RF) power limiter includes an input direct current (DC) block, an output DC block, a limiter diode, a RF choke, and a test diode. A first terminal of the limiter diode is coupled to a node between the input DC block and the output DC block, and a second terminal of the limiter diode is coupled to an electrical ground. A first terminal of the RF choke is coupled to the node between the input DC block and the output DC block so that the first terminal of the RF choke is coupled to the first terminal of the limiter diode. A first terminal of the test diode is coupled to the second terminal of the RF choke, and a second terminal of the test diode is coupled to the electrical ground.

Abstract: An amplification circuit includes an input terminal for receiving a radio frequency input signal, an output terminal for outputting an amplified radio frequency signal, a bias circuit for providing a bias voltage, an impedance circuit, a transistor, and a filter circuit. The impedance circuit is coupled to the bias circuit and the input terminal, and provides a voltage drop between the first terminal and the second terminal of the impedance circuit. The first transistor has a first terminal coupled to the output terminal, a second terminal coupled to a first reference voltage terminal, and a control terminal coupled to the impedance circuit and for receiving the radio frequency input signal. The filter circuit is coupled to the first transistor and the impedance circuit, filters out a harmonic signal, and provides a feedback signal including a primary frequency signal of the amplified radio frequency signal to the impedance circuit.

Abstract: A power amplifier circuit includes an amplifier transistor, a bias circuit that supplies a bias current or voltage to the amplifier transistor, and a resistance element connected between a base of the amplifier transistor and the bias circuit. The bias circuit includes a voltage generation circuit, a first transistor having a base to which a first direct-current voltage is supplied and an emitter from which the bias current or voltage is supplied, a second transistor having a base to which a second direct-current voltage is supplied and an emitter connected to the emitter of the first transistor, a signal supply circuit that supplies an input signal to the base of the second transistor, and an impedance circuit disposed between the base of the first transistor and the base of the second transistor.

Abstract: A power amplification circuit includes an amplification transistor, a variable voltage power supply that supplies a variable voltage to a collector of the amplification transistor, a bias circuit that has a constant current amplification transistor outputting a DC bias current to a base of the amplifier transistor, and a current limiting circuit that limits the DC bias current. The current limiting circuit includes a current limiting transistor, a resistor element connected to a collector of the current limiting transistor and the variable voltage power supply, and a resistor element connected to a base of the current limiting transistor and a base of the constant current amplifying transistor.

Abstract: Bias networks for amplifiers are disclosed. An example bias network includes an adaptive bias circuit, configured to generate a bias signal for an amplifier, and further includes a coupling circuit, configured to couple the adaptive bias circuit to the amplifier. The coupling circuit is made adaptive in that its' impedance depends on a power level of an input signal to be amplified by the amplifier. By configuring the coupling circuit to have a variable impedance that depends on the power level of the input signal, the coupling circuit may adapt to the input power level and, thereby, may modify the bias signal to reduce/optimize at least some of the nonlinearity that may be introduced to the bias signal by the adaptive bias circuit.

Abstract: A power amplification system with shared common base biasing is disclosed. A method for power amplification at a controller of a power amplification system comprising a plurality of cascode amplifier sections can include receiving a band select signal indicative of one or more frequency bands of a radio-frequency input signal to be amplified and transmitted. The method may further include biasing a common base stage of each of the plurality of cascode amplifier sections, and biasing a common emitter stage of a subset of the plurality of cascode amplifier sections.

Abstract: High frequency amplifier circuitry includes a common-source first transistor to amplify a high-frequency input signal, a common-gate second transistor cascade-connected to the first transistor, to amplify a signal amplified by the first transistor to generate an output signal, a first inductor connected between a source of the first transistor and a first reference potential node, a second inductor connected between a drain of the second transistor and a second reference potential node, and non-linear compensation circuitry connected to a connection node of the first transistor and the second transistor, to compensate for non-linearity of the output signal to the high-frequency input signal. The non-linear compensation circuitry has first rectifier circuitry, a first resistor, a second resistor, second rectifier circuitry, first capacitor and second capacitor.

Abstract: There is provided a power amplifier and an integrated circuit including the power amplifier. The power amplifier includes a first amplifier configured to amplify a first signal; a phase shifter configured to invert the first signal; and a harmonic sinker connected between an output terminal of the phase shifter and an output terminal of the first amplifier, configured to amplify an output signal of the phase shifter, and configured to have a conduction angle narrower than a conduction angle of the first amplifier.

Abstract: The present disclosure provides a power amplifier circuit capable of suppressing the occurrence of noises while enabling control of an output power level. The power amplifier circuit includes a first transistor that amplifies a first signal; a bias circuit that supplies a bias current or voltage based on a control signal to the first transistor; a second transistor to which a control current based on the control signal is supplied, which has an emitter or a source thereof connected to a collector or a drain of the first transistor, and from which a second signal obtained by amplifying the first signal is output; and a first feedback circuit provided between the collector or the drain of the second transistor and the base or the gate of the second transistor.

Abstract: A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. A output passive network can further generate a flat-phase response between dual resonances of operation.

Abstract: Embodiments of the present disclosure provide circuitry and a method for a gallium nitride (GaN) device. The circuitry includes a negative bias circuit configured to provide a negative bias voltage for a gate of the GaN device; a drain switch circuit configured to turn on or off a positive voltage for a drain of the GaN device; and a control circuit configured to control the drain switch circuit based on provision of the negative bias voltage, such that the positive voltage for the drain is turned on after a voltage of the gate reaches the negative bias voltage and turned off before the negative bias voltage completely disappears.

Abstract: A power module includes a number of sub-modules connected via removable jumpers. The removable jumpers allow the connections between one or more power semiconductor die in the sub-modules to be reconfigured, such that when the removable jumpers are provided, the power module has a first function, and when the removable jumpers are removed, the power module has a second function. The removable jumpers may also allow for independent testing of the sub-modules. The power module may also include a multi-layer printed circuit board (PCB), which is used to connect one or more contacts of the power semiconductor die. The multi-layer PCB reduces stray inductance between the contacts and therefore improves the performance of the power module.

Abstract: Circuits and methods for reducing the cost and/or power consumption of a user terminal and/or the gateway of a telecommunications system (550) that may include a telecommunications satellite. Embodiments generate a dynamic input bias signal based upon an information signal envelope (which may be pre-distorted) which is applied to the signal input of a power amplifier (PA), thus reducing average power consumption. Other embodiments further include dynamic linearization (518) of the information signal, and/or variation of the supply voltage to the power amplifier (PA) as a function of the envelope of the information signal. Another aspect is a multi-stage “chained” feedback regulated voltage supply circuit for providing two or more output voltages that may be used as alternative supply voltages to a power amplifier (PA).

Abstract: An amplifier device includes an amplifying unit, a bias module, an impedance unit and an adjusting module. The amplifying unit has a first end coupled to a voltage source and used for outputting an output signal amplified by the amplifying unit, a second end used for receiving an input signal, and a third end coupled to a first reference potential terminal. The bias module is coupled to the second end of the amplifying unit, and provides a bias voltage to the amplifying unit and adjusts linearity of the amplifier device according to a source voltage from the voltage source. The impedance unit is coupled to the bias module and used to receive a control voltage to adjust an impedance value of the impedance unit. The adjusting module is used to output the control voltage to the impedance unit according to the source voltage and a reference voltage.

Abstract: A power amplifier circuit includes a first transistor having a base to which a radio frequency (RF) signal is supplied and a collector to which a variable power-supply voltage corresponding to a level of the RF signal is supplied, and being configured to amplify the RF signal; a bias circuit including a second transistor configured to supply a bias current to the base of the first transistor; and an adjustment circuit configured to cause the bias current to be supplied to the base of the first transistor to decrease with decrease in the variable power-supply voltage by causing a current to be supplied to a base of the second transistor to decrease.

Abstract: An apparatus includes an amplifier and a gain control circuit. The amplifier may be configured to provide multiple gain steps. The gain control circuit may be configured to provide fast and precise changes between the multiple gain steps of the amplifier. The gain control circuit may be further configured to change an impedance of the amplifier to switch between the gain steps. The gain control circuit may be further configured to compensate for changes in frequency response related to changing the impedance. The gain control circuit may be further configured to inject a complementary charge to an input of the amplifier to correct a bias voltage deviation and a transient caused by the gain control circuit.

Abstract: The present disclosure relates to a power amplifier circuit including a current source, a power control circuit, a current mirror and an output circuit. The current source circuit includes a first transistor and a second transistor. A source of the first transistor is connected to a drain of the second transistor and a gate of the first transistor is connected to a source with the second transistor. The power control circuit is connected to a gate of the second transistor. The current mirror circuit is connected to the gate of the first transistor and a source of the second transistor. The output circuit is connected to the current mirror circuit.

Abstract: Apparatus and methods for low noise amplifiers (LNAs) are provided herein. In certain configurations, an LNA includes a mode control circuit that operates the LNA in one of a plurality of modes including a gain mode and a bypass mode, a gain circuit electrically connected between an input terminal and an output terminal and operable to amplify a radio frequency signal received from the input terminal in the gain mode, and a bypass circuit electrically connected between the input terminal and the output terminal and operable to bypass the gain circuit in the bypass mode. The bypass circuit includes a balun that provides a first amount of compensation for a difference in phase delay between the bypass circuit and the gain circuit, and the LNA further includes a phase compensation circuit operable to provide a second amount of compensation for the difference in phase delay.

Abstract: A power amplifier circuit includes an amplifier transistor having a base, a collector, a bias circuit, and a first resistance element connected between the base of the amplifier transistor and the bias circuit. The bias circuit includes a voltage generation circuit, a first transistor having a base to which a first direct-current voltage is supplied, and an emitter from which the bias current or voltage is supplied, a second transistor having a base to which a second direct-current voltage is supplied, and an emitter connected to the emitter of the first transistor, a signal supply circuit disposed between the base of the amplifier transistor and the base of the second transistor, and an impedance circuit disposed between the base of the first transistor and the base of the second transistor.

Abstract: A method and apparatus for a dual-feedback, amplifier limiter for providing a conditioned radio-frequency signal. The dual-feedback, amplifier limiter includes an input that receives a radio-frequency signal and a stacked amplifier including an input node coupled to the input, an output node, a first transistor configured as a common-base amplifier, and a second transistor configured as a common-emitter amplifier. The dual-feedback, amplifier limiter further includes an output coupled to the output node of the stacked amplifier. The output provides the conditioned radio-frequency signal. The dual-feedback, amplifier limiter further includes a radio-frequency feedback circuit coupled to the stacked amplifier. The radio-frequency feedback circuit includes a passive radio-frequency dependent reactive element in series with a radio-frequency feedback circuit resistor.

Abstract: Power conversion systems, ground fault detection apparatus and methods to detect and identify ground faults in a power conversion system using AC coupling to sense a system voltage to determine a leakage flux linkage, and to identify a faulted converter phase based on a phase shift angle of the leakage flux linkage.

Abstract: Power consumption of a signal processing circuit is reduced. Further, power consumption of a semiconductor device including the signal processing circuit is reduced. The signal processing circuit includes a reference voltage generation circuit, a voltage divider circuit, an operational amplifier, a bias circuit for supplying bias current to the operational amplifier, and first and second holding circuits. The first holding circuit is connected between the reference voltage generation circuit and the bias circuit. The second holding circuit is connected between the voltage divider circuit and a non-inverting input terminal of the operational amplifier. Reference voltage from the reference voltage generation circuit and reference voltage from the voltage divider circuit can be held in the first and second holding circuits, respectively, so that the reference voltage generation circuit can stop operating. Thus, power consumption of the reference voltage generation circuit can be reduced.

Abstract: There are disclosed various methods and apparatuses for providing power to a set of power amplifiers. In some embodiments the method comprises obtaining first transmission parameters associated with a first transmit signal, selecting one or more output voltage values on the basis of the first transmission parameters, controlling a multi-level power source to generate one or more output voltages on the basis of the one or more output voltage values, multiplexing based on the first transmit signal between two or more of the output voltages and a first supply voltage terminal of a first power amplifier, and amplifying the first transmit signal with the first power amplifier.

Abstract: Configurable adjustment of a power amplifier bias for a power amplifier. The power amplifier may be comprised within a variety of different apparatuses, such as without limitation a remote PHY node, a remote MACPHY node, and a wireless communication device. A processing unit, disposed within an apparatus, instructs an electrical circuit, also disposed within said apparatus, to change an RF signal output power carrying capability of the power amplifier based on a configuration. The configuration may, but need not, be maintained within the apparatus. The change in the RF signal output power carrying capability of the power amplifier causes an adjustment in a power consumption of the power amplifier.

Abstract: Provided is a communication unit that includes first and second power-amplification modules, which can be integrated. The first power-amplification module includes a first power-amplifier for a first frequency band in a first communication scheme, a second power-amplifier for a second frequency band in the first communication scheme, a third power-amplifier for a third frequency band in a second communication scheme, a fourth power-amplifier for a fourth frequency band in the second communication scheme, a first bias circuit that generates a first bias current to the first and second power-amplifiers, and a bias current circuit that converts the first bias current into a second bias current to the third and fourth power-amplifiers. The second power-amplification module includes a fifth power-amplifier for a fifth frequency band in the first communication scheme, and a second bias circuit that generates a third bias current to the fifth power-amplifier.

Abstract: A power amplification circuit includes: a first amplification transistor, a first signal being input to a base or gate thereof and a second signal obtained by amplifying the first signal being output from a collector or drain thereof; and a first bias circuit that supplies a first bias current to the base or gate of the first amplification transistor. The first bias circuit includes a first transistor that outputs the first bias current from an emitter or source thereof, and a first control circuit that controls an electrical connection between the emitter or source of the first transistor and ground. The first control circuit includes a first resistance element and a first switch element, which are connected in series with each other. The first switch element is switched on in the case of a first power mode and is switched off in the case of a second power mode.

Abstract: A wireless transmitter includes a an amplifier; and a switchable transformer, coupled to the amplifier, wherein the amplifier is configured to be coupled to the switchable transformer in first and second configurations, wherein the first configuration causes the amplifier to provide a first output impedance to the switchable transformer, and wherein the second configuration causes the amplifier to provide a second output impedance to the switchable transformer, the first and second output impedances being different from each other.

Abstract: A wireless device includes a radio-frequency module, a modem module, and a control unit. The radio-frequency module and the modem module operate either in a first operation mode or in a second operation mode. The control unit, coupled to the RF and the modem module, generates a control signal to indicate to the RF and the modem module to operate in the first operation mode or to operate in the second operation mode. A first set of signal formats corresponding to the first operation mode is a superset of a second set of signal formats corresponding to the second operation mode, and a first power consumption corresponding to the first operation mode is higher than a second power consumption corresponding to the second operation mode.

Abstract: Systems and methods for automatically controlling the bias in a pulsed power amplifier include components for measuring the current in an amplifier, comparing the measured value with the desired value, modifying the bias, and controlling the bias applied to the power amplifier. A measurement circuit converts the measured current to a voltage, and a comparator compares a measured voltage with a reference voltage to continuously indicate whether the amplifier current is less than a desired quiescent value. A circuit controls the level of the gate-bias (Vg) during a pulse, such as with a pulse width modulator. The measurement of the amplifier current is registered after the bias is enabled, but before the signal pulse. Drive control logic implements a control algorithm for adjusting the gate value in between pulses and in time to be used for the next pulse.

Abstract: Apparatus and methods for envelope tracking systems with automatic mode selection are provided herein. In certain configurations, a power amplifier system includes a power amplifier configured to provide amplification to a radio frequency signal and to receive power from a power amplifier supply voltage, and an envelope tracker including a signal bandwidth detection circuit configured to generate a detected bandwidth signal based on processing an envelope signal corresponding to an envelope of the radio frequency signal. The envelope tracker further includes a switch bank configured to receive a plurality of regulated voltages, a filter configured to filter an output of the switch bank to generate the power amplifier supply voltage, and a mode control circuit configured to control a filtering characteristic of the filter based on the detected bandwidth signal.

Abstract: A Biphase Mark Coding (BMC) transceiver is provided. In the BMC transceiver, an operational amplifier operating in a time division multiplexing manner is used. The operational amplifier is configured as a unity gain buffer, and it is determined whether the BMC transceiver operates as a transmitter or a receiver by selecting different input switches and output switches. In a transmitting mode, a bias current of an input differential pair transistor of the operational amplifier is changed, to change a slew rate, so as to obtain an output waveform with adjustable rising/falling edges of the transmitter.

Abstract: A method for reducing reverse power reflected from a plasma load to a high frequency power amplifier includes determining a sign of a slope of an output frequency outputted from the high frequency power amplifier; determining a sign of a slope of reverse power reflected from the plasma load to the high frequency power amplifier; deciding an increase or a decrease in an amount of frequency change according to a combination of the sign of the slope of the output frequency and the sign of the slope of the reverse power; updating the output frequency by using the amount of the frequency change, and changing the output frequency in order to escape from a hump when a reflection coefficient is larger than a predetermined reflection reference value and the amount of the frequency change is smaller than a predetermined variation width setting value.

Abstract: A reconfigurable low-noise amplifier (LNA) is disclosed. The reconfigurable LNA includes amplifier circuitry having a gate terminal coupled to an input terminal, a source terminal coupled to a fixed voltage node, and a drain terminal coupled to an output terminal. The reconfigurable LNA further includes a gamma inverting network (GIN) coupled between the input terminal and the fixed voltage node, wherein the GIN has a first switch configured to disable the GIN during operation at first frequencies within a lower frequency band relative to a higher frequency band and to enable the GIN during operation at second frequencies within the higher frequency band.

Abstract: A circuit topology including stacked power amplifiers (e.g., class D PA cells) in a ladder arranged in a house-of-cards topology such that the number of stacked-domains follows a decaying triangular series N, N?1, N?2, . . . , N?i from a fixed ladder to an ith ladder to provide a 1:(i+1) voltage conversion ratio, each stacked domain outputs its power via a flying domain power amplifier cell, and each ladder balances stacked domains of a prior ladder and combines power from all prior ladders.

Abstract: An amplifier device includes an amplifying unit, a bias module and an impedance unit. A first end of the amplifying unit electronically connects to a voltage source. A second end of the amplifying unit receives an input signal. The first end of the amplifying unit outputs an output signal amplified by the amplifying unit. A third end of the amplifying unit connects to a first reference potential. The bias module electrically connects to the second end of the amplifying unit for providing a bias voltage to the amplifying unit. An impedance unit is electrically connects to the bias module. An impedance value of the impedance unit is variable. The bias module adjusts the amplifier's linearity according to a frequency value of the input signal, a voltage value of the voltage source or a temperature value of the amplifier device. The impedance is adjusted according to the above-mentioned values.

Abstract: Embodiments disclosed herein relate to a bias circuit that uses Schottky diodes. Typically, a bias circuit will include a number of transistors used to generate a bias voltage or a bias current for a power amplifier. Many wireless devices include power amplifiers to facilitate processing signals for transmission and/or received signals. By substituting the bias circuit design with a design that utilizes Schottky diodes, the required battery voltage of the bias circuit may be reduced enabling the use of lower voltage power supplies.

Abstract: An RF power amplifier biasing circuit has a start ramp signal input, a main current source input, an auxiliary current source input, and a circuit output. A ramp-up capacitor is connected to the auxiliary current source input. A ramp-up switch transistor is connected to the start ramp signal input and is selectively thereby to connect the auxiliary current source input to the ramp-up capacitor. A buffer stage has an input connected to the ramp-up capacitor and an output connected to the main current source input at a sum node. A mirror transistor has a gate terminal corresponding to the circuit output and a source terminal connected to the sum node and to the gate terminal.

Abstract: A supply modulator for providing a first power supply voltage and a second power supply voltage to a first power amplifier and a second power amplifier, respectively, includes a first modulation circuit including a linear regulator and a switching regulator, the first modulation circuit being configured to generate a first modulation voltage in accordance with envelope tracking, and provide the first modulation voltage to the first power amplifier as the first power supply voltage; and a single inductor multiple output converter configured to generate a first output voltage and a second output voltage based on an input voltage having a fixed level, provide the first output voltage to the linear regulator of the first modulation circuit as a power supply voltage, and provide the second output voltage to the second power amplifier as the second power supply voltage.

Abstract: A gate drive circuit includes a lower limit clamping circuit, an upper limit clamping circuit, and an averaging circuit. The lower limit clamping circuit clamps the input node of a transistor at a minimum voltage with respect to the common node of the transistor, while the upper limit clamping circuit clamps the input node of the transistor at a maximum voltage with respect to the common node of the transistor and the averaging circuit sets the average voltage of the input node with respect to the common node over a specified period of time. The transistor including a common node, an output node and an input node receives the input signal. Controlling the upper limit, lower limit and average value in conjunction with fast transitions between the lower and upper limits controls the duty cycle of the input signal.

Abstract: A radio frequency (RF) power detector includes a first circuit having a first rectifying diode with a first terminal coupled to a first power supply voltage node. The first circuit also includes an input terminal coupled to a second terminal of the first rectifying diode, a first transistor having a first collector coupled to the second terminal of the first rectifying diode and a first emitter coupled to a reference voltage node, and a second transistor having a second emitter coupled to the reference voltage node and a second collector coupled to a second power supply voltage node. The first circuit further includes a low-pass filter network coupled between a first base of the first collector and a second base of the second transistor, and a first output terminal coupled to the second collector of the second transistor.