Abstract: The present disclosure relates to a system for biasing a power amplifier. The system can include a first die that includes a power amplifier circuit and a passive component having an electrical property that depends on one or more conditions of the first die. Further, the system can include a second die including a bias signal generating circuit that is configured to generate a bias signal based at least in part on measurement of the electrical property of the passive component of the first die.

Abstract: Designs and techniques for improving the linearity of the power amplifiers, especially of the non-linear types, operated in microwave and millimeter-wave frequency using method through purposely designed active transistors or passive devices or both, are disclosed. The techniques use the manipulation of transistors' cut-off frequencies (fT) design, attached loaded linearization stub and characteristics of space attenuation of microwave signals individually or in combination of them. The disclosed techniques provide the advantages to compromise the performance among linearity, gain and power consumption in a wide range of power amplifier types, such as Class- AB, B, C, D, E and F in the different application scenarios.

Abstract: An apparatus for amplifying a signal is provided. The apparatus includes a carrier transistor, a peaking transistor, a controller, and a power supply switching unit, wherein the controller controls the power supply switching unit to switch between two or more power supplies and wherein the power supply switching unit provides power from one of the two or more power supplies to the peaking transistor.

Abstract: There is provided a bias arrangement for an amplifier adapted to amplify a varying input signal, the arrangement comprising a control circuit arranged to adaptively vary a bias current to the amplifier in dependence on an envelope of the varying input signal.

Abstract: A low voltage, switch mode PHEMT power amplifier with a 0.1 ?m gate length and a low loss, lumped element, output matching circuit is disclosed that provides high performance over a frequency range of 1.4 GHz-2.5 GHz. The amplifier makes use of monolithic circuit technology for the first stage and output transistor, and uses a printed circuit board with surface mount components for the output matching network. The power output of the power amplifier is stable over a range of 60 degrees centigrade, has high power efficiencies of 44-53% with greater than 2 watts output power over the frequency range of 1.4 GHz and 2.5 GHz. In addition, through drain voltage control, the output power can be varied over a wide range between about 0.8 to 2.5 watts while still maintaining a high efficiency in the range of 50±3%.

Abstract: There are provided a bias circuit supplying different levels of bias power according to respective power modes through a simple circuit configuration, and a power amplifier having the same. The bias circuit includes: a bias setting unit setting a bias power voltage level by switching reference power having a pre-set voltage level determined according to a pre-set power mode; and a bias supply unit including a switching element performing switching according to the setting of the bias setting unit and supplying bias power having a voltage level determined according to a switching operation of the switching element.

Abstract: Methods and systems for a configurable front end are disclosed. Aspects of one method may include a transceiver on a single chip that may comprise a power amplifier (PA) and a low noise amplifier (LNA). The PA may amplify signals to be transmitted over a range of output transmit power. An upper limit for a power range may of substantially 12 dBm. The LNA may be tolerant to PA signals by, for example, being configured to follow signal voltages generated from an output of the power amplifier. For example, each input transistor of the LNA may be isolated from other transistors in the LNA. Accordingly, the input transistors may float since they may not be tied to a voltage level via other transistors. This may allow the input transistors to avoid damage. The transceiver may also be configured for differential RF input, differential RF output, single-ended RF input, and/or single-ended RF output.

Abstract: An apparatus according to an embodiment of the present invention includes a conversion unit configured to generate electric charge, a first amplification unit configured to amplify a signal corresponding to an amount of the electric charge and output a first amplified signal, a second amplification unit configured to amplify the first amplified signal and output a second amplified signal, a current source shared by the first amplification unit and the second amplification unit, and a selection unit configured to bring the first amplification unit and the second amplification unit into an inactive state. The current source is shared by the first amplification unit and the second amplification unit. The number of current sources is therefore reduced. This leads to the reduction in power consumption.

Abstract: A low-noise amplifier (300) is provided which comprises an input circuit (301) configured to operate with a variable bias current and an impedance boosting circuit (314) electrically connected to the input circuit (301). The impedance boosting circuit (314) comprises at least one switch (316) and at least one tail inductor (318) electrically connected with the at least one switch (316). The low-noise amplifier (300) is configured to activate the impedance boosting circuit (314) if the variable bias current is reduced, and the impedance boosting circuit (314) is configured to increase the input impedance of the low-noise amplifier (300) if the impedance boosting circuit (314) is activated.

Abstract: Combination circuitry includes a relatively small preamplifier and includes hybrid circuitry. The hybrid circuitry is configured to perform mode switching while also performing some amplification, thus allowing the relatively small preamplifier to be smaller than a conventional power amplifier. In one embodiment, the hybrid circuitry includes first series portion configured to amplify when ON, a first shunt portion, a second series portion configured to amplify when ON, and a second shunt portion. The first series portion may include: a first transistor; a first variable impedance in communication with a gate of the first transistor, wherein the first variable impedance is configured to receive a first transistor control signal; a second transistor in series with the first transistor; and a second variable impedance in communication with a gate of the second transistor, wherein second variable impedance is configured to receive a second transistor control signal.

Abstract: An improved regulator circuit, temperature compensation bias circuit, and amplifier circuit are disclosed.

Abstract: Examples of systems and methods are provided for converting an analog input signal to a digital output signal. A system may include a current mode (CM) digital-to-analog converter (DAC) circuit to provide a DAC current. A comparator circuit may be configured to generate a comparator signal in response to an error signal determined based on the DAC current and the analog input signal. A successive approximation register circuit may be configured to generate at least one of a DAC-code signal or the digital output signal, in response to the comparator signal. The DAC-code signal may be used by the CM DAC circuit to control the DAC current.

Abstract: Devices and methods for correcting for start-up transients in integrated power amplifiers are disclosed. A delay element is arranged to produce a delay waveform signal that is responsive to an input voltage signal. A transconductance element has an input that receives the delay waveform signal and is arranged to provide an output boost current that is based on the delay waveform signal and a gain of the transconductance element. A reference element provides an output bias current that is responsive to a static reference current and the boost current. A bias element has an input that receives the bias current and is arranged to provide a bias control output. A power amplifier is responsive to the bias control output and is arranged to provide an amplified power output.

Abstract: An amplifier includes a first lower active sub cell and a second lower active sub cell, each comprising an input terminal and an output terminal, wherein the input terminals of the lower active sub cells are connected to the amplifier input and the output terminals of the lower active sub cells are not shorted. Furthermore, the amplifier includes a first upper active sub cell and a second upper active sub cell, each including a biasing terminal, wherein the input terminals and the output terminals of the upper active sub cells are coupled between the output terminals of the lower active sub cells and the amplifier output. The amplifier includes a bias controller configured to provide a first biasing signal to the first upper active sub cell and a second biasing signal to the second upper active sub cell based on an output power of the output signal.

Abstract: A radio frequency (RF) power amplifier includes: a pre-stage amplifier configured to amplify an input power to the RF power amplifier; and a post-stage amplifier configured to amplify an output power of the pre-stage amplifier; wherein the pre-stage amplifier comprises a CMOS (Complementary Metal Oxide Semiconductor) amplifier, and the post-stage amplifier comprises a GaAs (Gallium Arsenide) amplifier or a SiGe (Silicon Germanium) amplifier.

Abstract: Illustrative embodiments of power amplifiers and associated methods are disclosed. In at least one embodiment, a method may include fabricating a power amplifier in a first silicon layer of a silicon-on-insulator (SOI) substrate, wherein the SOI substrate comprises the first silicon layer, a second silicon layer, and a buried oxide layer disposed between the first and second silicon layers; removing at least some of the second silicon layer from the SOI substrate, after fabricating the power amplifier; and securing the SOI substrate, after removing at least some of the second silicon layer, to an electrically non-conductive and thermally conductive substrate.

Abstract: A system for preventing power amplifier supply voltage saturation includes a multiple stage voltage regulator configured to provide a regulated voltage, a power amplifier configured to receive the regulated voltage, and a saturation protection circuit configured to apply a current into a first stage of the multiple stage voltage regulator when the regulated voltage reaches a reference voltage, the applied current causing a subsequent stage of the multiple stage voltage regulator to prevent the regulated voltage from exceeding the reference voltage.

Abstract: An amplifier circuit, comprising: an input, for receiving an input signal to be amplified; a power amplifier, for amplifying the input signal; a switched power supply, having a switching frequency, for providing at least one supply voltage to the power amplifier; and a dither block, for dithering the switching frequency of the switched power supply. The dither block is controlled based on the input signal. Another aspect of the invention involves using first and second switches, each having different capacitances and resistances, and using the first or second switch depending on the input signal or volume signal. Another aspect of the invention involves controlling a bias signal provided to one or more components in the signal path based on the input signal or volume signal.

Abstract: According to one embodiment, provided are an amplifier transistor configured to amplify an input signal; a biasing circuit configured to set a bias voltage in such a manner as to allow the amplifier transistor to perform amplification; an electrostatic protective circuit configured to set the bias voltage for the amplifier transistor in such a manner as to make the amplifier transistor to turn off based on voltage to be applied to the amplifier transistor; and a switching circuit configured to switch the bias voltage for the amplifier transistor based on a power supply condition.

Abstract: Provided is a compact high frequency power amplifier having a high degree of freedom of design with respect to a gain fluctuation immediately after start-up of an amplifier. The high frequency power amplifier includes a speed-up circuit that transiently increases a reference voltage during rise of a control voltage to increase an amount of bias supplied to an amplification transistor from a bias circuit. The speed-up circuit includes a capacitor and an overshoot control circuit. The overshoot control circuit determines an increasing amount of the reference voltage when the reference voltage is transiently increased according to a charge amount charged in the capacitor, and the overshoot control circuit also determines a time constant in charging and discharging the capacitor.

Abstract: A power amplifier includes generation, tracking and usage of an envelope of an input RF signal. To improve upon the efficiency of the power amplifier, various configurations include using the tracked envelope, for example, an OFDM signal, to improve the average efficiency. Suitable hardware/software in the form of circuitry, logic gates, and/or code functions to generate and track an envelope of an input RF signal and modulate one or more of the input supply voltage, cascode gate bias or parallel PA branches using the tracked envelope.

Abstract: According to one embodiment, a circuit for compensating fluctuation of a base current of a transistor is presented. The transistor has a base connected with an input terminal. The compensation circuit is provided with a first transistor, a current mirror circuit and a second transistor. The current mirror circuit mirrors a current which is supplied to a base of the first transistor. Further, the current mirror circuit supplies the obtained mirror current to the base of the transistor to be compensated. A base of the second transistor is connected with the input terminal electrically. The second transistor causes an early effect in the first transistor.

Abstract: A low-noise amplifier includes a first transistor having a gate configured to receive an oscillating input signal and a source coupled to ground. A second transistor has a source coupled to a drain of the first transistor, a gate coupled to a bias voltage, and a drain coupled to an output node. At least one of the first and second transistors includes a floating deep n-well that is coupled to an isolation circuit.

Abstract: A radio frequency (RF) switch semiconductor die and an RF supporting structure are disclosed. The RF switch semiconductor die is attached to the RF supporting structure. The RF switch semiconductor die has a first edge and a second edge, which may be opposite from the first edge. The RF supporting structure has a group of alpha supporting structure connection nodes, which is adjacent to the first edge; a group of beta supporting structure connection nodes, which is adjacent to the second edge; and an alpha AC grounding supporting structure connection node, which is adjacent to the second edge. When the group of alpha supporting structure connection nodes and the alpha AC grounding supporting structure connection node are active, the group of beta supporting structure connection nodes are inactive.

Abstract: Disclosed herein is a driver amplifier circuit, including: a first current source transistor of a first conductivity type, and a second current source transistor of the first conductivity type, control voltages being supplied to gates of the first current source transistor and the second current source transistor, respectively; a first switching transistor of the first conductivity type, and a second switching transistor of the first conductivity type; a third switching transistor of a second conductivity type, and a fourth switching transistor of the second conductivity type; first, second, third, and fourth resistor elements; and a first output node and a second output node.

Abstract: A voltage buffer having a first transistor, a second transistor, a third transistor and a voltage detector is provided. A first terminal of the first transistor is coupled to a first reference voltage. A first terminal of the second transistor is coupled to a second terminal of the first transistor, a control terminal of the second transistor is coupled to an input voltage, and a second terminal of the second transistor is coupled to an output voltage. A first terminal of the third transistor is coupled to a second terminal of the second transistor. A second terminal of the third transistor is coupled to a second reference voltage. The voltage detector detects a voltage of the second terminal of the first transistor to generate a detection result and outputs the detection result to a bulk terminal of the second transistor.

Abstract: An adaptive amplification circuit is disclosed, which includes an operational amplifier including a variable bias current source for providing a variable bias current for the operational amplifier, a simulation unit for simulating operational characteristics of the operational amplifier and transforming a simulation input voltage to a simulation output voltage, and a bias control unit for generating a bias control signal to the variable bias current source according to the simulation output voltage so as to adjust the variable bias current.

Abstract: The present disclosure relates to a direct current (DC)-DC converter, which includes a charge pump based radio frequency (RF) power amplifier (PA) envelope power supply and a charge pump based PA bias power supply. The DC-DC converter is coupled between RF PA circuitry and a DC power supply, such as a battery. As such, the PA envelope power supply provides an envelope power supply signal to the RF PA circuitry and the PA bias power supply provides a bias power supply signal to the RF PA circuitry. Both the PA envelope power supply and the PA bias power supply receive power via a DC power supply signal from the DC power supply. The PA envelope power supply includes a charge pump buck converter and the PA bias power supply includes a charge pump.

Abstract: A power amplifier includes: a first amplifying element amplifying an input signal; a second amplifying element amplifying an output signal of the first amplifying element; a third amplifying element amplifying the input signal; a first switch connected between an output of the first amplifying element and an input of second amplifying element; a second switch connected between an output of the first amplifying element and an output of the third amplifying element; a third switch connected between an output of the first amplifying element and an output of the second amplifying element; a reference voltage generating a circuit generating reference voltage; a bias circuit supplying a bias current, based on the reference voltage, to inputs of the first, second, and third amplifying elements; and a control circuit controlling the first, second and third switches and the reference voltage generating circuit.

Abstract: A method and apparatus is provided for linearizing the output of a non-linear device, such as a power amplifier. The input signal to the non-linear device is predistorted based on a predistortion model to compensate for distortion introduced by a non-linear device. A wideband feedback signal is generated from the output signal of the non-linear device, and the wideband feedback signal is filtered to generate two or more narrowband distortion signals with predetermined frequencies corresponding to anticipated distortion components in the output signal. Model parameters of the predistortion model are adapted based on the narrowband distortion signals.

Abstract: The present invention includes: a temperature compensation circuit for generating a digital signal corresponding to a temperature of a transistor and outputting a compensation bias current obtained by adding a control current to a reference bias current or by subtracting the control signal from the reference bias current using the generated digital signal; a characteristics compensation circuit for detecting a characteristics error of a mirror transistor connected to the transistor in parallel and for outputting a compensation signal to compensate the characteristics error; and a bias compensation circuit for compensating a bias power applied to the transistor using the compensation bias current and the compensation signal to output the compensated bias power. The present invention is capable of improving the performance of the transistor.

Abstract: A function cell comprising a first field effect transistor (FET) device, a second FET device, a first node connected to a gate terminal of the first FET device and a gate terminal of the second FET device, wherein the first node is operative to receive a voltage signal from an alternating current (AC) voltage source, an amplifier portion connected to the first FET device and the second FET device, the amplifier portion operative to receive a signal from the first FET device and the second FET device, a phase comparator portion having a first input terminal connected to an output terminal of the amplifier and a second input terminal operative to receive the voltage signal from the AC voltage source, the phase comparator portion operative to output a voltage indicative of a bit of a binary value.

Abstract: Power amplification devices are described, which are configured to amplify a radio frequency (RF) transmission signal. The power amplification device includes a voltage regulation circuit and a power amplification circuit. The voltage regulation circuit includes a voltage regulator that is operable to generate a regulated voltage from the supply voltage and a feedback circuit that sets a voltage adjustment gain of the voltage regulation circuit. To help prevent the voltage regulation circuit from saturating, the feedback circuit reduces the voltage adjustment gain in response to a voltage difference reaching a threshold voltage level. The voltage difference is between a voltage regulator control signal level of a voltage regulator control signal and the regulated voltage level of the regulated voltage.

Abstract: There is provided a bias circuit including a power amplifier in which influence of variation of a gate length L is reduced and variation of a gain among products is low. Two NPN- and PNP-type current mirror circuits 101 (NPN type) and 102 (PNP type) are inserted on an input side of a bias circuit 103. It is designed that a gate length of a transistor Q1 on an output side of the current mirror circuit 101 is longer than that of the other transistor. In this manner, even when an error is generated, influence of the error can be suppressed to be small.

Abstract: A power amplifier includes a first transistor, a second transistor and a bias voltage generator. The first transistor includes a gate electrode, a first electrode and a second electrode, where the gate electrode is coupled to a signal input terminal of the power amplifier. The second transistor includes a gate electrode, first electrode and a second electrode, where the second electrode of the second transistor is connected to the first electrode of the first transistor, and the first electrode of the second transistor is coupled to a signal output terminal of the power amplifier. The bias voltage generator is coupled to the second transistor, and is utilized for generating a bias voltage to bias the electrode of the second transistor, where the bias voltage is less than a supply voltage of the power amplifier.

Abstract: Implementations to mitigating side effects of impedance transformation circuits are described. In particular, mitigation circuitry may be coupled to a high impedance circuit to minimize or eliminate non-linear output of the high impedance circuit in order to provide a well-defined bias voltage to the input of a buffer or amplifier device coupled to a capacitive sensor. Additionally, the mitigation circuitry may be coupled to the high impedance circuit to reduce or eliminate rectifying effects of the high impedance circuit. Accordingly, a bias voltage can be utilized to provide a stable operating point of the buffer or amplifier device via a high impedance circuit utilizing one or more impedance transformations.

Abstract: A power amplifier includes: an amplifier having a base into which input signals are input, a collector to which a collector voltage is supplied, and an emitter; and a bias circuit for supplying a bias current to the base of the amplifier. The bias circuit includes a first transistor having a first control terminal into which a reference voltage is input, a first terminal to which a power voltage is applied, and a second terminal connected to the base of the amplifier. A capacitance adjusting circuit elevates capacitance between a grounding point and at least one of the first control terminal and the first terminal when the collector voltage of the amplifier is lowered.

Abstract: Apparatus and methods for envelope tracking are disclosed herein. In certain implementations, an envelope tracking system for generating a power amplifier supply voltage for a power amplifier is provided. The envelope tracking system can include a buck converter and an error amplifier configured to operate in parallel to control the voltage level of the power amplifier supply voltage based on an envelope of an RF signal amplified by the power amplifier. The buck converter can convert a battery voltage into a buck voltage that is based on an error current, and the error amplifier can generate the power amplifier supply voltage by adjusting the magnitude of the buck voltage using an output current that is based on the RF input signal's envelope. The error amplifier can control the buck converter by changing a magnitude of the error current in relation to a magnitude of the output current.

Abstract: Disclosed is an impedance matching circuit capable of wideband matching. The impedance matching circuit includes: a first variable inductor unit of which one end is connected to the first node and an inductance value varies; a second inductor unit connected between the first node and a second node and having a variable inductance value; a first variable capacitor unit of which one end is connected to the first node and a capacitance value varies; and a second variable capacitor unit of which one end is connected to the second node and a capacitance value varies, and the other end of the first variable capacitor unit and the other end of the second variable capacitor unit are connected to a ground voltage terminal to perform the impedance matching between a circuit connected to the other end of the first variable inductor unit and a circuit connected to the second node.

Abstract: There is provided an amplifier circuit. The amplifier circuit includes an amplifying unit including at least one transistor; at least one first bias circuit unit including a resistor and connected to the at least one transistor; and at least one second bias circuit unit connected between an input terminal to which an input signal is applied and the at least one transistor so as to block an input signal having a frequency higher than a first frequency or having a frequency lower than a second frequency. The amplifier circuit according to embodiment of the present invention may prevent thermal runaway, remove a harmonic component from an input signal to be amplified and suppress oscillations.

Abstract: In an amplification device, an amplification unit has a transistor and amplifies a signal that is input. A control unit applies, when a power source is turned on, a pinch-off voltage to a gate of the transistor before applying a drain bias voltage to a drain of the transistor and then applies a gate bias voltage to the gate of the transistor.

Abstract: Apparatus and methods for reducing output noise of a signal channel are provided. In one embodiment, a signal channel includes an amplifier for amplifying an input signal to generate an amplified signal. The amplifier includes a bias circuit that controls a bias current of the amplifier based on a voltage across a biasing capacitor. The apparatus further includes a sampling circuit for sampling the amplified signal. The sampling circuit generates an output signal based on a difference between a first sample of the amplified signal taken at a first time instance and a second sample of the amplified signal taken at a second time instance. The bias circuit samples a bias voltage onto the biasing capacitor before the first time instance and holds the voltage across the biasing capacitor substantially constant between the first time instance and the second time instance to reduce noise of the output signal.

Abstract: A regulator with decreased leakage and low loss for a power amplifier is described. Switching circuitry is used to connect the regulator input bias to a bias control voltage when the power amplifier is to be operated in an on condition or to a voltage generator when the power amplifier is to be operated in an off condition.

Abstract: There is provided a power amplifying apparatus with dual-current control mode, including: a transistor mirror circuit adjusting currents respectively flowing through a main path and a mirror path connected in parallel to a power source terminal; a resistor mirror circuit adjusting the respective currents of the main path and the mirror path; a current controlling unit controlling a control current flowing through the main path with a pre-set constant current; a voltage adjusting unit providing a bias adjustment signal that corresponds to a difference voltage between a first voltage of a first node on the main path to which a current is output from the resistor mirror circuit and a second voltage of a second node on the mirror path to which a current is output from the resistor mirror circuit; and a bias circuit unit adjusting a bias of a power amplifying unit.

Abstract: An amplifier circuit includes a power amplifier configured to amplify an RF input signal to obtain an RF output signal, and a bias controller configured to control a bias of the power amplifier. The bias controller is configured to determine a measure of a load impedance of a load coupled to an output of the power amplifier and provide a bias control signal to adjust the bias of the power amplifier based on the determination of the measure of the load impedance.

Abstract: An amplifier includes an envelope detection unit that detects an envelope of a transmission signal; a comparing unit that compares a voltage of the envelope with a reference voltage; a selecting unit that selects, in accordance with a comparison result obtained by the comparing unit, an amplifying element that amplifies the transmission signal from among a plurality of amplifying elements each having different operating power; a voltage control unit that controls, in accordance with the envelope, a voltage that is used to amplify the transmission signal in the amplifying element that is selected by the selecting unit; a current measuring unit that measures a current of a power supply that supplies the voltage that is controlled by the voltage control unit; and a reference voltage control unit that controls the reference voltage such that the current measured by the current measuring unit decreases.

Abstract: A cascode amplifier circuit having substantial linearity, while maintaining other advantages of cascode amplifiers such as relatively high input-to-output isolation and relatively high gain. The cascode amplifier circuit also provides substantially matched impedance between input and output, at least within a selected frequency band, with the effect of providing a circuit that is well-suited for use in a communication system. The cascode amplifier circuit includes feedback loops, such as for example DC feedback loops and AC feedback loops, and bias optimization, with the effect of improving linearity, maintaining gain, minimizing return loss, and providing a relatively high dynamic range.

Abstract: A system and method improve amplifier efficiency of operation relative to that of an amplifying transistor with a fixed bias current. A power level representing a level of transmission power from an amplifier circuit and an indicator of amplifier circuit operation are provided. The indicator is at least one of channel, channel bandwidth, out-of band spectral requirements, spectral mask requirements, error vector magnitude, modulation rate, and modulation type. The amplifying transistor is biased with a bias current that is determined based at least in part on the power level and the indication where the bias current is different for channels at an edge of a channel band than for channels nearer a center of the channel band.

Abstract: A method generates a reference voltage by steps including: generating a reference signal from a voltage source; generating a comparison signal of the reference signal with a voltage reference; sampling the comparison signal; adjusting a numerical value as a function of the result of the comparison and of the numerical value; and converting the current numerical value into a voltage corresponding to the reference voltage.

Abstract: Memory apparatuses and methods for low power current mode sense amplification are disclosed. An example memory apparatus may include a current mode sense amplifier and a current circuit. The current mode sense amplifier may be configured to provide an output current. The current circuit may comprise a bias generator that is configured to generate a bias signal as well as a current control circuit coupled to both the current mode sense amplifier and the bias generator. The current control circuit may be configured to receive both the output current and the bias signal and control the output current based, at least in part, on the bias signal.