Abstract: An amplifier and a transceiver including the amplifier are provided. The amplifier includes an input terminal; a first transistor of a first conductivity and a second transistor of a second conductivity, each transistor comprising a source terminal, a gate terminal and a drain terminal respectively, the source terminal of the first transistor being coupled to the source terminal of the second transistor, and the gate terminal of the first transistor and the gate terminal of the second transistor being coupled to the input terminal; and an output terminal coupled to the drain terminal of the first transistor and the drain terminal of the second transistor.

Abstract: Bias circuits, amplifiers and methods are provided, such as those for providing bias signals over a range of common mode inputs for an amplifier to output a constant current. One example of a bias circuit is configured to generate a bias signal having a voltage magnitude according to a reference signal. The reference signal is indicative of a common mode input level of an input signal of the amplifier circuit and the bias circuit is further configured to adjust the bias signal over a range of common mode input levels. An amplifier receiving the bias signal is configured to generate an output signal in response to an input signal and drive an output current based on the voltage magnitude of the bias signal provided by the bias circuit.

Abstract: An amplifier (210) includes an input stage (310, 320) and an output stage (330). The input stage (310, 320) has an input for receiving an input signal, and an output. The output stage (330) has an input coupled to the output of the input stage (310, 320), and an output for providing an amplified output signal. The output stage (330) includes a gain stage and a bias circuit. The gain stage has an input forming the input of the output stage, an output for providing the amplified output signal, and a first bias terminal. The bias circuit has a first output terminal coupled to the first bias terminal of the gain stage. During a turn-on period the bias circuit gradually ramps the first bias terminal from a first initial voltage to a first bias voltage.

Abstract: The configurations of sense amplifier and methods thereof are provided. The proposed sense amplifier includes a switch circuit having a main control switch, a sensing switch and a holding switch, wherein the three switches have a first bias, a second bias and a third bias respectively, and an auxiliary control switch electrically connected to the holding switch to control an operation of the holding switch.

Abstract: Provided is a Polar modulation apparatus which compensates for output characteristics of a power amplifier. A data generator generates an amplitude component signal and a phase component signal. A phase modulator generates a phase modulated signal obtained by phase modulating the phase component signal. An adder adds an amplitude offset voltage to the amplitude component signal. A power amplifier which includes a first hetero-junction bipolar transistor, amplifies the phase modulated signal by using the amplitude component signal. A monitor unit monitors the power amplifier and outputs a monitor voltage. The control unit calculates the amplitude offset voltage according to the monitor voltage and outputs the calculated amplitude offset voltage to the adder. The monitor unit includes a second hetero-junction bipolar transistor and outputs a collector emitter voltage of the second hetero-junction bipolar transistor as the monitor voltage.

Abstract: The low-noise amplifier with through mode is configured such that a source grounded transistor and a gate grounded transistor are connected in cascode, and a load impedance element and a switching transistor are serially connected between the drain of the gate grounded transistor and a power supply, and a through pass circuit is connected between an input terminal and an output terminal. The gate voltage of the gate grounded transistor is regulated by a bias circuit and the voltage of a mode control terminal is converted by a level shifter to control the gate voltage of the switching transistor, whereby, in the case of using only transistors whose terminal-to-terminal breakdown voltages are each equal to or less than the power supply voltage, it becomes feasible to prevent voltages equal to or more than the terminal-to-terminal breakdown voltages from being applied between the terminals of each transistor.

Abstract: Disclosed herein is a circuit for preventing an element from being damaged although output impedance of a final transistor is changed in a power amplifier. The power amplifier includes: a power stage amplifying a signal; a transformer connected to an output terminal of the power stage and coupling a signal output from the power stage; and a controller controlling a bias voltage from the power stage according to the coupled signal. Although output impedance is changed, damage to the power amplifier can be prevented. Also, the power amplifier can be automatically controlled to maintain performance thereof by sensing an operational state in which output impedance is normal.

Abstract: A power amplifier includes a first matching circuit configured to perform harmonic processing of an input signal, and a second matching circuit configured to perform the harmonic processing of an output signal, the output signal being generated by amplifying a power of the input signal. The power amplifier rotates a phase of output impedance at a matching point of the harmonic included in the generated output signal when the power of the input signal is decreased from a value higher than a certain value to a value lower than the certain value.

Abstract: According to embodiments of the present invention, an over-input signal may be limited to be within a range between adjustable upper limit voltage and lower limit voltage while suppressing deterioration of a noise figure. An amplifier circuit includes an input transistor; an input transistor; a resistor element having a first terminal connected to a gate of the input transistor and a second terminal connected to a bias voltage; and a protective circuit connected to the gate of the input transistor and limiting an input to the gate of the input transistor to be within a range between an upper limit voltage and lower limit voltage adjustable based on the bias voltage.

Abstract: Techniques for monitoring and controlling bias current of amplifiers are described. In an exemplary design, an apparatus may include an amplifier and a bias circuit. The amplifier may include at least one transistor coupled to an inductor. The bias circuit may generate at least one bias voltage for the at least one transistor in the amplifier to obtain a target bias current for the amplifier. The bias circuit may generate the at least one bias voltage based on a voltage across the inductor in the amplifier, or a current through a current mirror formed with one of the at least one transistor in the amplifier, or a gate-to-source voltage of one of the at least one transistor in the amplifier, or a voltage in a replica circuit replicating the amplifier, or a current applied to the amplifier with a switched mode power supply disabled.

Abstract: Techniques for monitoring and controlling bias current of amplifiers are described. In an exemplary design, an apparatus may include an amplifier and a bias circuit. The amplifier may include at least one transistor coupled to an inductor. The bias circuit may generate at least one bias voltage for the at least one transistor in the amplifier to obtain a target bias current for the amplifier. The bias circuit may generate the at least one bias voltage based on a voltage across the inductor in the amplifier, or a current through a current mirror formed with one of the at least one transistor in the amplifier, or a gate-to-source voltage of one of the at least one transistor in the amplifier, or a voltage in a replica circuit replicating the amplifier, or a current applied to the amplifier with a switched mode power supply disabled.

Abstract: Illustrative embodiments of power amplifiers are disclosed. In one embodiment, a power amplifier includes a plurality of transistors formed on a silicon-on-insulator (SOI) substrate such that the plurality of transistors are each electrically isolated from one another within the SOI substrate. The power amplifier also includes a plurality of biasing networks, each biasing network being configured to dynamically bias at least one of the plurality of transistors. The plurality of transistors are electrically coupled in a series stack, with an output of the power amplifier being provided across the series stack.

Abstract: An amplifier circuit includes an amplification unit and a back-bias voltage providing unit. The amplification unit amplifies input data. The back-bias voltage providing unit provides selectively back-bias voltages of different levels to the amplification unit in an initial operation period of the amplification unit and a period after the initial operation period.

Abstract: A system includes a power amplifier, a preamplifier, a first temperature sensor, and a bias generator. The power amplifier has a first gain, which is a function of a temperature of the power amplifier. The preamplifier has a second gain, amplifies an input signal, and outputs an amplified signal to the power amplifier. The first temperature sensor senses the temperature and generates a first signal. The bias generator generates a first biasing signal to bias the power amplifier, generates a second biasing signal to bias the preamplifier, and adjusts the second gain by adjusting the second biasing signal based on the first signal. The adjusted second gain compensates a change in the first gain due to the change in the temperature.

Abstract: In one embodiment the present invention includes a switching circuit. The circuit comprises a first transistor, a second transistor, and a boost circuit. The first transistor couples a first power source to a first intermediate node during a first phase of operation and the second transistor couples a second intermediate node to the first intermediate node during a second phase of operation. The boost circuit is coupled to the second intermediate node and provides a second power source by a transferring of energy from the first power source. The transferring of energy includes an inductor receiving energy from the first power source during the first phase of operation and providing a portion of said energy to the boost circuit during the second phase of operation. The boost circuit provides a biasing to enable deactivation of the second transistor during the first phase of operation.

Abstract: Apparatus and methods for power amplifiers are disclosed. In one embodiment, a power amplifier circuit assembly includes a power amplifier and an impedance matching network. The impedance matching network is operatively associated with the power amplifier and is configured to provide a load line impedance to the power amplifier between about 6 ? and about 10 ?. The impedance matching network includes a fundamental matching circuit and one or more termination circuits, and the fundamental matching circuit and each of the of the one or more termination circuits include separate input terminals for coupling to an output of the power amplifier so as to allow the fundamental matching circuit and each of the one or more termination circuits to be separately tuned.

Abstract: A method and network equipment for controlling power amplification are disclosed. The method for controlling power amplification includes outputting a voltage signal according to the state of an NE. The voltage signal is applied to a grid electrode or a base electrode of at least one power amplifier transistor in a power amplifier.

Abstract: According to one embodiment, provided are an amplifier transistor configured to amplify an input signal; a biasing circuit configured to set a bias voltage in such a manner as to allow the amplifier transistor to perform amplification; an electrostatic protective circuit configured to set the bias voltage for the amplifier transistor in such a manner as to make the amplifier transistor to turn off based on voltage to be applied to the amplifier transistor; and a switching circuit configured to switch the bias voltage for the amplifier transistor based on a power supply condition.

Abstract: A power amplifier includes: an amplifying element having a base into which input signals are inputted, a collector to which a collector voltage is applied, and an emitter; and a bias circuit supplying a bias current to the base of the amplifying element. The bias circuit includes a bias current lowering circuit which lowers the bias current when the collector voltage is lower than a prescribed threshold value.

Abstract: This document discusses, among other things, a system and method for receiving an input signal and power supply information, and amplifying the input signal by a gain value determined as a function of the power supply information.

Abstract: A power control circuit for regulating an output voltage applied to a radio frequency power amplifier. The power control circuit includes an amplifier, a pass transistor and one or more saturation detectors. An input ramp voltage having a magnitude equal to a first voltage level is applied to a negative terminal of the amplifier. The pass transistor provides an output voltage at a drain terminal of the pass transistor. The saturation detector detects a magnitude of a voltage at a gate terminal of the pass transistor and generates a control current based on the magnitude of the voltage at the gate terminal of the pass transistor. The voltage regulating circuit reduces the magnitude of the input ramp voltage from the first voltage level to a third voltage level based on the control current.

Abstract: Disclosed is a sound detecting circuit which includes a sensing unit configured to generate an AC signal in response to a sound pressure level of a sound signal; an amplification unit configured to amplify the AC signal; and a bias voltage generating unit configured to generate a bias voltage to be provided to the amplification unit. The bias voltage generating unit comprises a current source configured to provide a power current; and a current-voltage converting circuit configured to convert the power current into the bias voltage and to reduce a noise due to the power current.

Abstract: In one embodiment, a temperature compensation circuit includes a bias circuit configured to output a bias current having a current value increasing in proportion to an absolute temperature in a low-temperature region, and having a greater current value than the current value proportional to the absolute temperature in a high-temperature region, and a transistor which is supplied with the bias current. The bias circuit includes first to third transistors, a fourth transistor through which a first current flows, a fifth transistor, a sixth transistor through which a second current flows, and a control circuit having a connection terminal capable of being connected with an external resistor for adjusting a magnitude of the second current. The bias circuit generates a third current by adding the first current to the second current, and outputs the bias current that is the third current or a fourth current depending on the third current.

Abstract: Aspects of a system for a power amplifier with an on-package matching transformer may include a DC/DC converter that enables generation of a bias voltage level within an IC die based on an amplitude of an input signal to a PA circuit within the IC die. The bias voltage level may be applied to a transformer, which is external to the IC die but internal to an IC package containing the IC die and/or a circuit board containing the IC package. One or more amplifier bias voltage levels, derived from the bias voltage level applied to the transformer, may be applied to the PA circuit.

Abstract: An amplifier circuit comprises differential amplification circuitry comprising an input stage having first and second differential inputs, and an output stage, having respective first and second amplifier components with first and second differential outputs. The first amplifier component of the output stage comprises a first power transistor operably coupled to the first differential output and driven by a first differential output of the input stage, and a third power transistor operably coupled to the first differential output of the amplifier circuit and driven by a second output of the input stage. The second amplifier component comprises a second power transistor operably coupled to the second differential output and driven by a second output of the input stage, and a fourth power transistor operably coupled to the second differential output and driven by the first output of the input stage.

Abstract: A semiconductor integrated circuit device constituting an inverting amplifier employs a cascode current source as a current source. In the semiconductor integrated circuit device, a high-potential-side transistor of the cascode current source and a low-potential-side transistor constituting an amplification portion are shared. The configuration can not only make an output impedance of the cascode current source high and improve current source characteristics but also make a minimum potential at a minimum potential point of the amplification portion low and ensure a sufficient power supply voltage margin.

Abstract: An operational amplifier includes a first stage, a second stage, and a switching unit. The first stage receives an analog input signal. The second stage has an output node coupled to an output switch. The switching unit is coupled between the first stage and the second stage. The switching unit includes a capacitive component and a first switch coupled to the capacitive component in series. The first switch is turned off when the output switch is turned on. The first switch is turned off while the analog input signal is in transition, and is turned on while the analog input signal is steady. The first switch is turned on when the output switch is turned off.

Abstract: There is provided a power amplifier module having a bias circuit, in which a bias power is supplied to an amplifier by differently setting an impedance between an input signal terminal and a reference power terminal and an impedance between the input signal terminal and a ground. The power amplifier module includes: an amplifier unit receiving a bias power to amplify an input signal; and a bias unit supplying the bias power to the amplifier, by differently setting an impedance between an input signal terminal transmitting the input signal therethrough and a reference power terminal transmitting a reference power having a predetermined voltage level and an impedance between the input signal terminal and a ground.

Abstract: There is provided a power amplifier. The power amplifier includes an amplification unit including at least one amplification device; a power generation unit generating an input signal supplied to the amplification unit; and a bias circuit unit controlling bias of the at least one amplification device according to the input signal, wherein the bias circuit unit supplies a predetermined bias voltage to the amplification unit before the input signal is applied to the amplification unit. According to the embodiments of the present invention, a delay phenomenon occurring at an initial driving time or a low power mode may be significantly reduced by supplying a predetermined bias signal to an amplification unit in a standby circuit before the bias circuit unit of the power amplifier normally outputs the bias signal to the amplification unit.

Abstract: A transimpedance method and apparatus are provided. In one implementation an apparatus includes a common-gate amplifier for receiving a first current from a first circuit node and outputting a second current to a second circuit node, and a load circuit coupled to the second circuit node, the load circuit comprising a diode-connected MOS (metal-oxide semiconductor field effect transistor), wherein a gate terminal of the MOS is coupled to a drain terminal of the MOS via a resistor. In one embodiment, a current-mode input is injected to the first circuit node and the apparatus further comprises a biasing circuit for outputting a substantially constant current to the first circuit node.

Abstract: An automatic bias operational amplifying circuit, includes a control sub-circuit and an offset sub-circuit connected to the control sub-circuit. The control sub-circuit includes a first input terminal, a second input terminal, a first field-effect transistor connected to the offset sub-circuit, a second field-effect transistor connected to the first input terminal, a third field-effect transistor connected to the second input terminal, a first output terminal connected to the second field-effect transistor, a second output terminal connected to the third field-effect transistor, a first resistor connected to the first output terminal, and a second resistor connected to the second output terminal.

Abstract: A circuit that includes a Darlington transistor pair having an input transistor and an output transistor configured to generate an output signal at an output node in response to an input signal received through the input node is disclosed. The circuit has a frequency bias feedback network communicatively coupled between the output transistor and the input node for providing biasing to the Darlington transistor pair as well as for adjusting a phase and amplitude of an amplified version of the input signal that passes through the input transistor and into the frequency bias network. The circuit further includes a feedback coupling network coupled between the output node and the input node for feeding back to the input node a portion of the amplified version of the input signal that passes through the input transistor.

Abstract: Embodiments of the present invention may provide an integrated circuit that may comprise a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain. Further, the integrated circuit may comprise a second transistor to form an active load of the first transistor, the second transistor may have its drain and gate coupled to the drain of the first transistor. In addition, the integrated circuit may comprise a third transistor to form a current mirror with the second transistor, a fourth transistor to form an active load of the third transistor, and a fifth transistor to form a current mirror with the fourth transistor. The fifth transistor may be connected to the drain of the second transistor. The integrated circuit may form an amplifier and Gm stage of a reference buffer.

Abstract: This disclosure relates generally to radio frequency (RF) amplification devices and methods of limiting an RF signal current. Embodiments of the RF amplification device include an RF amplification circuit and a feedback circuit. The RF amplification circuit is configured to amplify an RF input signal so as to generate an amplified RF signal that provides an RF signal current with a current magnitude. The feedback circuit is used to limit the RF signal current. In particular, a thermal sense element in the feedback circuit is configured to generate a sense current, and thermal conduction from the RF amplification circuit sets a sense current level of the sense current as being indicative of the current magnitude of the RF signal current. To limit the RF signal current, the feedback circuit decreases the current magnitude of the RF signal current in response to the sense current level reaching a trigger current level.

Abstract: Disclosed herein is a power amplifier system including: a power amplifier; a power controlling unit providing driving voltage and driving current corresponding to a preset reference voltage to the power amplifier; a current controlling unit performing a control so that control current corresponding to applied control voltage flows; a bias controlling unit detecting current and voltage corresponding to the driving current of the power controlling unit and controlling bias current of the power amplifier according to the detected voltage; and a current adjusting unit detecting bias voltage corresponding to the bias current of the power amplifier and adjusting the driving current of the power controlling unit according to the detected bias voltage. Even though applied control voltage increases, current applied to the power amplifier is appropriately adjusted, thereby making it possible to improve characteristics of the power amplifier.

Abstract: Disclosed herein is a power amplifier system, including: a power amplifier; a first regulator generating driving voltage Vd and driving current Id corresponding to preset first reference voltage; a current controller controlling the driving current Id of the first regulator corresponding to applied control voltage; a first resistor connected between the first regulator and the current controller and a second resistor connected between the first regulator and the power amplifier, a bias controller detecting current and voltage corresponding to the driving current and controlling bias current of the power amplifier according to the detected voltage; and a second regulator generating power supply voltage corresponding to preset second reference voltage, whereby characteristics of the power amplifier can be improved by constantly controlling current supplied to the power amplifier even though the input voltage applied to the power amplifier system is increased.

Abstract: One embodiment of the present invention relates to a power amplifier comprising a plurality of amplifying elements connected in a serial-parallel matrix configuration, containing parallel columns having amplifying elements connected in series. The parallel columns are connected to a common output path coupled to a supply voltage source configured to provide an equal supply voltage to each of the columns. One or more input signals (e.g., RF input signals) are connected to the power amplifier by way of input terminals on a first row of amplifying elements. The remaining amplifying elements have control terminals that are connected to independent control signals, which allow each amplifying element to be operated independent of the other amplifying elements in the matrix. This selective operation of amplifying elements allows for improved efficiency over a wide range of power amplifier output powers.

Abstract: A Bi-Directional and Adjustable Current Source (“BACS”) for providing an input voltage to a mute/standby control pin of a power stage integrated circuit (“IC”) of an amplifier input with a voltage signal that is linear, where an output of the BACS and the input to the control pin are shunted with a capacitor, is described. The BACS may include a first switch in signal communication with a high voltage reference and a first current source in signal communication with the first switch. The BACS may also include a second switch in signal communication with a low voltage reference and a second current source in signal communication with the second switch. The BACS may further include a directional current element in signal communication with both the first current source, the second current source, the output of the BACS, the input to the control pin, and the capacitor, where the directional current element is configured to prevent current flow from the output BACS to the first current source.

Abstract: A power amplifier circuit can be linked to an antenna arrangement of a communication system for transmission of ASK RF data signals. The power amplifier circuit includes an amplifier core with several cascode amplifier cells in parallel. Each cascode amplifier cell is composed of three NMOS transistors in triode mounting between an output terminal connected to the antenna arrangement, and an earth terminal. A first transistor of each cascode amplifier cell is controlled by a carrier frequency signal, whereas a second transistor of each cascode amplifier cell is controlled by a smoothing control loop in order to modulate data to be transmitted on carrier frequency by amplitude shift keying. The smoothing control loop is provided for generating an increasing gate voltage for the second transistors on the basis of an increasing current ramp from a first minimum current value to a second maximum current value during a “0” to “1” data transition.

Abstract: Techniques to improve low noise amplifiers (LNAs) with noise canceling are described. LNA includes a first and a second amplifier which work together to noise cancel the noise generated at an input stage circuit. The input stage circuit receives an RF signal and is characterized by a first node and a second node. The first amplifier converts a noise voltage at the first node into a first noise current at an output of the first amplifier. The second amplifier is directly coupled to the output of the first amplifier and provides noise canceling by summing the first noise current with a second noise current generated by the second amplifier as a function of the noise voltage at the second node. The proposed techniques eliminate the need for large ac coupling capacitors and reduce the die size occupied by the LNA.

Abstract: Disclosed are voltage distribution device and method for controlling CMOS-based devices for switching radio frequency (RF) signals. In certain RF devices such as mobile phones, providing different amplification modes can yield performance advantages. For example, a capability to transmit at low and high power modes typically results in an extended battery life, since the high power mode can be activated only when needed. Switching between such amplification modes can be facilitated by one or more switches formed in an integrated circuit and configured to route RF signal to different amplification paths. In certain embodiments, such RF switches can be formed as CMOS devices, and can be based on triple-well structures. In certain embodiments, various bias voltages applied to such a CMOS RF switch can be facilitated by a voltage distribution component.

Abstract: Systems and methods may include an amplifier having at least a first input port, where the amplifier includes a first capacitance associated with the first input port; a first bias circuit, where the first bias circuit comprises a series connection of a first charging circuit and a first discharging circuit, wherein a first node between the first charging circuit and the first discharging circuit is connected to the first input port, wherein responsive to an RF input signal having at least a first predetermined level being received at the first input port, the first charging circuit charges the first capacitance associated with the first input port during a first portion of a cycle of the RF input signal, and discharges the first capacitance associated with the first input port during a second portion of the cycle, thereby controlling a DC bias voltage level available at the first input port.

Abstract: A power amplifier includes an input matching circuit, an amplifier transistor for amplifying an input signal received through the input matching circuit, an element for varying the collector voltage of the amplifier transistor, a bias circuit for varying the idle current in the amplifier transistor, and a compensation circuit for varying capacitance of the input matching circuit to maintain the phase shift and the input reflection in the power amplifier constant when the collector voltage and the idle current are varied, to prevent a decrease in the efficiency of the power amplifier due to changes in the output power of the amplifier transistor.

Abstract: A radio frequency (RF) amplifier module has a digitally controllable amplifier to receive a first biased signal, a further biased signal, and a digital control signal including a less significant bit (LSB) component and a more significant bit (MSB) component. The digitally controllable amplifier has an LSB module operating according to the first biased signal and the LSB component, and an MSB module operating according to the further biased signal and the MSB component. The RF amplifier module further has a biasing component to apply a first, operating DC bias voltage to the further biased signal when the digitally controllable amplifier operates in a higher gain mode and the MSB module outputs a load current component, and apply a second, higher DC bias voltage to the further biasing signal when the digitally controllable amplifier operates in a lower gain mode and the MSB module outputs the load current component.

Abstract: Biasing methods and devices for amplifiers are described. The described methods generate bias voltages proportional to the amplifier output voltage to control stress voltages across transistors used within the amplifier.

Abstract: Systematic IM2 calibration for a differential LNA is disclosed. In an aspect, an apparatus includes an amplifier configured to output an amplified signal having a level of systematic pre-mixer IM2 distortion, a detector configured to detect the level of the systematic pre-mixer IM2 distortion in the amplified signal, and a bias signal generator configured to generate at least one bias signal configured to adjust the amplifier to reduce the level of the systematic pre-mixer IM2 distortion.

Abstract: An amplifier including an amplifier transistor, and a switch transistor, wherein the amplifier is configured to be switched on and off by controlling bias voltages of the transistors.

Abstract: A power amplifier includes: an amplifying element having a base into which input signals are inputted, a collector to which a collector voltage is applied, and an emitter; and a bias circuit supplying a bias current to the base of the amplifying element. The bias circuit includes a bias current lowering circuit which lowers the bias current when the collector voltage is lower than a prescribed threshold value.

Abstract: A method of operating an amplifier output of an amplifier as a signal switch, the method including coupling a gate of a switch transistor of the amplifier to a switch signal line, coupling a gate of an amplifier transistor of the amplifier to a gate signal line, and controlling impedance of the amplifier by manipulating gate bias voltages of the transistors via the signal lines.

Abstract: A radio frequency amplifier circuit includes a substrate that is capable of receiving a substrate bias voltage. The source of a transistor is capable of receiving a source bias voltage. The drain of the transistor is capable of receiving a drain bias voltage. The gate of the transistor is located between the source and the drain. A radio frequency input signal is coupled to the gate. A substrate bias circuit provides the substrate bias voltage. The substrate bias voltage and the source bias voltage forward bias the first diode formed by the source and the substrate. The substrate bias voltage and the drain bias voltage reverse bias the second diode formed by the drain and the substrate.