Integrated Circuits Patents (Class 330/307)
  • Patent number: 10243522
    Abstract: A low-noise amplifier device includes an inductive input element, an amplifier circuit, an inductive output element and an inductive degeneration element. The amplifier device is formed in and on a semiconductor substrate. The semiconductor substrate supports metallization levels of a back end of line structure. The metal lines of the inductive input element, inductive output element and inductive degeneration element are formed within one or more of the metallization levels. The inductive input element has a spiral shape and the an amplifier circuit, an inductive output element and an inductive degeneration element are located within the spiral shape.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: March 26, 2019
    Assignee: STMicroelectronics SA
    Inventor: Raphael Paulin
  • Patent number: 10230337
    Abstract: Aspects of this disclosure relate to an impedance transformation circuit for use in an amplifier, such as a low noise amplifier. The impedance transformation circuit includes a matching circuit including a first inductor. The impedance transformation circuit also includes a second inductor. The first and second inductors are magnetically coupled to each other to provide negative feedback to linearize the amplifier.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: March 12, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventor: Leslie Paul Wallis
  • Patent number: 10218321
    Abstract: Thermally rugged power amplifiers and related methods. In some embodiments, a method for manufacturing a radio-frequency amplifier can include providing or forming a semiconductor substrate, and forming an array of cascoded devices on the semiconductor substrate to be capable of amplifying a signal, such that the array of cascoded devices includes a plurality of cascoded devices arranged in a first row and a plurality of cascoded devices arranged in a second row. Each cascoded device can include an input stage and an output stage arranged in a cascode configuration, and each of the first and second rows can be configured such that the output stages are positioned in a staggered orientation. The staggered arrangement of the cascoded devices in the first row can be offset relative to the staggered arrangement of the cascoded devices in the second row to avoid a direct row-to-row adjacent pair of output stages.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: February 26, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventor: Philip John Lehtola
  • Patent number: 10156864
    Abstract: In accordance with an embodiment, an integrated circuit includes a substrate, an amplifier MOSFET, and a bias voltage terminal configured to generate a potential difference of the substrate relative to at least one load terminal of the amplifier MOSFET.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: December 18, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Winfried Bakalski, Werner Simbuerger, Anton Steltenpohl, Hans Taddiken
  • Patent number: 10128204
    Abstract: In accordance with an embodiment, an RF module includes a bulk semiconductor substrate with at least one integrated RF component integrated in a first main surface region of the bulk semiconductor substrate; an insulator structure surrounding a side surface region of the bulk semiconductor substrate; a wiring layer stack including at least one structured metallization layer embedded into an insulation material, the wiring layer stack being arranged on the first main surface region of the bulk semiconductor substrate and a first main surface region of the insulator structure; and a carrier structure at a second main surface region of the insulator structure, wherein the carrier structure and the insulator structure include different materials.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: November 13, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Carsten Ahrens, Katharina Umminger, Carsten von Koblinski
  • Patent number: 10027282
    Abstract: According to the present invention, an integrated circuit includes a first amplifier stage, a second amplifier stage, a first signal line connecting an output of the first amplifier stage and an input of the second amplifier stage to each other, a first plane for ground connected to the first amplifier stage, a second plane for ground connected to the second amplifier stage and at least one at least one line for ground connecting the first plane and the second plane to each other, wherein the at least one line has a center line having a length of 10 ?m to 1 mm, a width of the at least one line is ? or less of a width of the first plane, and a pattern ratio is 1 or more.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: July 17, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takumi Sugitani, Hitoshi Kurusu
  • Patent number: 9991909
    Abstract: A radio-frequency module includes switch elements, first signal paths, band pass filters, first matching circuits, second signal paths, and second matching circuits. Each of the first signal paths is connected between one end of a corresponding one of the switch elements and an antenna terminal. Each of the band pass filters is connected to a corresponding one of the first signal paths and allows a radio-frequency signal of one of the plurality of frequency bands to pass therethrough. Each of the first matching circuits is connected to a corresponding one of the first signal paths. Each of the second signal paths is connected to a corresponding one of the switch elements. Each of the second matching circuits is connected to a corresponding one of the second signal paths. A component included in the first matching circuits and a component included in the second matching circuits are electromagnetically coupled.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: June 5, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takashi Watanabe
  • Patent number: 9827871
    Abstract: A system, method, and computer-readable storage medium to dynamically manage heat in an electric energy storage system, such as a battery pack or ultra-capacitor pack system in an electric vehicle.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: November 28, 2017
    Inventor: Robert Del Core
  • Patent number: 9787260
    Abstract: Power amplifier having staggered cascode layout for enhanced thermal ruggedness. In some embodiments, a radio-frequency (RF) amplifier such as a power amplifier (PA) can be configured to receive and amplify an RF signal. The PA can include an array of cascoded devices connected electrically parallel between an input node and an output node. Each cascoded device can include a common emitter transistor and a common base transistor arranged in a cascode configuration. The array can be configured such that the common base transistors are positioned in a staggered orientation relative to each other.
    Type: Grant
    Filed: February 13, 2016
    Date of Patent: October 10, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventor: Philip John Lehtola
  • Patent number: 9553549
    Abstract: A heterojunction bipolar transistor (HBT) hybrid type RF (radio frequency) power amplifier includes a first device including an input terminal for receiving an RF signal, a pre-driver stage for amplifying the received RF signal, and an output terminal, the input terminal, the pre-driver stage and the output terminal being disposed in or over a first substrate; and a second device having a main stage having an HBT amplifier circuit disposed in or over a second substrate to further amplify the RF signal amplified by the pre-driver stage. The RF signal further amplified by the main stage is output through the output terminal of the first device.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: January 24, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Young Kwon, David Bockelman, Marshall Maple, Joo Min Jung
  • Patent number: 9553550
    Abstract: A radio frequency (RF) switch semiconductor die and an RF supporting structure are disclosed. The RF switch semiconductor die is attached to the RF supporting structure. The RF switch semiconductor die has a first edge and a second edge, which may be opposite from the first edge. The RF supporting structure has a group of alpha supporting structure connection nodes, which is adjacent to the first edge; a group of beta supporting structure connection nodes, which is adjacent to the second edge; and an alpha AC grounding supporting structure connection node, which is adjacent to the second edge. When the group of alpha supporting structure connection nodes and the alpha AC grounding supporting structure connection node are active, the group of beta supporting structure connection nodes are inactive.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: January 24, 2017
    Assignee: Qorvo US, Inc.
    Inventors: Anthony Puliafico, David E. Jones, Paul D. Jones, Chris Levesque, William David Southcombe, Scott Yoder, Terry J. Stockert
  • Patent number: 9484222
    Abstract: A semiconductor device, related package, and method of manufacturing same are disclosed. In at least one embodiment, the semiconductor device includes a radio frequency (RF) power amplifier transistor having a first port, a second port, and a third port. The semiconductor device also includes an output lead, a first output impedance matching circuit between the second port and the output lead, and a first additional circuit coupled between the output lead and a ground terminal. At least one component of the first additional circuit is formed at least in part by way of one or more of a plurality of castellations and a plurality of vias.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: November 1, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Hussain H. Ladhani, Lu Li, Mahesh K. Shah, Lakshminarayan Viswanathan, Michael E. Watts
  • Patent number: 9462675
    Abstract: A method of improving electrical isolation between a first circuit and a second circuit sharing a common substrate having an effective dielectric constant greater than that of air. The first and second circuits are spaced apart and separated from one another by an intermediate portion of the substrate. The method includes removing a portion of the intermediate portion to replace the portion removed with air thereby reducing the effective dielectric constant of the intermediate portion. By reducing the effective dielectric constant of the intermediate portion, electrical isolation between the first and second circuits is improved thereby reducing crosstalk between the first and second circuits. In particular implementations, the method may be used to reduce alien crosstalk between adjacent communication outlets in a patch panel.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: October 4, 2016
    Assignee: LEVITON MANUFACTURING CO., INC.
    Inventors: Adam W. Gibson, Jeffrey Alan Poulsen
  • Patent number: 9462395
    Abstract: A MEMS acoustic transducer device has a capacitive microelectromechanical sensing structure and a biasing circuit. The biasing circuit includes a voltage-boosting circuit that supplies a boosted voltage on an output terminal, and a high-impedance insulating circuit element set between the output terminal and a terminal of the sensing structure, which defines a first high-impedance node associated with the insulating circuit element. The biasing circuit has: a pre-charge stage that generates a first pre-charge voltage on a first output thereof, as a function of, and distinct from, the boosted voltage; and a first switch element set between the first output and the first high-impedance node. The first switch element is operable for selectively connecting the first high-impedance node to the first output, during a phase of start-up of the biasing circuit, for biasing the first high-impedance node to the first pre-charge voltage.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: October 4, 2016
    Assignee: STMicroelectronics S.r.l.
    Inventors: Germano Nicollini, Andrea Barbieri, Federica Barbieri, Alberto Danioni, Edoardo Marino, Sergio Pernici
  • Patent number: 9407222
    Abstract: A variable matching circuit includes a transformer which is disposed between first and second transistor circuits. A primary inductor device and a secondary inductor device are magnetically coupled in the transformer. The primary inductor device is connected between an output terminal of the first transistor circuit and a bias circuit for the first transistor circuit. The secondary inductor device is connected between an input terminal of the second transistor circuit and a bias circuit for the second transistor circuit. Connection points between the primary inductor device and the bias circuit for the first transistor circuit and between the secondary inductor device and the bias circuit for the second transistor circuit are connected to first and second capacitive elements, respectively. At least one of inductance values of the respective primary and secondary inductor devices and capacitance values of the respective first and second capacitive elements is variable.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: August 2, 2016
    Assignee: PANASONIC CORPORATION
    Inventor: Masaki Kanemaru
  • Patent number: 9202904
    Abstract: According to example embodiments, a power device chip includes a plurality of unit power devices classified into a plurality of sectors, a first pad and a second pad. At least one of the first and second pads is divided into a number of pad parts equal to a number of the plurality of sectors. The first pad is connected to first electrodes of the plurality of unit power devices, and the second pad is connected to second electrodes of the plurality of unit power devices. The unit power devices may be diodes. The power device chip may further include third electrodes in the plurality of unit power devices, and a third pad may be connected to the third electrodes. In this case, the unit power devices may be high electron mobility transistors (HEMTs). Pad parts connected to defective sectors may be excluded from bonding.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: December 1, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-jun Hwang, Jong-seob Kim, Jae-joon Oh
  • Patent number: 9203358
    Abstract: A radio frequency amplifier circuit includes a transistor and an output-side matching circuit. The output-side matching circuit includes a first distributed constant line to which a radio frequency signal from the transistor is transmitted, a flat plate lead terminal transmitting the radio frequency signal from the first distributed constant line to an outside of the package, and a capacitive element having one electrode that is connected to the lead terminal and the other electrode that is grounded. A back surface of the lead terminal is joined to a resin substrate, and the capacitive element and the first distributed constant line are disposed adjacent to each other, with an alignment direction of the capacitive element and the first distributed constant line intersecting an alignment direction of the first distributed constant line and the lead terminal.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 1, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tomohide Kamiyama, Hiroshi Naitou, Takashi Uno, Motoyoshi Iwata, Kazuhiro Yahata, Hikaru Ikeda
  • Patent number: 9159288
    Abstract: Gate line driver circuitry applies an output pulse to each of several gate lines for a display element array. The circuitry has a number of gate drivers each being coupled to drive a respective one of the gate lines. Each of the gate drivers has an output stage in which a high side transistor and a low side transistor are coupled to drive the respective gate line, responsive to at least one clock signal. A pull down transistor is coupled to discharge a control electrode of the output stage. A control circuit having a cascode amplifier is coupled to drive the pull down transistor as a function of a) at least one clock signal and b) feedback from the control electrode. Other embodiments are also described and claimed.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: October 13, 2015
    Assignee: Apple Inc.
    Inventors: Shih Chang Chang, Young Bae Park, Chun-Yao Huang, Kyung Wook Kim, Szu-Hsien Lee
  • Patent number: 9099962
    Abstract: A system and method improve amplifier efficiency of operation relative to that of a matching circuit with fixed matching conditions. A power level representing a level of transmission power from an amplifier circuit and an indicator of amplifier circuit operation are provided. The indicator is at least one of channel, channel bandwidth, out-of band spectral requirements, spectral mask requirements, error vector magnitude, modulation rate, and modulation type. The matching conditions for a matching circuit of an amplifying transistor are adjusted based at least in part on the power level and the indication where the matching conditions are different for channels at an edge of a channel band than for channels nearer a center of the channel band.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: August 4, 2015
    Assignee: SiGe Semiconductor, Inc.
    Inventors: Alan J. A. Trainor, Grant Darcy Poulin, Craig Joseph Christmas
  • Patent number: 9041470
    Abstract: A semiconductor package device comprises a radio frequency power transistor having an output port operably coupled to a single de-coupling capacitance located within the semiconductor package device. The single de-coupling capacitance is arranged to provide both high frequency decoupling and low frequency decoupling of signals output from the radio frequency power transistor.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: May 26, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Gerard Bouisse
  • Patent number: 9041472
    Abstract: A power amplifier module includes a power amplifier including a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3×1016 cm?3 at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base; and an RF transmission line driven by the power amplifier, the RF transmission line including a conductive layer and finish plating on the conductive layer, the finish plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness that is less than about the skin depth of nickel at 0.9 GHz. Other embodiments of the module are provided along with related methods and components thereof.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: May 26, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventors: Howard E. Chen, Yifan Guo, Dinhphuoc Vu Hoang, Mehran Janani, Tin Myint Ko, Philip John Lehtola, Anthony James LoBianco, Hardik Bhupendra Modi, Hoang Mong Nguyen, Matthew Thomas Ozalas, Sandra Louise Petty-Weeks, Matthew Sean Read, Jens Albrecht Riege, David Steven Ripley, Hongxiao Shao, Hong Shen, Weimin Sun, Hsiang-Chih Sun, Patrick Lawrence Welch, Peter J. Zampardi, Jr., Guohao Zhang
  • Publication number: 20150116040
    Abstract: An amplifier includes a transistor chip, a matching chip with a capacitor group having multiple MIM capacitors, each of the MIM capacitors including a lower electrode, a dielectric, and an upper electrode, a bonding wire that electrically connects the transistor chip to the upper electrode of any one of the MIM capacitors of the capacitor group and transmits a high-frequency signal, and a case that accommodates the transistor chip and the matching chip. The lower electrodes of the MIM capacitors are grounded, and capacitance values of each of the MIM capacitors of the capacitor group are different from each other.
    Type: Application
    Filed: July 2, 2014
    Publication date: April 30, 2015
    Inventors: Shinichi Miwa, Kunihiro Sato
  • Patent number: 9007129
    Abstract: The disclosure relates to an amplifier device comprising an integrated circuit die (701a; 701b) having a first amplifier (702a; 702b) and a second amplifier. A Doherty amplifier may be implemented in accordance with the present invention. The amplifier device also comprises a first connector (706a; 706b) having a first end coupled to the first amplifier and a second end for coupling with a circuit board (718a; 718b), a second connector (708a; 708b) having a first end coupled to the second amplifier (704a; 704b) and a second end for coupling with a circuit board (718a; 718b), a shielding member (710a; 710b) having a first end coupled to the integrated circuit die (701a; 701b) and a second end for coupling with a circuit board (718a; 718b), the shielding member (710a; 710b) situated at least partially between the second connector and the first connector (706a; 706b) and a capacitor. The capacitor has a first plate and a second plate.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: April 14, 2015
    Assignee: NXP, B.V.
    Inventors: Albert Gerardus Wilhelmus Philipus van Zuijlen, Vittorio Cuoco, Josephus Henricus Bartholomeus van der Zanden
  • Patent number: 8988114
    Abstract: Systems and methods for low-power voltage tamper detection are described. In some embodiments, an integrated circuit may include source-follower circuitry configured to produce a scaled down supply voltage. The integrated circuit may also include undervoltage detection circuitry coupled to the source-follower circuitry, the undervoltage detection circuitry configured to output a first signal having a first logic value if the scaled down supply voltage is greater than a low threshold voltage or a second logic value if the scaled down supply voltage is smaller than the low threshold voltage. Additionally or alternatively, the integrated circuit may include overvoltage detection circuitry coupled to the source-follower circuitry, the overvoltage detection circuitry configured to output a second signal having the first logic value if the scaled down supply voltage is smaller than a high threshold voltage or the second logic value if the scaled down supply voltage is greater than the high threshold voltage.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: March 24, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sanjay K. Wadhwa, Alfredo Olmos, Fabio Duarte De Martin
  • Patent number: 8988146
    Abstract: According to some embodiments, a switch having an “on” state and an “off” state is exhibiting a low impedance in the “on” state, and a very high impedance in the “off” state. The switch comprises three series MOS transistors, the first transistor having its drain connected to the input. The switch also comprises additional circuitry which reduces, in the “off” state, the leakage current of the MOS transistor connected to the input of the switch by connecting its source and bulk to an electrical node replicating the voltage of the input node. According to some embodiments, the said switch is used in a voltage amplifier for capacitive sensing devices, such as MEMS gyroscopes and MEMS microphones; the voltage amplifier uses an operational amplifier used in a trans-capacitance configuration, with the feedback path comprising the said switch and a capacitor, wherein the said switch is connected to the input of, the voltage amplifier.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: March 24, 2015
    Inventor: Ion E. Opris
  • Publication number: 20150077188
    Abstract: An amplifier circuit includes a first transistor, a second transistor, and a third transistor. The gate of the first transistor receives the input signal to the amplifier. The second transistor's drain terminal is connected to the first source terminal. The second transistor's source terminal is connected to a first supply node. The third transistor's gate terminal is connected to the first transistor's drain terminal via a first node. The third transistor's drain terminal is connected to a second supply node. The third transistor's source terminal is connected to the second transistor's gate terminal via a second node. The amplifier includes first current bias connected between the second node and the first supply node. The amplifier includes a second current bias connected between the first node and the second supply node.
    Type: Application
    Filed: December 26, 2013
    Publication date: March 19, 2015
    Inventor: Sanyi Zhan
  • Patent number: 8981852
    Abstract: A power amplifier includes a power amplifier core including a plurality of gain stages to receive a radio frequency (RF) signal and to output an amplified RF signal, an output network coupled to the power amplifier core to receive the amplified RF signal and output a transmit output power signal, and a directional coupler coupled to the output network to obtain a coupled signal proportional to the transmit output power signal. Each of these components can be configured on a single semiconductor die, in an embodiment.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: March 17, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Timothy Dupuis
  • Patent number: 8983406
    Abstract: This disclosure relates to a harmonic termination circuit that is separate from a load line. In one embodiment, the load line is configured to match an impedance at the power amplifier output at a fundamental frequency of the power amplifier output and the harmonic termination circuit is configured to terminate at a phase corresponding to a harmonic frequency of the power amplifier output. According to certain embodiments, the load line and the harmonic termination circuit can be electrically coupled to the power amplifier output external to a power amplifier die via different output pins of the power amplifier die.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: March 17, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventors: Guohao Zhang, Hardik Bhupendra Modi, Dinhphuoc Vu Hoang
  • Patent number: 8970300
    Abstract: Improved preamplifier circuits for converting single-ended input current signals to differential output voltage signals, including first and second transimpedance amplifiers with input transistors operating according to bias currents from a biasing circuit, output transistors and adjustable feedback impedances modified using an automatic gain control circuit, as well as a reference circuit controlling the bias currents according to an on-board reference current and the single-ended input or the differential output voltage signals from the transimpedance amplifiers.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: March 3, 2015
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Oliver Piepenstock, Gerd Schuppener, Frank Gelhausen, Ulrich Schacht
  • Patent number: 8963645
    Abstract: An integrated circuit amplifier comprises: a first planar substrate having an upper surface and a lower surface; a second planar substrate having an upper surface and a lower surface, the lower surface of the second planar substrate physically affixed to the upper surface of the first planar substrate; at least one transistor pair comprising a first and second transistor, formed in the upper surface of the second planar substrate; and a conductor electrically coupling a drain electrode of the first transistor to a source electrode of the second transistor. The first substrate material may have a higher thermal conductivity than the second substrate material. The first material may be Silicon Carbide and may have a thickness of about 10 mils. The second material may be Gallium Arsenide and may have a thickness of about 1 to 2 mils.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: February 24, 2015
    Assignee: Lockheed Martin Corporation
    Inventors: David R. Helms, John Ditri, Stuart R. Ducker, Dana J. Sturzebecher
  • Patent number: 8928411
    Abstract: Embodiments of the invention are generally directed to integration of signal sampling within a transistor amplifier stage. An embodiment of an apparatus includes a amplifier stage including a transistor to receive a source signal and produce an output signal, wherein the transistor includes multiple fingers for at least a first electrode of the transistor. The amplifier stage uses connections to some of the fingers of the first electrode for production of the output signal, and uses one or more other fingers for the first electrode of the transistor for a separate function from the production of the output signal.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 6, 2015
    Assignee: Silicon Image, Inc.
    Inventors: James R. Parker, Sohrab Emami
  • Patent number: 8896380
    Abstract: A high frequency amplifier is characterized wherein a power amplification element and at least one of temperature compensation elements are adjacently provided on a first semiconductor layer, a first wiring pattern connected to the power amplification element, a second wiring pattern connected to the temperature compensation element, and a ground electrode are provided on at least one of second semiconductor layers existing in layers different from the first semiconductor layer, and the ground electrode is formed on the second semiconductor layer corresponding to a region that substantially projects a crevice part on which the temperature compensation element and the power amplification element are provided, on the same plane as the first semiconductor element.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: November 25, 2014
    Assignee: TDK Corporation
    Inventors: Tomihiko Shibuya, Atsushi Ajioka, Atsushi Tsumita
  • Patent number: 8884700
    Abstract: A temperature control system having: a resistor formed in a region of a semiconductor, such resistor having a pair of spaced electrodes in ohmic contact with the semiconductor; at least one device formed in another region of the semiconductor thermally proximate the resistor formed region, such device generating heat in the semiconductor; and circuitry, including a reference connected to one of the pair of electrodes, for operating the resistor in saturation and for sensing variation in the resistor in response to the heat generated by the device and for controlling the heat generated by the device in the semiconductor in response to the sensed variation.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: November 11, 2014
    Assignee: Raytheon Company
    Inventors: Jon Mooney, Bryan G. Fast, David D. Heston
  • Patent number: 8865498
    Abstract: A method for manufacturing a three-dimensionally shaped comb-tooth electret electrode, provided with positive ions, includes: forming a three-dimensional movable comb-tooth electrode and a three-dimensional fixed comb-tooth electrode from an Si substrate; contacting a vapor including ions thereto, and forming an oxide layer including ions upon surfaces of the comb-tooth electrodes with heat applied thereto; and applying a voltage between the movable electrode and the fixed electrode with heat applied thereto, and thereby causing the ions included in the oxide layer to shift to a surface of the oxide layer; wherein, the voltage between the movable electrode and the fixed electrode is changed, so that the operation of each of the comb-teeth of the movable electrode being alternatingly pulled in against two opposed comb-teeth of the fixed electrode is repeated, and the pulling in voltage and the pulled-in state release voltage are gradually increased.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: October 21, 2014
    Assignee: AOI Electronics Co., Ltd.
    Inventors: Masato Suzuki, Hiroki Hayashi
  • Patent number: 8861749
    Abstract: An audio output circuit includes an on-chip left channel amplifier module, an on-chip center channel amplifier module, and an on-chip right channel amplifier module. A left channel IC pin is operably coupled to an output of the on-chip left channel amplifier module. A right channel IC pin is operably coupled to an output of the on-chip right channel amplifier module. A center channel IC pin is operably coupled to an output of the on-chip center channel amplifier module. A center channel feedback IC pin is operably coupled to an input of the on-chip center channel amplifier module to provide a feedback loop. A left jack connection is operably coupled to the left channel IC pin. A right jack connection is operably coupled to the right channel IC pin. A jack return connection coupled to the center feedback IC pin. An inductor has a first node coupled to the jack return connection and a second node coupled to the center channel IC pin.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: October 14, 2014
    Assignee: Sigmatel, Inc.
    Inventor: Matthew D. Felder
  • Patent number: 8847684
    Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: September 30, 2014
    Assignee: SuVolta, Inc.
    Inventors: Lawrence T. Clark, Scott E. Thompson
  • Publication number: 20140266470
    Abstract: This disclosure relates generally to radio frequency (RF) amplification devices and methods of operating the same. In one embodiment, an RF amplification device includes an RF amplification circuit and a stabilizing transformer network. The RF amplification circuit defines an RF signal path and is configured to amplify an RF signal propagating in the RF signal path. The stabilizing transformer network is operably associated with the RF signal path defined by the RF amplification circuit. Furthermore, the stabilizing transformer network is configured to reduce parasitic coupling along the RF signal path of the RF amplification circuit as the RF signal propagates in the RF signal path. In this manner, the stabilizing transformer network allows for inexpensive components to be used to reduce parasitic coupling while allowing for smaller distances along the RF signal path.
    Type: Application
    Filed: March 17, 2014
    Publication date: September 18, 2014
    Applicant: RF Micro Devices, Inc.
    Inventors: George Maxim, Baker Scott, Ming Tsai, Alireza Shirvani
  • Patent number: 8836429
    Abstract: There is provided a CMOS integrated circuit capable of avoiding deterioration of NF characteristic and achieving a high degree of linearity in the case in which an LNA circuit is formed on an SOI substrate and an LAN circuit is formed in a bulk CMOS process. The CMOS integrated circuit includes a field effect transistor having a gate electrode connected to a signal input terminal, a drain electrode connected to a power terminal, and a source electrode connected to a ground terminal, wherein the field effect transistor is formed on the SOI substrate and a connection between a body potential and a potential lower than a source potential are formed by a resistor element. The deterioration of NF characteristic can be avoided and a high degree of linearity can be achieved by using this CMOS integrated circuit.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: September 16, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Tadamasa Murakami
  • Patent number: 8836433
    Abstract: Apparatus and methods for electronic amplification are disclosed herein. In certain implementations, an amplifier is provided for amplifying a RF signal, and the amplifier includes a first transistor and a second transistor electrically connected in a Darlington configuration. The first and second transistors can be, for example, bipolar or field effect transistors and the first transistor can amplify an input signal and provide the amplified input signal to the second transistor. The first and second transistors are electrically connected to a power low node such as a ground node through first and second bias circuits, respectively. In certain implementations, the first transistor includes an inductor disposed in the path from the first transistor to the power low voltage. By including the inductor in the path from the first transistor to the ground node, the third order distortion of the amplifier can be improved.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: September 16, 2014
    Assignee: Skyworks Solutions, Inc.
    Inventors: David Dening, Alan W Ake
  • Patent number: 8829999
    Abstract: A low noise amplifier includes a first Group III-nitride based transistor and a second Group III-nitride based transistor coupled to the first Group III-nitride based transistor. The first Group III-nitride based transistor is configured to provide a first stage of amplification to an input signal, and the second Group III-nitride based transistor is configured to provide a second stage of amplification to the input signal.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: September 9, 2014
    Assignee: Cree, Inc.
    Inventor: Jeremy Fisher
  • Publication number: 20140225675
    Abstract: A low noise amplifier for radio frequency integrated circuits having an adaptive input and operating mode selection. The low noise amplifier comprises two inputs which can be operated in different configurations. The operating mode may be chosen in such way that the inputs are used respectively one at the time for single-ended configuration or both inputs are used for differential configuration. Additionally, in single-ended operation, inputs can be matched to different frequencies. The information regarding the operating mode is obtained from an external component. The operating mode to be used may be determined when the device using a particular radio frequency integrated circuit is designed or it can be determined dynamically by the device using the radio frequency integrated circuit.
    Type: Application
    Filed: January 15, 2014
    Publication date: August 14, 2014
    Applicant: Broadcom Corporation
    Inventors: Jouni Kristian KAUKOVUORI, Jonne Riekki, Jari Heikkinen
  • Patent number: 8797104
    Abstract: A low-noise amplifier includes a first transistor having a gate configured to receive an oscillating input signal and a source coupled to ground. A second transistor has a source coupled to a drain of the first transistor, a gate coupled to a bias voltage, and a drain coupled to an output node. At least one of the first and second transistors includes a floating deep n-well that is coupled to an isolation circuit.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsieh-Hung Hsieh, Yi-Hsuan Liu, Chiao-Han Lee, Tzu-Jin Yeh, Chewn-Pu Jou
  • Patent number: 8797103
    Abstract: Apparatus and methods for capacitive load reduction are disclosed. In one embodiment, a power amplifier system includes an envelope tracker configured to provide a supply voltage to a plurality of power amplifiers. The power amplifiers include power supply inputs electrically connected in a star configuration so as to reduce a capacitive load of the envelope tracker. The distributed capacitance of the power amplifiers is used to provide RF grounding so as to reduce the size of or eliminated the use of bypass capacitors.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: August 5, 2014
    Assignee: Skyworks Solutions, Inc.
    Inventors: Daniel Lee Kaczman, James Phillip Young
  • Patent number: 8781028
    Abstract: Integrated receiving circuit for radiofrequency signals an amplifying element using the multiplication zone of a reverse biased semiconductor junction operating in Geiger mode for amplifying an input radiofrequency signal (Vin) and converting it into a digital signal. And a digital part for digitally processing the digital signal.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: July 15, 2014
    Assignee: Ecole Polytechnique Federale de Lausanne (EPFL)
    Inventors: Edoardo Charbon, Marek Gersbach, Maximilian Sergio
  • Patent number: 8766427
    Abstract: An RF-power device includes a semiconductor substrate having a plurality of active regions arranged in an array. Each active region includes one or more RF-power transistors. The active regions are interspersed with inactive regions for reducing mutual heating of the RF-power transistors in separate active regions. The devices also includes at least one impedance matching component located in one of the inactive regions of the substrate.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: July 1, 2014
    Assignee: NXP, B.V.
    Inventor: Marnix Bernard Willemsen
  • Publication number: 20140132355
    Abstract: A power amplifier includes a power amplifier core including a plurality of gain stages to receive a radio frequency (RF) signal and to output an amplified RF signal, an output network coupled to the power amplifier core to receive the amplified RF signal and output a transmit output power signal, and a directional coupler coupled to the output network to obtain a coupled signal proportional to the transmit output power signal. Each of these components can be configured on a single semiconductor die, in an embodiment.
    Type: Application
    Filed: November 12, 2012
    Publication date: May 15, 2014
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd
    Inventor: Timothy Dupuis
  • Publication number: 20140132353
    Abstract: An integrated power amplifier circuit is disclosed. The circuit comprises: first and second amplifiers fabricated on one or more dies, the one or more dies being mounted on a support structure; a first set of one or more connection elements connected to the first amplifier and passing above a portion of the support structure; and a second set of one or more connection elements connected to the second amplifier and passing above a portion of the support structure. The support structure comprises at least one void, at least a portion of the at least one void being positioned directly underneath at least one of the first and second sets of one or more connection elements.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 15, 2014
    Applicant: NXP B.V.
    Inventors: Vittorio Cuoco, Josephus Henricus Bartholomeus van der Zanden, Albert Gerardus Wilhelmus Philipus van Zuijlen
  • Patent number: 8717105
    Abstract: A photodetecting device 1 includes a photodiode PD and an integrating circuit 11. The integrating circuit 11 includes an amplifier circuit 20, a capacitive element C2, and a second switch SW2. The amplifier circuit 20 has a driving section including a PMOS transistor T1 and an NMOS transistor T2, the respective drain terminals thereof being connected to each other. A first switch SW1 comprising a PMOS transistor T10 is opened or closed according to the level of a first reset signal Reset1 input to the gate terminal. When the first reset signal Reset1 is at a low level, the first switch SW1 is closed to apply a power supply potential VDD to the gate terminal of the PMOS transistor T1, thereby turning off the PMOS transistor T1. Thus, an amplifier circuit, an integrating circuit and a photodetecting device capable of achieving both low power consumption and high speed can be realized.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: May 6, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Haruhiro Funakoshi, Shinya Ito
  • Patent number: 8710928
    Abstract: A semiconductor power amplifier of an embodiment includes: a plurality of unit FETs disposed in parallel in a direction of a substantially straight line connecting source electrodes of the unit FETs; a first via hole which connects the two source electrodes positioned between adjacent ones of the unit FETs in common and an RF ground electrode; and a second via hole which connects the source electrode on a side having no adjacent unit FET and the RF ground electrode. Each unit FET includes: a gate electrode which connects gate finger electrodes and leads out the gate finger electrodes; a drain electrode which connects drain finger electrodes disposed facing the gate finger electrodes and leads out the drain finger electrodes; and two source electrodes which connects source finger electrodes disposed facing the gate finger electrodes and lead out the source finger electrodes to opposing sides in a widthwise direction thereof.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: April 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Choon Yong Ng
  • Publication number: 20140104004
    Abstract: Radio Frequency (RF) amplifier circuits are disclosed which may exhibit improved video/instantaneous bandwidth performance compared to conventional circuits. For example, disclosed RF amplifier circuits may employ a baseband decoupling network connected in parallel with a low-pass RF matching network of the amplifier circuit.
    Type: Application
    Filed: October 15, 2013
    Publication date: April 17, 2014
    Applicant: NXP B.V.
    Inventors: Gerard Jean-Louis Bouisse, Jean-Jacques Bouny