Abstract: According to example embodiments, a power device chip includes a plurality of unit power devices classified into a plurality of sectors, a first pad and a second pad. At least one of the first and second pads is divided into a number of pad parts equal to a number of the plurality of sectors. The first pad is connected to first electrodes of the plurality of unit power devices, and the second pad is connected to second electrodes of the plurality of unit power devices. The unit power devices may be diodes. The power device chip may further include third electrodes in the plurality of unit power devices, and a third pad may be connected to the third electrodes. In this case, the unit power devices may be high electron mobility transistors (HEMTs). Pad parts connected to defective sectors may be excluded from bonding.

Abstract: A radio frequency amplifier circuit includes a transistor and an output-side matching circuit. The output-side matching circuit includes a first distributed constant line to which a radio frequency signal from the transistor is transmitted, a flat plate lead terminal transmitting the radio frequency signal from the first distributed constant line to an outside of the package, and a capacitive element having one electrode that is connected to the lead terminal and the other electrode that is grounded. A back surface of the lead terminal is joined to a resin substrate, and the capacitive element and the first distributed constant line are disposed adjacent to each other, with an alignment direction of the capacitive element and the first distributed constant line intersecting an alignment direction of the first distributed constant line and the lead terminal.

Abstract: Gate line driver circuitry applies an output pulse to each of several gate lines for a display element array. The circuitry has a number of gate drivers each being coupled to drive a respective one of the gate lines. Each of the gate drivers has an output stage in which a high side transistor and a low side transistor are coupled to drive the respective gate line, responsive to at least one clock signal. A pull down transistor is coupled to discharge a control electrode of the output stage. A control circuit having a cascode amplifier is coupled to drive the pull down transistor as a function of a) at least one clock signal and b) feedback from the control electrode. Other embodiments are also described and claimed.

Abstract: A system and method improve amplifier efficiency of operation relative to that of a matching circuit with fixed matching conditions. A power level representing a level of transmission power from an amplifier circuit and an indicator of amplifier circuit operation are provided. The indicator is at least one of channel, channel bandwidth, out-of band spectral requirements, spectral mask requirements, error vector magnitude, modulation rate, and modulation type. The matching conditions for a matching circuit of an amplifying transistor are adjusted based at least in part on the power level and the indication where the matching conditions are different for channels at an edge of a channel band than for channels nearer a center of the channel band.

Abstract: A semiconductor package device comprises a radio frequency power transistor having an output port operably coupled to a single de-coupling capacitance located within the semiconductor package device. The single de-coupling capacitance is arranged to provide both high frequency decoupling and low frequency decoupling of signals output from the radio frequency power transistor.

Abstract: A power amplifier module includes a power amplifier including a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3×1016 cm?3 at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base; and an RF transmission line driven by the power amplifier, the RF transmission line including a conductive layer and finish plating on the conductive layer, the finish plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness that is less than about the skin depth of nickel at 0.9 GHz. Other embodiments of the module are provided along with related methods and components thereof.

Abstract: An amplifier includes a transistor chip, a matching chip with a capacitor group having multiple MIM capacitors, each of the MIM capacitors including a lower electrode, a dielectric, and an upper electrode, a bonding wire that electrically connects the transistor chip to the upper electrode of any one of the MIM capacitors of the capacitor group and transmits a high-frequency signal, and a case that accommodates the transistor chip and the matching chip. The lower electrodes of the MIM capacitors are grounded, and capacitance values of each of the MIM capacitors of the capacitor group are different from each other.

Abstract: The disclosure relates to an amplifier device comprising an integrated circuit die (701a; 701b) having a first amplifier (702a; 702b) and a second amplifier. A Doherty amplifier may be implemented in accordance with the present invention. The amplifier device also comprises a first connector (706a; 706b) having a first end coupled to the first amplifier and a second end for coupling with a circuit board (718a; 718b), a second connector (708a; 708b) having a first end coupled to the second amplifier (704a; 704b) and a second end for coupling with a circuit board (718a; 718b), a shielding member (710a; 710b) having a first end coupled to the integrated circuit die (701a; 701b) and a second end for coupling with a circuit board (718a; 718b), the shielding member (710a; 710b) situated at least partially between the second connector and the first connector (706a; 706b) and a capacitor. The capacitor has a first plate and a second plate.

Abstract: According to some embodiments, a switch having an “on” state and an “off” state is exhibiting a low impedance in the “on” state, and a very high impedance in the “off” state. The switch comprises three series MOS transistors, the first transistor having its drain connected to the input. The switch also comprises additional circuitry which reduces, in the “off” state, the leakage current of the MOS transistor connected to the input of the switch by connecting its source and bulk to an electrical node replicating the voltage of the input node. According to some embodiments, the said switch is used in a voltage amplifier for capacitive sensing devices, such as MEMS gyroscopes and MEMS microphones; the voltage amplifier uses an operational amplifier used in a trans-capacitance configuration, with the feedback path comprising the said switch and a capacitor, wherein the said switch is connected to the input of, the voltage amplifier.

Abstract: Systems and methods for low-power voltage tamper detection are described. In some embodiments, an integrated circuit may include source-follower circuitry configured to produce a scaled down supply voltage. The integrated circuit may also include undervoltage detection circuitry coupled to the source-follower circuitry, the undervoltage detection circuitry configured to output a first signal having a first logic value if the scaled down supply voltage is greater than a low threshold voltage or a second logic value if the scaled down supply voltage is smaller than the low threshold voltage. Additionally or alternatively, the integrated circuit may include overvoltage detection circuitry coupled to the source-follower circuitry, the overvoltage detection circuitry configured to output a second signal having the first logic value if the scaled down supply voltage is smaller than a high threshold voltage or the second logic value if the scaled down supply voltage is greater than the high threshold voltage.

Abstract: An amplifier circuit includes a first transistor, a second transistor, and a third transistor. The gate of the first transistor receives the input signal to the amplifier. The second transistor's drain terminal is connected to the first source terminal. The second transistor's source terminal is connected to a first supply node. The third transistor's gate terminal is connected to the first transistor's drain terminal via a first node. The third transistor's drain terminal is connected to a second supply node. The third transistor's source terminal is connected to the second transistor's gate terminal via a second node. The amplifier includes first current bias connected between the second node and the first supply node. The amplifier includes a second current bias connected between the first node and the second supply node.

Abstract: A power amplifier includes a power amplifier core including a plurality of gain stages to receive a radio frequency (RF) signal and to output an amplified RF signal, an output network coupled to the power amplifier core to receive the amplified RF signal and output a transmit output power signal, and a directional coupler coupled to the output network to obtain a coupled signal proportional to the transmit output power signal. Each of these components can be configured on a single semiconductor die, in an embodiment.

Abstract: This disclosure relates to a harmonic termination circuit that is separate from a load line. In one embodiment, the load line is configured to match an impedance at the power amplifier output at a fundamental frequency of the power amplifier output and the harmonic termination circuit is configured to terminate at a phase corresponding to a harmonic frequency of the power amplifier output. According to certain embodiments, the load line and the harmonic termination circuit can be electrically coupled to the power amplifier output external to a power amplifier die via different output pins of the power amplifier die.

Abstract: Improved preamplifier circuits for converting single-ended input current signals to differential output voltage signals, including first and second transimpedance amplifiers with input transistors operating according to bias currents from a biasing circuit, output transistors and adjustable feedback impedances modified using an automatic gain control circuit, as well as a reference circuit controlling the bias currents according to an on-board reference current and the single-ended input or the differential output voltage signals from the transimpedance amplifiers.

Abstract: An integrated circuit amplifier comprises: a first planar substrate having an upper surface and a lower surface; a second planar substrate having an upper surface and a lower surface, the lower surface of the second planar substrate physically affixed to the upper surface of the first planar substrate; at least one transistor pair comprising a first and second transistor, formed in the upper surface of the second planar substrate; and a conductor electrically coupling a drain electrode of the first transistor to a source electrode of the second transistor. The first substrate material may have a higher thermal conductivity than the second substrate material. The first material may be Silicon Carbide and may have a thickness of about 10 mils. The second material may be Gallium Arsenide and may have a thickness of about 1 to 2 mils.

Abstract: Embodiments of the invention are generally directed to integration of signal sampling within a transistor amplifier stage. An embodiment of an apparatus includes a amplifier stage including a transistor to receive a source signal and produce an output signal, wherein the transistor includes multiple fingers for at least a first electrode of the transistor. The amplifier stage uses connections to some of the fingers of the first electrode for production of the output signal, and uses one or more other fingers for the first electrode of the transistor for a separate function from the production of the output signal.

Abstract: A high frequency amplifier is characterized wherein a power amplification element and at least one of temperature compensation elements are adjacently provided on a first semiconductor layer, a first wiring pattern connected to the power amplification element, a second wiring pattern connected to the temperature compensation element, and a ground electrode are provided on at least one of second semiconductor layers existing in layers different from the first semiconductor layer, and the ground electrode is formed on the second semiconductor layer corresponding to a region that substantially projects a crevice part on which the temperature compensation element and the power amplification element are provided, on the same plane as the first semiconductor element.

Abstract: A temperature control system having: a resistor formed in a region of a semiconductor, such resistor having a pair of spaced electrodes in ohmic contact with the semiconductor; at least one device formed in another region of the semiconductor thermally proximate the resistor formed region, such device generating heat in the semiconductor; and circuitry, including a reference connected to one of the pair of electrodes, for operating the resistor in saturation and for sensing variation in the resistor in response to the heat generated by the device and for controlling the heat generated by the device in the semiconductor in response to the sensed variation.

Abstract: A method for manufacturing a three-dimensionally shaped comb-tooth electret electrode, provided with positive ions, includes: forming a three-dimensional movable comb-tooth electrode and a three-dimensional fixed comb-tooth electrode from an Si substrate; contacting a vapor including ions thereto, and forming an oxide layer including ions upon surfaces of the comb-tooth electrodes with heat applied thereto; and applying a voltage between the movable electrode and the fixed electrode with heat applied thereto, and thereby causing the ions included in the oxide layer to shift to a surface of the oxide layer; wherein, the voltage between the movable electrode and the fixed electrode is changed, so that the operation of each of the comb-teeth of the movable electrode being alternatingly pulled in against two opposed comb-teeth of the fixed electrode is repeated, and the pulling in voltage and the pulled-in state release voltage are gradually increased.

Abstract: An audio output circuit includes an on-chip left channel amplifier module, an on-chip center channel amplifier module, and an on-chip right channel amplifier module. A left channel IC pin is operably coupled to an output of the on-chip left channel amplifier module. A right channel IC pin is operably coupled to an output of the on-chip right channel amplifier module. A center channel IC pin is operably coupled to an output of the on-chip center channel amplifier module. A center channel feedback IC pin is operably coupled to an input of the on-chip center channel amplifier module to provide a feedback loop. A left jack connection is operably coupled to the left channel IC pin. A right jack connection is operably coupled to the right channel IC pin. A jack return connection coupled to the center feedback IC pin. An inductor has a first node coupled to the jack return connection and a second node coupled to the center channel IC pin.

Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.

Abstract: This disclosure relates generally to radio frequency (RF) amplification devices and methods of operating the same. In one embodiment, an RF amplification device includes an RF amplification circuit and a stabilizing transformer network. The RF amplification circuit defines an RF signal path and is configured to amplify an RF signal propagating in the RF signal path. The stabilizing transformer network is operably associated with the RF signal path defined by the RF amplification circuit. Furthermore, the stabilizing transformer network is configured to reduce parasitic coupling along the RF signal path of the RF amplification circuit as the RF signal propagates in the RF signal path. In this manner, the stabilizing transformer network allows for inexpensive components to be used to reduce parasitic coupling while allowing for smaller distances along the RF signal path.

Abstract: Apparatus and methods for electronic amplification are disclosed herein. In certain implementations, an amplifier is provided for amplifying a RF signal, and the amplifier includes a first transistor and a second transistor electrically connected in a Darlington configuration. The first and second transistors can be, for example, bipolar or field effect transistors and the first transistor can amplify an input signal and provide the amplified input signal to the second transistor. The first and second transistors are electrically connected to a power low node such as a ground node through first and second bias circuits, respectively. In certain implementations, the first transistor includes an inductor disposed in the path from the first transistor to the power low voltage. By including the inductor in the path from the first transistor to the ground node, the third order distortion of the amplifier can be improved.

Abstract: There is provided a CMOS integrated circuit capable of avoiding deterioration of NF characteristic and achieving a high degree of linearity in the case in which an LNA circuit is formed on an SOI substrate and an LAN circuit is formed in a bulk CMOS process. The CMOS integrated circuit includes a field effect transistor having a gate electrode connected to a signal input terminal, a drain electrode connected to a power terminal, and a source electrode connected to a ground terminal, wherein the field effect transistor is formed on the SOI substrate and a connection between a body potential and a potential lower than a source potential are formed by a resistor element. The deterioration of NF characteristic can be avoided and a high degree of linearity can be achieved by using this CMOS integrated circuit.

Abstract: A low noise amplifier includes a first Group III-nitride based transistor and a second Group III-nitride based transistor coupled to the first Group III-nitride based transistor. The first Group III-nitride based transistor is configured to provide a first stage of amplification to an input signal, and the second Group III-nitride based transistor is configured to provide a second stage of amplification to the input signal.

Abstract: A low noise amplifier for radio frequency integrated circuits having an adaptive input and operating mode selection. The low noise amplifier comprises two inputs which can be operated in different configurations. The operating mode may be chosen in such way that the inputs are used respectively one at the time for single-ended configuration or both inputs are used for differential configuration. Additionally, in single-ended operation, inputs can be matched to different frequencies. The information regarding the operating mode is obtained from an external component. The operating mode to be used may be determined when the device using a particular radio frequency integrated circuit is designed or it can be determined dynamically by the device using the radio frequency integrated circuit.

Abstract: Apparatus and methods for capacitive load reduction are disclosed. In one embodiment, a power amplifier system includes an envelope tracker configured to provide a supply voltage to a plurality of power amplifiers. The power amplifiers include power supply inputs electrically connected in a star configuration so as to reduce a capacitive load of the envelope tracker. The distributed capacitance of the power amplifiers is used to provide RF grounding so as to reduce the size of or eliminated the use of bypass capacitors.

Abstract: A low-noise amplifier includes a first transistor having a gate configured to receive an oscillating input signal and a source coupled to ground. A second transistor has a source coupled to a drain of the first transistor, a gate coupled to a bias voltage, and a drain coupled to an output node. At least one of the first and second transistors includes a floating deep n-well that is coupled to an isolation circuit.

Abstract: Integrated receiving circuit for radiofrequency signals an amplifying element using the multiplication zone of a reverse biased semiconductor junction operating in Geiger mode for amplifying an input radiofrequency signal (Vin) and converting it into a digital signal. And a digital part for digitally processing the digital signal.

Abstract: An RF-power device includes a semiconductor substrate having a plurality of active regions arranged in an array. Each active region includes one or more RF-power transistors. The active regions are interspersed with inactive regions for reducing mutual heating of the RF-power transistors in separate active regions. The devices also includes at least one impedance matching component located in one of the inactive regions of the substrate.

Abstract: An integrated power amplifier circuit is disclosed. The circuit comprises: first and second amplifiers fabricated on one or more dies, the one or more dies being mounted on a support structure; a first set of one or more connection elements connected to the first amplifier and passing above a portion of the support structure; and a second set of one or more connection elements connected to the second amplifier and passing above a portion of the support structure. The support structure comprises at least one void, at least a portion of the at least one void being positioned directly underneath at least one of the first and second sets of one or more connection elements.

Abstract: A power amplifier includes a power amplifier core including a plurality of gain stages to receive a radio frequency (RF) signal and to output an amplified RF signal, an output network coupled to the power amplifier core to receive the amplified RF signal and output a transmit output power signal, and a directional coupler coupled to the output network to obtain a coupled signal proportional to the transmit output power signal. Each of these components can be configured on a single semiconductor die, in an embodiment.

Abstract: A photodetecting device 1 includes a photodiode PD and an integrating circuit 11. The integrating circuit 11 includes an amplifier circuit 20, a capacitive element C2, and a second switch SW2. The amplifier circuit 20 has a driving section including a PMOS transistor T1 and an NMOS transistor T2, the respective drain terminals thereof being connected to each other. A first switch SW1 comprising a PMOS transistor T10 is opened or closed according to the level of a first reset signal Reset1 input to the gate terminal. When the first reset signal Reset1 is at a low level, the first switch SW1 is closed to apply a power supply potential VDD to the gate terminal of the PMOS transistor T1, thereby turning off the PMOS transistor T1. Thus, an amplifier circuit, an integrating circuit and a photodetecting device capable of achieving both low power consumption and high speed can be realized.

Abstract: A semiconductor power amplifier of an embodiment includes: a plurality of unit FETs disposed in parallel in a direction of a substantially straight line connecting source electrodes of the unit FETs; a first via hole which connects the two source electrodes positioned between adjacent ones of the unit FETs in common and an RF ground electrode; and a second via hole which connects the source electrode on a side having no adjacent unit FET and the RF ground electrode. Each unit FET includes: a gate electrode which connects gate finger electrodes and leads out the gate finger electrodes; a drain electrode which connects drain finger electrodes disposed facing the gate finger electrodes and leads out the drain finger electrodes; and two source electrodes which connects source finger electrodes disposed facing the gate finger electrodes and lead out the source finger electrodes to opposing sides in a widthwise direction thereof.

Abstract: Radio Frequency (RF) amplifier circuits are disclosed which may exhibit improved video/instantaneous bandwidth performance compared to conventional circuits. For example, disclosed RF amplifier circuits may employ a baseband decoupling network connected in parallel with a low-pass RF matching network of the amplifier circuit.

Abstract: The present invention relates to a micro CMOS power amplifier, in which an output transformer is configured as a substrate of a multilayer structure, and an amplifier circuit module is stacked on the output transformer. The micro CMOS power amplifier includes: an amplifier circuit module chip configured by modularizing circuits for amplifying power as a module; and an output transformer for outputting output of the amplifier circuit module chip to outside through a transformer circuit, in which the output transformer is implemented on a multilayer substrate, and the amplifier circuit module chip and the output transformer are configured as a stack. According to the micro CMOS power amplifier of the present invention described above, an output transformer occupying a large space in a conventional power amplifier is configured as a multilayer substrate, and thus the chip size can be reduced within 50% without decreasing output power of the power amplifier.

Abstract: A class-AB power amplifier according to the present embodiment includes an amplifying element whose power supply voltage is expressed as Vdc and whose maximum current is expressed as Imax, a conduction angle ?o of the amplifying element being more than ?(rad) and less than 2·?(rad), and load impedance of a fundamental wave being expressed as Z1=R1+j·X1, load impedance of a 2nd harmonic being expressed as Z2=R2+j·X2, and load impedance of a 3rd harmonic being expressed as Z3=R3+j?X3 which are observed from a dependent current source of an equivalent circuit of the amplifying element, and a relationship between variables X1 and R1 is set to ?0.5·R1<=X1<=0.5·R1, variable R1 is set to R1=Vdc/Imax·{1?cos(?o/2)}·?/{?o/2?sin(?o)/2}, variable X2/X1 is set to X2/X1=?2·{?o?sin(?o)}/{sin(?o/2)?sin(1.5·?o)/3}, and variable X3/X1 is set to X3/X1={?o?sin(?o)}/{sin(?o)/3?sin(2·?o)/6}, or each of the variables is set thereto so as to become equal substantially.

Abstract: A monolithic integrated circuit (IC) chip containing a plurality of transistors, including: a substrate; a first transistor on the substrate; and a second transistor integrally formed on the substrate with the first transistor, the second transistor having a different structure than the first transistor, wherein the first transistor includes a first material system and the second transistor includes a second material system different from the first material system. The monolithic IC chip may further include a third transistor integrally formed on the substrate with the first and second transistors. The first transistor may include gallium nitride (GaN) and the second and third transistors may include silicon carbide (SiC).

Abstract: In accordance with an embodiment, a low noise amplifier (LNA) includes a transistor, and a transformer having a first winding coupled between a LNA input terminal and a control node of the transistor, and a second winding magnetically coupled to the first winding coupled between a reference node of the transistor and a LNA reference terminal. An output of the LNA is coupled to an output node of the transistor.

Abstract: A semiconductor device includes a semiconductor chip in which an internal circuit is formed, with the internal circuit having an output signal that fluctuates due to variation of fluctuation in electrical characteristics of multiple circuit elements constituting the internal circuit; a chip tab on which the semiconductor chip is mounted, with the semiconductor chip completely overlapping the chip tab and the circuit elements in the semiconductor chip arranged on the chip tab, and encapsulation resin within which the semiconductor chip and the chip tab are sealed. A horizontal surface area of the chip tab is smaller than that of the semiconductor chip, and a distance between a periphery of the chip tab and a periphery of the semiconductor chip is sufficient to cause stress exerted on the semiconductor chip by the encapsulation resin to be uniform across the horizontal surface area of the chip tab.

Abstract: According to an embodiment, a power amplifier includes: an MMIC substrate; a high frequency probe pad disposed on the MMIC substrate; and a metal plate disposed on the MMIC substrate so as to adjoin to the high frequency probe pad, and connected to an MMIC external circuit via a bonding wire.

Abstract: An external audio signal is input to an input terminal which is connected to the first terminal of a first resistor. The first terminal of a second resistor is connected to the second terminal of the first resistor. An operational amplifier is arranged such that its inverting input terminal is connected to the second terminal of the second resistor, and a reference voltage is applied to its non-inverting input terminal. A third resistor is arranged between the output terminal and the inverting input terminal of the operational amplifier. A first diode is arranged between the second terminal of the first resistor and a power supply terminal such that its cathode is on the power supply terminal side. Furthermore, a second diode is arranged between the second terminal of the first resistor and the ground such that its cathode is on the second terminal side of the first resistor.

Abstract: Disclosed is a high-frequency power amplifier device capable of reducing a talk current. For example, the high-frequency power amplifier device has first and second power amplifier circuits, first and second transmission lines, and a region in which the first and second transmission lines are disposed close to each other. Either the first or second power amplifier circuit becomes activated in accordance with an output level. When the second power amplifier circuit is activated, currents flowing in the first and second transmission lines are transmitted in the same direction so that magnetic coupling occurs to strengthen each transmission line's magnetic force. When, on the other hand, the first power amplifier circuit is activated, currents flowing in the first and second transmission lines are transmitted in the opposite directions so that magnetic coupling occurs to weaken each transmission line's magnetic force.

Abstract: A wireless communication system includes: a filter; and a semiconductor chip including a signal processing integrated circuit having an amplifier, wherein a main surface of the semiconductor chip is provided with a plurality of electrode terminals along an edge portion thereof; wherein the amplifier has a transistor including a control electrode, a first electrode through which a signal is outputted, and a second electrode to which a voltage is applied; wherein the control electrode, the first electrode and the second electrode of the transistor are connected to the electrode terminals, respectively; and wherein none of wirings are arranged between the electrode terminals and placements of the control electrode, the first electrode and the second electrode, making space between the electrodes and the electrode terminals narrow.

Abstract: A technology is provided so that RF modules used for cellular phones etc. can be reduced in size. Over a wiring board constituting an RF module, there are provided a first semiconductor chip in which an amplifier circuit is formed and a second semiconductor chip in which a control circuit for controlling the amplifier circuit is formed. A bonding pad over the second semiconductor chip is connected with a bonding pad over the first semiconductor chip directly by a wire without using a relay pad. In this regard, the bonding pad formed over the first semiconductor chip is not square but rectangular (oblong).

Abstract: A power amplifier according to the present invention includes: an input-side transformer which has an annular primary coil which is a first metal line and a plurality of linear secondary coils which are second metal lines, and matches input impedance and divides the input signal into a plurality of split signals; push-pull amplifiers each including a pair of transistors for amplifying one of the split signals; and an output-side transformer which has an annular secondary coil which is a third metal line and a plurality of linear primary coils which are fourth metal lines, and combines the amplified split signals and matches output impedance, two input terminals of the pair of transistors being connected to each other via each of the second metal lines and two output terminal of the pair of transistors being connected to each other via each of the fourth metal lines.

Abstract: In a mobile wireless telecommunication device, a bidirectional serial interface is used to transfer a digital representation of an analog value from a first chip associated with a power amplifier module to a second chip. In an exemplary embodiment, circuitry on the first chip receives this clock signal from the second chip during the address portion of a read operation and uses this clock signal to generate a conversion clock signal. An analog-to-digital converter (ADC) on the first chip operates in response to the conversion clock signal to convert an analog value to a digital output. Circuitry on the first chip then transfers the digital output of the ADC from the first chip to the second chip via the serial interface.

Abstract: A reference buffer amplifier within an integrated circuit includes a first output terminal connected to a first bond pad, the first bond pad being connected to a first external pin of the integrated circuit chip, the first external pin to allow an external capacitance to be connected to the output terminal. The reference buffer further includes a variable, settable resistance sub-circuit connected to a second bond pad, the second bond pad also being connected to the first external pin. The resistance sub-circuit is configured to be set to exhibit a resistance value to critically dampen a response of the reference buffer amplifier.

Abstract: Embodiments of the invention are concerned with configurable RFICs. In an exemplary embodiment there is provided a configurable radio-frequency integrated circuit (RFIC) including one or more configurable low noise amplifier circuits, each of said one or more configurable low noise amplifier circuits being configurable between: an internal input impedance matching topology in which the respective low noise amplifier circuit includes one or more internal input impedance matching components adapted to match the input impedance of the respective low noise amplifier to a given input, said one or more internal input impedance matching components being located internally to the respective low noise amplifier circuit; and a topology different from said internal input impedance matching topology.

Abstract: Techniques for reducing undesired source degeneration inductance are disclosed. In an exemplary design, an apparatus includes first and second connections. The first connection includes a first parasitic inductance acting as a source degeneration inductance of an amplifier. The second connection includes a second parasitic inductance magnetically coupled to the first parasitic inductance to reduce the source degeneration inductance of the amplifier. The amplifier (e.g., a single-ended power amplifier) may be coupled to circuit ground via the first connection. An impedance matching circuit may be coupled to the amplifier and may include a circuit component coupled to circuit ground via the second connection. The first connection may be located sufficiently close to (e.g., within a predetermined distance of) the second connection in order to obtain the desired magnetic coupling between the first and second parasitic inductances.