Abstract: A small-sized on-chip complementary metal-oxide semiconductor (CMOS) Power Amplifier having improved efficiency is provided herein. The on-chip CMOS power amplifier is capable of improving efficiency and maximizing output thereof by enhancing a K factor, which may cause a problem in a power amplifier having a distributed active transformer structure. The on-chip CMOS power amplifier having an improved efficiency and being fabricated in a small size, the on-chip CMOS power amplifier includes a primary winding located at a first layer, secondary windings located at a second layer, which is an upper part of the first layer, the secondary windings being located corresponding to a position of the primary winding, and a cross section for coupling the second windings with each other.

Abstract: An inductor element containing circuit board of the present invention comprises a plurality of conductive layers, and a conductor having an inductor function (inductor conductor segment) in one or more of the conductive layers, wherein at least part of the inductor conductor segment is made thicker than other conductors disposed within the circuit board. The at least part of the inductor conductor segment extends through an insulating layer disposed between the conductive layers, or is embedded in the insulating layer, wherein the part of the inductor conductor segment has a thickness one-half or more the thickness of the insulating layer. A power amplifier module of the present invention comprises the multi-layer circuit board, a semiconductor amplifier fabricated in the multi-layer circuit board, and an impedance matching circuit coupled to the output of the semiconductor amplifier. The impedance matching circuit has a portion thereof formed of the inductor conductor segment.

Abstract: A receiving amplifier includes a semiconductor body with a first node, a second node and an amplifier circuit. The amplifier includes at least one field-effect transistor, a first input, and a second input. A capacitive element is arranged between the inputs of the amplifier circuit, and a tuned circuit whose resonant frequency can be tuned is connected upstream of the amplifier circuit and contains a variable-capacitance element that is connected in parallel with the element in the amplifier circuit. Two inductive elements are also provided, wherein the first inductive element is connected to the first node and the second inductive element is connected to the second node. This results in a series tuned circuit, which leads to a voltage increase at the resonant frequency, and results in an improved signal-to-noise ratio for a signal which is supplied to the receiving amplifier.

Abstract: Power amplifier circuits which constitute an RF power module used for a digital device capable of handling high frequency signals in two frequency bands are disposed over the same IC chip. The power amplifier circuits are disposed around the IC chip, and a secondary circuit is disposed between the power amplifier circuits. Thus, the power amplifier circuits are provided within the same IC chip to enable a size reduction. Further, the distance between the power amplifier circuits is ensured even if the power amplifier circuits are provided within the same IC chip. It is therefore possible to suppress the coupling between the power amplifier circuits and restrain crosstalk between the power amplifier circuits.

Abstract: A radio frequency (RF) module includes a first substrate adapted to receive passive circuits; and a second substrate adapted to receive active circuits, the first and second substrates electrically coupled through pads positioned on opposing surfaces of the first and second substrate.

Abstract: A multiple op amp IC with a single low noise op amp configuration comprises at least two op amp circuits fabricated on a common substrate. The IC can be configured such that the multiple op amps are connected in parallel to form a single op amp having output drive and input-referred noise characteristics which are superior to those of the constituent op amps. The IC can be fabricated with either first or second metallization patterns, with the first pattern providing multiple op amps with separate inputs and outputs, and the second pattern interconnecting the amplifiers to form a single op amp. The second pattern also preferably interconnects at least one set of corresponding high impedance nodes to prevent a difference voltage which might otherwise arise between the nodes due to component mismatches between the multiple op amps.

Abstract: A monolithically integrated microwave frequency high power amplifier device comprises a plurality of transistors connected in a load modulation configuration wherein the number of the transistors that is operational depends on the drive level. The transistors have each a finger type layout, where fingers from different ones of the transistors are interleaved. The sources of the plurality of transistors are typically interconnected, whereas the gates of the transistors have separate connections for connection to separate package leads. Similarly, the drains of the transistors have separate connections for connection to separate package leads. Advantageously, an LC-based passive network performs a power combining operation of the amplifier device.

Abstract: A method and apparatus are provided for operating a feedback network (300, 400). The method and apparatus operate to combine (240) a feedback signal (IF) and an incoming signal (VIN) to generate an adjusted signal (IADJ) at an input node of an amplifier element (110); amplifying the amplifier input signal in the amplifier element to produce an amplifier output signal (VOUT) at an output node of the amplifier element; processing the amplifier output signal according to a feedback operation (230) to generate the feedback signal (IF); and providing an assist current (350, 450, IASSIST) to the output node of the amplifier element, separate from an output current provided by the amplifier element.

Abstract: An integrated power amplifier (PA) module formed on a substrate includes a first cluster of transistor cells positioned in a first portion of the substrate; a second cluster of transistor cells positioned in a second portion of the substrate and spaced apart from the first portion; and a combiner coupled to the first and second clusters to combine the output of the first and second clusters.

Abstract: Circuits and methods are provided for building integrated transformer-coupled amplifiers with on-chip transformers that are designed to resonate or otherwise tune parasitic capacitances to achieve frequency tuning of amplifiers at millimeter wave operating frequencies.

Abstract: An apparatus and method for transmitting signal, the apparatus comprising a front end telecommunications module including a power amplifier, a matching circuit coupled to the power amplifier, and a filter coupled to the matching circuit, such that a signal received by the power amplifier is transmitted to the filter through the matching circuit. The telecommunications module provides quad-band capability in a compact design.

Abstract: An input impedance matching circuit for a low noise amplifier includes a source pad, a gate pad, an input transistor, a source degeneration inductor and a matching capacitor. The gate pad receives an input signal and the input transistor amplifies the input signal transmitted from the gate pad. The source degeneration inductor electrically coupled to an external ground voltage is adapted for input impedance matching of the low noise amplifier. The source pad is coupled to a source electrode of the input transistor and the matching capacitor is formed between the gate pad and the source pad extending the source pad to be disposed under the gate pad. Accordingly, impedance matching of the low noise amplifier may be facilitated and the gain and noise figure of the low noise amplifier may be improved.

Abstract: A power amplifier integrated into an RF-IC (integrated circuit carrying radio frequency signals) comprises an active stage (350) and a passive stage (360), the passive stage being electrically coupled between the active stage and a load of the power amplifier. Electrically conductive elements (305) accomplishing an electrical connection between the active part and the passive part of an RF-IC are designed in a way that the electrically conductive elements perform at least part of impedance transformation on a signal path from signal output terminals of the active stage to signal output terminals of the passive stage.

Abstract: The transistor circuit 1 includes a plurality of transistor cells 10 each having a transistor 11, a base ballast resistor 12, a capacitor 13, and an inductor 14. The transistors 11 have the respective collectors commonly connected to a collector terminal 1c of the transistor circuit 1 and the respective emitters commonly connected to an emitter terminal 1e thereof. Each base ballast resistor 12 is connected to bases of the transistor 11 at one end and to a base terminal 1b of the transistor circuit 1 at the other end. The capacitor 13 is serially connected to the inductor 14, thus to form a serial resonant circuit 15, which is connected in parallel with the base ballast resistor 12 and provided between the bases of the transistor 11 and the base terminal 1b of the transistor circuit 1 and connected thereto.

Abstract: An embodiment of the present invention includes an amplifier on an integrated circuit, with the amplifier having positive and negative inputs, and positive and negative outputs. A first feedback capacitor is on the integrated circuit between the positive input and the negative output. A second feedback capacitor is on the integrated circuit between the negative input and the positive output. A package encloses the integrated circuit. A third capacitor is between the positive and negative inputs. A feedback factor of the amplifier circuit approaches unity. In example embodiments, the first and second capacitors are between 3 and 10 pF. The third capacitor is between 3 and 10 pF.

Abstract: In one embodiment, an output transistor and a bias compensation device are placed in proximity to each other on the same package substrate. The bias compensation device is electrically isolated but thermally coupled to the output transistor, and is configured to provide a output signal for adjusting bias to the output transistor.

Abstract: An integrated circuit includes a resistive circuit with reduced mismatch that includes a primary resistive network with several main resistances (Rp) each having the same theoretical main value. It also includes an auxiliary resistance (Rau) having an auxiliary theoretical resistive value equal to the product or to the quotient of the theoretical main resistive value by ?{square root over (2)}. All these resistances are connected together so as to attribute a theoretical overall resistive value to the primary resistive network equal to the theoretical auxiliary resistive value.

Abstract: A transistor integrated circuit apparatus generating less noise, having superb RF characteristics, and preventing thermal runaway of transistors is provided. Owing to capacitors C11 through C1n having one end commonly connected to an RF signal input terminal RFin and the other end connected to a base electrode of a corresponding transistor, and inductors L11 through L1n having one end commonly connected to a DC power supply input terminal DCin and the other end connected to a base electrode of a corresponding transistor, RF noise generated in a DC power supply circuit is reduced. This can reduce the RF noise output from the transistors Tr11 through Tr1n. The inductors L11 through L1n prevent an RF signal input from the RF input terminal RFin from flowing toward the DC power supply circuit. This can prevent the RF signal from being lost by the flow thereof toward the DC power supply circuit.

Abstract: Disclosed herein is a layout structure of a signal driver. The layout structure of the signal driver of the present invention includes a first signal response unit, a second signal response unit, and a current source unit. The first signal response unit responds to a first input signal, and the second signal response unit responds to a second input signal. The current source unit has a plurality of bias unit pairs for restricting currents provided to the first and second signal response units to respective source currents thereof. The bias unit pairs each include at least two bias units, which are separately arranged on opposite sides of a predetermined imaginary centerline. According to the layout structure of the signal driver of the present invention, there is a benefit in that current mismatch occurring between the first and second current response units is reduced, thus consequently improving the operating characteristics of the signal driver.

Abstract: A DC offset calibration device for calibrating a DC offset of an output signal of a gain stage, the DC offset calibration device includes: a digital-to-analog converter (DAC) electrically connected to the gain stage for generating an offset current according to the DC offset of the output signal of the gain stage; and a current-to-current converter electrically connected to the DAC and the gain stage for reducing the signal scale of the offset current to generate a compensation signal so as to reduce the DC offset at the output of the gain stage.

Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals.

Abstract: A power amplifier arrangement comprises a power amplifier in a semiconductor body. At least one first input terminal on the surface of the semiconductor body is provided for feeding in a signal to be amplified. A first output tap of the arrangement is designed for outputting a signal with a first center frequency; a second and a third output tap are designed for outputting a second signal with a second center frequency. A line wire is respectively connected to the second and third output taps on the surface of the semiconductor body. According to the invention, a charge store is provided, which is coupled to the third output tap and is designed for forming a series resonant circuit with the line wire connected to the third output tap.

Abstract: An amplifier module has a substrate, as assembly having one or more integrated circuit (IC) dies mounted to the substrate, and one or more other electronic components mounted to the substrate. The assembly receives an input signal and generates an amplified output signal. The one or more other electronic components perform one or more amplifier-related functions. The amplifier module is adapted to be mounted to a circuit board (CB) as a distinct electronic package. The invention may be implemented as an electronic system having the CB and at least one such amplifier module mounted to the CB.

Abstract: A method and apparatus provides techniques for electrically isolating switching devices in a stacked RF power amplifier, which prevents the switching devices from being subjected to high breakdown voltages. The isolation provided allows the power amplifier to be implemented on an integrated circuit.

Abstract: A low noise amplifier (LNA), which utilizes an AC coupling technique that can internally bias diodes in such a way as to provide effective low noise amplification, is provided. The low noise amplifier includes an input to an amplifier circuit, and an AC coupling capacitor disposed externally to a chip boundary of the amplifier circuit.

Abstract: In a driver circuit including transistors each having an emitter follower configuration and a pair of differential transistors with emitter outputs of the transistors of the emitter follower configuration as inputs, end terminals of the pair of differential transistors are connected to individual bonding pads, and the respective bonding pads and voltage sources are individually connected by wires that function as inductors. Thereby, even in the case where the lengths of the wires of output terminals change according to packaging, outputs can be matched by determining the wire lengths of the wires suitably.

Abstract: An amplifier circuit includes a first multiple gate field-effect transistor having a source terminal, a drain terminal, at least one signal gate terminal for receiving an input signal and at least one control gate terminal for receiving a control signal, and a second multiple gate field-effect transistor having a source terminal, a drain terminal, at least one signal gate terminal connected to the signal gate terminal of the first multiple gate field-effect transistor, and a control gate terminal connected to the control gate terminal of the first multiple gate field-effect transistor, the signal gate terminal of the second multiple gate field-effect transistor being connected to that source terminal/drain terminal of the second multiple gate field-effect transistor which is closer to the signal gate terminal of the second multiple gate field-effect transistor.

Abstract: Cross-band isolation characteristics are to be significantly improved without using any filtering circuit. In the central part of a semiconductor chip provided in an RF power module is formed a ground wiring layer from the upper part downward. This ground wiring layer is formed on the boundary between GSM side transistors and DCS side transistors for amplifying different frequency bands. Over the ground wiring layer are formed chip electrodes at equal intervals, and any one of the chip electrodes is connected via a bonding wire to a bonding electrode. The bonding electrode is formed over a module wiring board over which the semiconductor chip is to be mounted, and the ground wiring layer is connected to it. Harmonic signals are trapped by the ground wiring layer and the bonding wire.

Abstract: A high frequency amplifier includes a constant voltage driven amplifier 1 using as its amplifying element a bipolar transistor 7 with its base biased by a constant voltage, and a constant current driven amplifier 2 using as its amplifying element a bipolar transistor 8 with its base biased by a constant current. The idle current of the constant current driven amplifier 2 is set at a low value. In accordance with the idle current, the idle current of the constant voltage driven amplifier 1 is adjusted, and the two amplifiers are combined in parallel.

Abstract: A power amplifier module for amplifying radio frequency signals includes first, second, third and fourth corner ground pads positioned at each corner of the power amplifier module; one or more radio frequency input pads positioned between the first and second corner ground pads; one or more radio frequency output pads positioned between the third and fourth corner ground pads; and one or more power amplifier circuits centrally positioned on the power amplifier module.

Abstract: An apparatus and method for transmitting signal, the apparatus comprising a front end telecommunications module including a power amplifier, a matching circuit coupled to the power amplifier, and a filter coupled to the matching circuit, such that a signal received by the power amplifier is transmitted to the filter through the matching circuit. The telecommunications module provides quad-band capability in a compact design.

Abstract: A general purpose Darlington pair amplifier circuit, configured in accordance with a preferred embodiment of the invention, utilizes GaAs heterojunction bipolar transistor technology. The amplifier circuit incorporates a temperature compensation circuit at the input stage that controls the total current drawn by the transistors such that the total current is stable over temperature. The temperature compensation circuit includes a feedback resistance element and a bias resistance element that form a voltage divider that establishes the base voltage (bias voltage) of an input transistor. The feedback resistance element and the bias resistance element are of different types, having different positive temperature coefficients. In the example embodiment, the temperature coefficient of the feedback resistance element is greater than the temperature coefficient of the bias resistance element.

Abstract: A selectable gain amplifier in a standard integrated circuit package configuration comprises an amplifier having an analog input, an output and a control input for selecting one of two or three possible gains for the operational amplifier. A plurality of selectable gain amplifiers may be in a standard integrated circuit package configuration, each having a gain control input for selection of the two or three possible gains. The gain control input replaces an inverting input of a standard operational amplifier and the analog input is the a non-inverting input of the operational amplifier or visa-versa. All other characteristics of the selectable gain amplifier may be the same or similar to a standard operational amplifier. The selectable gain amplifier(s) may be packaged in industry standard integrated circuit packages having standard pin-outs so that they may be compatible as replacement analog amplifiers for existing technology operational amplifier integrated circuit packages.

Abstract: A multi-stage amplifier circuit arranged to take advantage of the desirable characteristics of non-field-plate and field plate transistors when amplifying a signal. One embodiment of a multi-stage amplifier according to the present invention comprises a non-field-plate transistor and a field-plate transistor. The field-plate transistor has at least one field plate arranged to reduce the electric field strength within the field plate transistor during operation. The non-field plate transistor is connected to the field plate transistor, with the non-field-plate providing current gain and the field plate transistor providing voltage gain. In one embodiment the non-field-plate and field plate transistors are coupled together in a cascode arrangement.

Abstract: The output of a differential amplifier circuit group (PA) that amplifies signals inputted to input PINs is connected to a final-stage differential amplifier circuit (PAn). The output of the differential amplifier circuit (PAn) is connected to a detection (DET) circuit. A detect signal sent from the DET circuit is outputted to the (?) side input of a comparator. A bias signal (BP) outputted from a bias circuit is inputted to the base of a PMOS transistor of a source follower circuit. An output signal (SFOUT) outputted from a source terminal thereof is inputted to the (+) side input of the comparator. A result of comparison between the bias signal (BP) and the output signal (SFOUT) is outputted from the comparator as an output signal (COMPOUT).

Abstract: Power amplifier circuits which constitute an RF power module used for a digital device capable of handling high frequency signals in two frequency bands are disposed over the same IC chip. The power amplifier circuits are disposed around the IC chip, and a secondary circuit is disposed between the power amplifier circuits. Thus, the power amplifier circuits are provided within the same IC chip to enable a size reduction. Further, the distance between the power amplifier circuits is ensured even if the power amplifier circuits are provided within the same IC chip. It is therefore possible to suppress the coupling between the power amplifier circuits and restrain crosstalk between the power amplifier circuits.

Abstract: RF phase distortion circuits and methods for controllably phase distorting an RF signal based on amplitude of the RF signal. An MOS device is provided having a body of a first conductivity type and at least one region of a second conductivity type in the body, with a conductive layer over at least part of the body and the region of the second conductivity type and insulated therefrom. The MOS device may be coupled into a phase distortion circuit individually or in back-to-back pairs and biased to invert the body under the conductive layer for small signal amplitudes and not for large signal amplitudes, or to not invert the body under the conductive layer for small signal amplitudes and to invert the body under the conductive layer for large signal amplitudes. Various embodiments are disclosed.

Abstract: The invention concerns an integrated circuit amplifier designed to supply an amplified signal at a power of a few hundreds of milliwatts at frequencies from one to several Gigahertz.

Abstract: A ground layer is provided between a first and a second wiring layer. A first transistor provided at the first wiring layer amplifies a supplied high-frequency signal. A second transistor provided at the first wiring layer amplifies the output signal of the first transistor. A first power supply line, which supplies power to the first transistor, is provided at the first wiring layer. A second power supply line, which supplies power to the second transistor, is provided at the second wiring layer.

Abstract: Apparatus and methods are described for biasing amplifiers with multiple outputs. A semiconductor die may include a reference Field Effect Transistor (FET) integrated on the semiconductor die and coupled to an amplifier integrated on the semiconductor die. A voltage offset circuit may also be integrated on the semiconductor die for determining the voltage needed to operate the amplifier.

Abstract: A method and apparatus provides techniques for electrically isolating switching devices in a stacked RF power amplifier, which prevents the switching devices from being subjected to high breakdown voltages. The isolation provided allows the power amplifier to be implemented on an integrated circuit.

Abstract: In a high-frequency power amplifier, gate feed portions are formed by dividing a gate feed which connects transistor gate electrodes in parallel, and each of the gate feed portions includes a given number of gate electrodes connected in parallel. Each of transistor cell elements includes a set of the gate electrodes connected in parallel. A resistance wire is interposed between the transistor cell elements to isolate each transistor cell element. The resistance wire and the gate electrodes are made of the same metal material and formed by the same process. Thus, closed loop oscillation of transistors is suppressed with no increase in chip size.

Abstract: A power amplifier matching circuit is provided. The matching circuit includes a ferro-electric tunable component. A control signal is applied to the tunable component, changing the component's impedance. This changes the impedance of the matching circuit.

Abstract: The invention is directed to a system for electromagnetic communications that includes a semiconductor die; at least one amplifier on the die to amplify an input signal and generate an output signal; and an active bias control component on the die for adjusting biasing of the amplifier so that the amplifier is operable in a plurality of frequency bands. In one embodiment, a PCS band and W-CDMA power amplifier may be integrated on the same power amplifier die, and different output power requirements may be addressed by the use of an Si DC-DC converter. Such a converter may provide efficiency enhancements to the overall system through the use of dynamic bias control under active power control situations from the network. In addition, the converter may be used in a voltage up-converter state that allows a W-CDMA optimized power amplifier to operate at PCS frequencies and output power levels.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically.

Abstract: A method and circuit is provided for improving the control of the trimming procedure for various devices without the need for additional dedicated control pins. Instead, the trimming procedure is controlled through sensing of changes in current and/or voltage applied through the existing available pins or bondpads of the devices to determine whether a command for trim programming has occurred. As a result, package-level trimming of the devices can be conducted in standard device packages having low pin count configurations, such as operational amplifiers, instrumentation amplifiers, difference amplifiers, low drop-out regulators, voltage references and other similar types of devices. A device to be trimmed is configured with internal circuitry configured to sense changes in current and/or voltage in the output or supply voltage of the device, and a test system for applying changes in the current and/or voltage through the existing available pins or bondpads of the devices.

Abstract: A first circuit which is constituted by a thin film resistor is connected between the collector of a transistor and a power supply terminal, and a second circuit which is constituted by a semiconductor resistor is connected between the emitter of the transistor and a grounding terminal. The film thickness of a thin film resistor is set to not more than its skin depth at a frequency to be compensated for.

Abstract: Briefly, DC offset cancellation techniques that utilize one of multiple sources of a DC offset cancellation signal. The DC offset cancellation techniques may be used by a limiting amplifier.

Abstract: The amplifier includes two or more amplification stages. The rear amplification stage amplifies an output signal of a front stage transistor is comprised of two or more transistors connected in parallel. Bias point of the front stage transistor and a first rear stage transistor is class AB. Base bias of a second rear stage transistor is controlled according to an RF input by a rear stage DC bias control circuit. As a result, the second rear stage transistor is turned on when the output power is high, whereas it is turned off when the output power is low or medium.

Abstract: Synthetic circuit elements and amplifier applications for synthetic circuit elements are provided. The synthetic circuit elements disclosed herein may be configured to compensate for some or all of the parasitic capacitance normally associated with circuit elements disposed on a substrate providing a selectable impedance characteristic. Amplifier circuit constructed using such synthetic circuit elements exhibit improved performance characteristics such as improved recovery time, frequency response, and time domain response.