Abstract: A power amplifier with stacked, serially connected, field effect transistors is described. DC control voltage inputs are fed to the gates of each transistor. Capacitors are coupled to the transistors. The inputs and the capacitors are controlled to minimize generation of non-linearities of each field effect transistor and/or to maximize cancellation of distortions between the field effect transistors of the power amplifier in order to improve linearity of the power amplifier output.

Abstract: An amplifier (210) includes an input stage (310, 320) and an output stage (330). The input stage (310, 320) has an input for receiving an input signal, and an output. The output stage (330) has an input coupled to the output of the input stage (310, 320), and an output for providing an amplified output signal. The output stage (330) includes a gain stage and a bias circuit. The gain stage has an input forming the input of the output stage, an output for providing the amplified output signal, and a first bias terminal. The bias circuit has a first output terminal coupled to the first bias terminal of the gain stage. During a turn-on period the bias circuit gradually ramps the first bias terminal from a first initial voltage to a first bias voltage.

Abstract: Apparatus are provided for amplifier circuits and related receiver systems. An amplifier circuit includes a first common-source amplification stage and a second common-source amplification stage. The input of the second common-source amplification stage is coupled to the output of the first common-source amplification stage such that the first common-source amplification stage generates a first amplified signal, and the second common-source amplification stage generates a second amplified signal based on the first amplified signal. The first common-source amplification stage is coupled to a first node and the second common-source amplification stage is coupled to a second node, wherein the common-source amplification stages are configured such that a current between the first node and the second node flows in series through the common-source amplification stages.

Abstract: A power amplifier includes a first amplifier unit, a second amplifier unit, and an attenuator. The second amplifier receives a signal from the first amplifier unit and amplifies the signal. The attenuator is provided between the first and second amplifier units. The attenuator has arms, including at least one parallel arm and at least one series arm, and has switches connected to the arms to switch the electrical connection states of the arms with respect to the first and second amplifier units. The at least one parallel arm and the at least one series arm are alternately arranged, in the order named, as viewed in the direction from the first amplifier unit to the second amplifier unit.

Abstract: A method of sharing inductors for inductive peaking of an amplifier having at least two stages includes calculating a single stage inductance of a single stage of the at least two stages for inductive peaking in order to have a stable impulse response. A shared inductance is calculated for inductive peaking by dividing the single stage inductance by a number of stages of the at least two stages. At least two inductors having the shared inductance are shared among the at least two stages for inductive peaking.

Abstract: A power amplifier is provided, which includes a power dividing unit, a first power amplification tributary, a second power amplification tributary, and an impedance conversion unit. Input ends of the first power amplification tributary and the second power amplification tributary are coupled to two output ends of the power dividing unit respectively. An output end of the first power amplification tributary is coupled to an output end of the second power amplification tributary through the impedance conversion unit. Rated power of a peak power amplifier in the second power amplification tributary is greater than that of a main power amplifier in the first power amplification tributary. The beneficial effects of the present invention lie in that larger back-off exists at the peak of an efficiency curve of the power amplifier, and in the case that power is back-off, efficiency of the power amplifier is improved.

Abstract: An amplifier device includes an initial amplifier stage configured to receive a differential input signal at a first leg and a second leg; a final amplifier stage coupled to outputs of the initial amplifier stage, the final amplifier stage including a primary signal amplifier and an error amplifier in each of the first and second legs; and wherein an output of the error amplifier of the first leg is combined with an output of the primary signal amplifier in the second leg, and an output of the error amplifier of the second leg is combined with an output of the primary signal amplifier in the first leg.

Abstract: A system includes a power amplifier, a preamplifier, a first temperature sensor, and a bias generator. The power amplifier has a first gain, which is a function of a temperature of the power amplifier. The preamplifier has a second gain, amplifies an input signal, and outputs an amplified signal to the power amplifier. The first temperature sensor senses the temperature and generates a first signal. The bias generator generates a first biasing signal to bias the power amplifier, generates a second biasing signal to bias the preamplifier, and adjusts the second gain by adjusting the second biasing signal based on the first signal. The adjusted second gain compensates a change in the first gain due to the change in the temperature.

Abstract: There is provided an amplifier circuit including: a first transistor having a source thereof connected to an input port and having a gate thereof grounded; a second transistor having a gate thereof grounded; a first inductor provided between a drain of the first transistor and a source of the second transistor; and a second inductor provided between a drain of the second transistor and an output port.

Abstract: An operational amplifying device comprises an input stage and an output stage. The input stage receives and processes an input voltage to output an amplified voltage. The output stage is electrically connected to the input stage in series. The output stage comprises a first switch and a second switch. The first switch is configured to turn on for transferring the amplified voltage. The second switch is connected in parallel with the first switch and is configured to turn on for transferring the amplified voltage. The second switch is turned off when the first switch is turned on such that the amplified voltage is transferred through the first switch to the first resistor array for gamma correction.

Abstract: A low-noise amplifier (“LNA”) includes a first cascode gain stage including a first complementary metal oxide semiconductor (“CMOS”) transistor configured to receive a radio frequency (“RF”) input signal and a second CMOS transistor coupled to an output node. The first inductive gate network is coupled to a gate of the second CMOS transistor for increasing a gain of the first cascode gain stage. The first inductive gate network has a non-zero inductive input impedance and includes at least one passive circuit element.

Abstract: The invention is an improvement in microwave and millimeter wave amplifiers. Capacitors are connected in parallel with the source and drain terminals of all of the amplifying elements in a series of such elements except the first, compensating for current leakage due to gate capacitance. This results in improved synchronism of the amplifying elements, and improved overall efficiency and circuit performance.

Abstract: An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.

Abstract: An electronic circuit includes: a first transistor having a control terminal, a first terminal, and a second terminal; a second transistor having a control terminal connected to the second terminal of the first transistor, a first terminal, and a second terminal connected to a DC power supply; a plurality of DC paths that are mutually independent of each other and supply DC currents from the first terminal of the second transistor to the second terminal of the first transistor; and distributed constant lines connected in series with the plurality of DC paths.

Abstract: Techniques to improve low noise amplifiers (LNAs) with noise canceling are described. LNA includes a first and a second amplifier which work together to noise cancel the noise generated at an input stage circuit. The input stage circuit receives an RF signal and is characterized by a first node and a second node. The first amplifier converts a noise voltage at the first node into a first noise current at an output of the first amplifier. The second amplifier is directly coupled to the output of the first amplifier and provides noise canceling by summing the first noise current with a second noise current generated by the second amplifier as a function of the noise voltage at the second node. The proposed techniques eliminate the need for large ac coupling capacitors and reduce the die size occupied by the LNA.

Abstract: Embodiments of RF switching amplifiers are described generally herein. Other embodiments may be described and claimed.

Abstract: A communications device is provided. The communications device includes an antenna port, transmitter circuitry configured to broadcast a radio frequency (RF) output signal across the antenna port, and a controller configured to adjust a signal level of the RF output signal in accordance with antenna compensation information. The antenna port, the transmitter circuitry, and the controller are at least partially integrated on the same integrated circuit.

Abstract: An amplifier includes an amplifier section having selectable signal paths to provide discrete gain settings, and logic to incrementally select the signal paths. The logic may be configured to increment the gain in response to digital gain control signals or an analog gain control signal. Another amplifier has an input section with one or more input cells and an output section with one or more output cells. Either the input section or the output section includes at least two cells that may be selected to provide discrete gain settings. A loop amplifier is configured in a feedback arrangement with the input section. The input and output sections may have multiple selectable cells to provide coarse and fine gain steps. The gain of the loop amplifier may be coordinated with the gain of the input section to provide constant bandwidth operation.

Abstract: A signal processing system and method utilizes a multi-stage amplifier to amplify an input signal. The multi-stage amplifier uses a mixed set of voltage rails to improve the operating efficiency of at least one of the amplification stages while allowing other amplification stages to operate in a predetermined operating mode. Efficiency of at least one of the stages is improved by supplying at least one variable voltage rail to an amplification stage of the multi-stage amplifier. The variable voltage rail varies in response to changes in an input signal voltage to the amplification stage. Accordingly, at least one amplification stage utilizes a variable voltage rail, and all amplification stages are supplied with a set of voltage rails that provides sufficient input signal headroom, thus, providing amplification stage efficiency and adequate voltage to allow operation of all amplification stages.

Abstract: An operational amplifier may include a transimpedance input stage. The operational amplifier is capable of self-biasing its input voltage(s) including a first stage, an input source connected to the first stage, an output stage connected to the first stage via feedback resistors, and feedback current sources connected to the first stage, wherein the feedback current sources are set to generate feedback currents flowing from the output stage back to the input stage via the feedback resistors, so as to self-bias the input voltage(s) at the input stage. A method for allowing for an op-amp to self-bias its input voltage(s), including generating feedback currents flowing from the output stage back to the input stage via feedback resistors, so as to self-bias the input voltage(s) at the input stage.

Abstract: According to one embodiment, a circuit comprises a Capacitive Trans-Impedance Amplifier (CTIA) configured to receive a current pulse at an input and convert the current pulse to a voltage step. The voltage step is directed to a first signal path and a second signal path. When the voltage step exceeds a first threshold, the first signal path directs an enable pulse to the second signal path. The second signal path generates an output pulse when the voltage step exceeds a second threshold and the enable pulse is enabled. The second signal path comprises a first, a second, and a third amplifier to increase detection of the voltage step by the second signal path.

Abstract: In one embodiment, an apparatus includes a first amplification block configured to receive a signal and a second amplification block configured to output the signal. The outputted signal is an amplified version of the signal. A circuit allows reuse of a second current flowing through the second amplification block by coupling the second current to pass through the first amplification block to increase a first current that flows through the first amplification block. Amplification of the signal is based on the increased first current that flows through the first amplification block.

Abstract: Power amplifier circuits which constitute an RF power module used for a digital device capable of handling high frequency signals in two frequency bands are disposed over the same IC chip. The power amplifier circuits are disposed around the IC chip, and a secondary circuit is disposed between the power amplifier circuits. Thus, the power amplifier circuits are provided within the same IC chip to enable a size reduction. Further, the distance between the power amplifier circuits is ensured even if the power amplifier circuits are provided within the same IC chip. It is therefore possible to suppress the coupling between the power amplifier circuits and restrain crosstalk between the power amplifier circuits.

Abstract: The present invention includes a class-E power amplifier, comprising a driver stage (DS) including a first power amplifier with transistors, to which an input signal is inputted; a main stage (MS), including a second power amplifier with transistors, whose input is connected to the output of the DS; and a first LC resonator whose one end is connected to the output of the DS and the other end to the ground as an AC equivalent circuit and a second LC resonator whose one end is connected to the input of the MS and the other end to the ground as an AC equivalent circuit. In accordance with the present invention, as the voltage stress is reduced on the CMOS class-E power amplifier, the application of the high power supply voltage may be allowed and therefore the load impedance may be high while the same efficiency is maintained.

Abstract: Receiver circuits for differential and single-ended signals are disclosed. In some embodiments, a receiver may include a first amplifier configured to receive a first signal of a differential pair of signals at a first input and a second signal of the differential pair of signals at a second input when operating in differential mode. The receiver may also include a second amplifier coupled to the first amplifier, where the second amplifier is configured to receive a reference signal at a third input and a single-ended signal at the first input when operating in single-ended mode. In some embodiments, several receivers may be used, for example, to process a differential clock signal and one or more single-ended data signals referenced to the clock signal and/or differential data signals referenced to a single-ended clock signal. In some embodiments, the delays of each signal propagating through each respective receiver may be independently adjusted.

Abstract: A receiving circuit is provided for performing reception of a plurality of band signals and suppression of blockers that remain in the plurality of band signals being received and converted in frequency. The receiving circuit includes a first low-pass filter that has a first pole position to suppress blockers remaining in a received signal by the first pole position, and a second low-pass filter that has a second pole position to suppress blockers remaining in a signal that has passed through said first low-pass filter by the second pole position. A switch that switches on/off an input-output path including the filters so that the received signal passes through said first filter without passing through the second filter when receiving a first band signal, while the received signal passes through both filters when receiving a second band signal different from the first band signal.

Abstract: A circuit for sharing Tx/Rx ports of a CMOS based time multiplexed transceiver includes a Low Noise Amplifier (LNA) and a Power amplifier (PA), and deploys a single RF choke shared between the LNA and PA. The circuit selectively functions as a PA cascode or a LNA input device. In one form the circuit uses MOS transistors configured for use in one of Blue tooth, WLAN and TDMA applications, taking advantage of source-drain symmetry of the MOS transistors. The circuit may include a DC path and be used in WLAN applications, wherein the sharing of the single choke is enabled by one switch in the DC path. As described, the single RF choke is disposed outside of the LNA and the PA. The circuit supports high out powers and causes reduced signal loss due to just one LC tank as opposed to two LC tanks present in the prior art.

Abstract: A radio frequency (RF) power amplifier includes a low impedance pre-driver driving the input of a common-source output amplifier stage. The preamplifier includes a first transistor that has a first terminal coupled to a preamplifier RF input node, a second terminal coupled to a preamplifier RF output node, and a third terminal coupled to a supply voltage node. A first inductor is coupled between the RF output node and a bias voltage node. A voltage difference between respective first and second voltages on the RF input node and the RF output node that are substantially in phase, determines current through the first transistor.

Abstract: A semiconductor device for transmitting-signal amplification which has a fine resolution, a high dynamic range, a small occupied area, and low power consumption, is realized. An input signal amplitude is reduced every one half by a ladder network, and a transconductance amplifier stage is arranged corresponding to each node of the ladder network. An output of the transconductance amplifier stage is coupled to an output signal line in common. According to a control word WC<21:0>, the transconductance amplifier stage is enabled selectively, and the output current which appears in the output signal line is added.

Abstract: The present disclosure describes a distributed amplifier (DA) that includes active device cells within sections that are configured to provide an input gate termination that is conducive for relatively low noise and high linearity operation. A section adjacent to an output of the DA is configured to effectively terminate the impedance of an input transmission line of the DA. Each active device cell includes transistors coupled in a cascode configuration that thermally distributes a junction temperature among the transistors. In this manner, noise generated by a common source transistor of the cascode configuration is minimized. The transistors coupled in the cascode configuration may be fabricated using gallium nitride (GaN) technology to reduce physical size of the DA and to further reduce noise.

Abstract: An audio amplifier circuit has a first cascode stage configured as a voltage gain stage and having an input for an audio signal, and an output. The circuit has a second cascode stage configured as a unity gain or near unity gain stage and having an input to receive an output from the first cascode stage, and a low impedance output to drive an output stage of an audio power amplifier. The first cascode stage has a first, input transistor having an input biased to a predetermined bias voltage, and a second, output transistor arranged to drive the second cascode stage. The first, input transistor of the first cascode stage may have a common-emitter configuration, and the second, output transistor may have a common-base configuration. The invention extends to an audio amplifier which includes a circuit of the invention.

Abstract: This is disclosed an amplification stage including a first amplifier stage, a second amplifier stage, and a power supply unit, in which the output of the first stage provides the input to the second stage, and the power supply unit provides a power supply for both amplifier stages, wherein the voltage of the power supply is continuously varied in dependence of the amplitude of the signal being amplified.

Abstract: A low-noise amplifier (LNA) includes a first cascode gain stage coupled to an input node for increasing an amplitude of an RF input signal. A first variable gain network is coupled to the first cascode gain stage and includes a first inductor for boosting a gain of the first cascode gain stage, a first capacitor coupled to the first inductor for blocking a direct current (DC) voltage, and a first switch coupled to the first inductor and to the first capacitor. The first switch is configured to selectively couple the first inductor to the first cascode gain stage in response to a first control signal.

Abstract: An amplifier is realized by a distributed-constant-type amplifier including an input-side transmission line and an output-side transmission line, and a plurality of unit circuits coupled between the input-side transmission line and the output-side transmission line, in which each of the plurality of unit circuits is formed by including an amplification circuit having a gain equal to or greater than one.

Abstract: An electronic circuit includes a first transistor having a first terminal grounded, a second transistor having a control terminal coupled with a second terminal of the first transistor, a first terminal grounded via a first capacitor, and a second terminal to which a DC power supply is connected, a first distributed constant line having one end connected to a first node between the second terminal of the first transistor and the control terminal of the second transistor and another end grounded via a second capacitor, a second distributed constant line having one end connected to the second terminal of the first transistor and another end connected to the first node, a third distributed constant line having one end connected to the control terminal of the second transistor and another end connected to the first node, a resistor connected between a second node between the first line and the second capacitor and a third node between the first terminal of the second transistor and the first capacitor, and a path

Abstract: To reduce a knee voltage of a Darlington amplifier, a negative voltage is applied by a depletion mode FET between the emitter of one amplifying transistor and the base of another amplifying transistor to provide a reduced potential, which reduces the knee voltage of the Darlington amplifier. Reducing the knee voltage of the Darlington amplifier decreases the size of a saturation region thereby increasing the linearity of the Darlington amplifier.

Abstract: Techniques to improve low noise amplifiers (LNAs) with noise canceling are described. LNA includes a first and a second amplifier which work together to noise cancel the noise generated at an input stage circuit. The input stage circuit receives an RF signal and is characterized by a first node and a second node. The first amplifier converts a noise voltage at the first node into a first noise current at an output of the first amplifier. The second amplifier is directly coupled to the output of the first amplifier and provides noise canceling by summing the first noise current with a second noise current generated by the second amplifier as a function of the noise voltage at the second node. The proposed techniques eliminate the need for large ac coupling capacitors and reduce the die size occupied by the LNA.

Abstract: A low noise amplifier includes a first Group III-nitride based transistor and a second Group III-nitride based transistor coupled to the first Group III-nitride based transistor. The first Group III-nitride based transistor is configured to provide a first stage of amplification to an input signal, and the second Group III-nitride based transistor is configured to provide a second stage of amplification to the input signal.

Abstract: A communications device is provided. The communications device includes first output stage circuitry configured to generate a first radio frequency (RF) output signal in response to receiving an RF input signal, a first antenna port configured to couple to a first antenna and configured receive the first RF output signal from the first output stage circuitry, second output stage circuitry configured to generate a second RF output signal in response to receiving the first RF output signal, and a second antenna port configured to couple to a second antenna and configured to receive the second RF output signal from the second output stage circuitry. The first output stage circuitry, the first antenna port, the second output stage circuitry, and the second antenna port are at least partially integrated on the same integrated circuit.

Abstract: An amplifier circuit includes a first amplifier stage having a first output node; a second amplifier stage having a second output node; and a compensation block electrically coupled between the first and second output nodes. The compensation block has a compensation capacitor electrically coupled to the first node and electrically connectable to the second node, and has an impedance electrically connectable to the compensation capacitor. The compensation capacitor is electrically coupled via a switch to the impedance such that the compensation capacitor can contribute a zero to shunt branch formed by the compensation capacitor and impedance when the compensation capacitor is disconnected from the second node.

Abstract: The present invention relates generally to an operational amplifier. In one embodiment, the present invention is an operational amplifier including a transimpedance input stage, the transimpedance input stage including a first stage connected to a first resistor and a second resistor, and an output stage connected to the transimpedance input stage.

Abstract: Apparatus are provided for amplifier circuits and related receiver systems. An amplifier circuit includes a first common-source amplification stage and a second common-source amplification stage. The input of the second common-source amplification stage is coupled to the output of the first common-source amplification stage such that the first common-source amplification stage generates a first amplified signal, and the second common-source amplification stage generates a second amplified signal based on the first amplified signal. The first common-source amplification stage is coupled to a first node and the second common-source amplification stage is coupled to a second node, wherein the common-source amplification stages are configured such that a current between the first node and the second node flows in series through the common-source amplification stages.

Abstract: Method and systems related to obstructing a first predefined portion of at least one defined wavelength of light incident upon a first photo-detector array; and detecting the at least one defined wavelength of light with a photo-detector in a second photo-detector array.

Abstract: A power amplifier includes a first transistor and a first inductor disposed between the first transistor and a voltage source. A first node between the first transistor and the first inductor is an output node. The power amplifier further includes a second inductor disposed between the first transistor and ground The power amplifier further includes a third inductor coupled to a gate of the first transistor and configured as a first AC input. The power amplifier further includes a first phase conditioner inductively coupled to the second inductor and the third inductor and configured to set phases of AC signals across the first inductor and the second inductor in phase. The second inductor is configured to release energy into the first inductor to raise a voltage of the AC signal and raise a power output at the output node.

Abstract: There is provided an amplifier circuit, comprising: an input, for receiving an input signal to be amplified; a power amplifier, for amplifying the input signal; a switched power supply, having a switching frequency, for providing at least one supply voltage to the power amplifier; and a dither block, for dithering the switching frequency of the switched power supply. The dither block is controlled based on the input signal. Another aspect of the invention involves using first and second switches, each having different capacitances and resistances, and using the first or second switch depending on the input signal or volume signal. Another aspect of the invention involves controlling a bias signal provided to one or more components in the signal path based on the input signal or volume signal.

Abstract: The disclosure relates to an electronic differential amplification device integrated on a semiconductor chip. The device may include first and second transistors having respective source terminals connected to a first potential, and drain terminals to receive a first differential current signal. The device may include third and fourth transistors having respective source terminals connected to the first potential, and drain terminals to provide a second differential current signal to a load obtained by amplifying the first signal. The third and fourth transistors may have a respective gate terminal connected to the drain terminal of the first and the second transistors, respectively, in order to form current mirrors with the latter.

Abstract: The RF power amplifier circuit including multiple amplification stages has a previous-stage amplifier, a next-stage amplifier and a controller. The previous-stage amplifier responds to an RF transmission input signal. The next-stage amplifier responds to an amplification signal output by the previous-stage amplifier. In response to an output-power-control voltage, the controller controls the former- and next-stage amplifiers in quiescent current and gain. In response to the output-power-control voltage, the quiescent current and gain of the previous-stage amplifier are continuously changed according to a first continuous function, whereas those of the next-stage amplifier are continuously changed according to a second continuous function. The second continuous function is higher than the first continuous function by at least one in degree. The RF power amplifier circuit brings about the effect that the drop of the power added efficiency in low and middle power modes is relieved.

Abstract: Disclosed is a radio frequency (RF) communication circuit having an input for receiving an RF signal and providing independently gain controlled signal paths from the input. In a first signal path, the signal is amplified by a constant gain. In a second signal path, the signal is amplified by a constant gain and by a variable gain amplifier.

Abstract: Disclosed is a high-frequency signal processing device capable of reducing transmission power variation and harmonic distortion. For example, the high-frequency signal processing device includes a pre-driver circuit, which operates within a saturation region, and a final stage driver circuit, which operates within a linear region and performs a linear amplification operation by using an inductor having a high Q-value. The pre-driver circuit suppresses the amplitude level variation of a signal directly modulated, for instance, by a voltage-controlled oscillator circuit. Harmonic distortion components (2HD and 3HD), which may be generated by the pre-driver circuit, are reduced, for instance, by the inductor of the final stage driver circuit.

Abstract: In one embodiment, the present disclosure includes an amplifier comprising first and second output stages. The first output stage receives first power supply voltages and the second output stage receives second power supply voltages greater than the first power supply voltages. A switching stage configures the output stages to provide a first current to an amplifier output node from the first output stage when a magnitude of a voltage on the output node is below a first value, provide a second current to the output node from the second output stage when the magnitude of the voltage on the output node is above a second value greater than the first value, and provide a third current to the output node from both the first output stage and the second output stage when the magnitude of the voltage on the output node is between the first value and the second value.