Sum And Difference Amplifiers Patents (Class 330/69)
  • Patent number: 8729961
    Abstract: A voltage output device capable of preventing an increase in circuit scale includes an offset compensation function and is suitably applicable to a drive circuit for display devices. The voltage output device includes an operational amplifier having an inverting input terminal and a non-inverting input terminal. Resistance values of a load resistor on the inverting input side and a load resistor on the non-inverting input side are maintained when the output voltage of the amplifier has changed while sequentially varying either one or both of the resistance values of the load resistor on the inverting input side and the load resistor on the non-inverting input side in a state that the inverting input terminal and the non-inverting input terminal are connected. The voltage output device is configured to output the output voltage of the amplifier with the inverting input terminal not connected to the non-inverting input terminal.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: May 20, 2014
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroyoshi Ichikura
  • Publication number: 20140132341
    Abstract: A multi-mode OPAMP-based circuit is provided. An input amplifying stage amplifies a pair of input differential signals to provide a pair of intermediate differential signals. An output amplifying stage amplifies the pair of intermediate differential signals to provide a pair of output differential signals. A first capacitor is disposed in a first negative feedback loop of the output amplifying stage. A second capacitor is disposed in a second negative feedback loop of the output amplifying stage. A third capacitor is selectively disposed in a first positive feedback loop of the output amplifying stage or coupled to the first capacitor in parallel according to a control signal. A fourth capacitor is selectively disposed in a second positive feedback loop of the output amplifying stage or coupled to the second capacitor in parallel according to the control signal.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 15, 2014
    Applicant: MediaTek Inc.
    Inventors: Chi Yun WANG, Chih-Hong LOU
  • Publication number: 20140126622
    Abstract: In one embodiment, a method includes applying, by a transimpedance amplifier at a receiving end of a communication link, equalization to a signal carried by the communication link at the receiving end of the communication link.
    Type: Application
    Filed: November 6, 2012
    Publication date: May 8, 2014
    Applicant: Fujitsu Limited
    Inventors: Scott McLeod, Nikola Nedovic
  • Patent number: 8717097
    Abstract: An amplifier with improved noise reduction is disclosed. In one implementation, an amplifier is provided that includes a main output stage configured to output an amplified signal at a main output terminal, a secondary output stage configured to output a copy of the amplified signal at a secondary output terminal, and a signal coupler configured to provide a variable resistance coupling between the secondary output terminal and the main output terminal to reduce noise at the main output terminal.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: May 6, 2014
    Assignee: QUALCOMM Incorporated
    Inventor: Vijayakumar Dhanasekaran
  • Patent number: 8704596
    Abstract: An amplifier arrangement constituted of: a first input lead; a second input lead; a difference amplifier; a first buffer, the input of the first buffer coupled to the first input lead, the output of the first buffer coupled to a first input of the difference amplifier; a second buffer, the input of the second buffer coupled to the second input lead, the output of the second buffer coupled to a second input of the difference amplifier; and a transconductance amplifier, the non-inverting input and the non-inverted output of the transconductance amplifier coupled to the first input of the difference amplifier, the inverting input and the inverted output of the transconductance amplifier coupled to the second input of the difference amplifier. The input signals are thus buffered and the offset of the buffers are compensated for.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: April 22, 2014
    Assignee: Microsemi Corporation
    Inventors: Kai Kwan, Peter Kim
  • Patent number: 8693679
    Abstract: A communications system includes a communications device having a plurality of access modules each having a port and connected to a communications line and a plurality of transmitters with the respective transmitter associated in one-to-one correspondence with the communications line of an access module. Each transmitter has a line driver and is configured to couple communications signals to a respective communications line. A voltage source is connected to the line drivers and configured to provide a bias voltage to the line drivers that varies depending on a selected minimum power level. A controller is connected to the voltage source and has logic configured to change the bias voltage to the line drivers. The controller is responsive to a minimum data rate for each bias voltage.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: April 8, 2014
    Assignee: Adtran, Inc.
    Inventor: Brian Christian Smith
  • Publication number: 20140084999
    Abstract: Apparatus and methods reduce increase the common mode range of a difference amplifier. A circuit uses one or more floating powers and one or more floating grounds coupled to an input stage of an amplifier to increase the common mode range of a difference amplifier. The floating power can be configured to select from the greater of the voltage level of one of the differential signals and the system power high source. The floating ground can be configured to select from the lesser of the voltage level of one of the differential signals and the system power low source.
    Type: Application
    Filed: September 25, 2012
    Publication date: March 27, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventor: Quan Wan
  • Publication number: 20140079246
    Abstract: Systems and methods are disclosed to provide automatic power control for a driver circuit. Embodiments disclosed herein enable a driver circuit to automatically decrease the gain of amplified input signals when output power exceeds a threshold. Further, embodiments disclosed herein enable a driver circuit to automatically increase the gain of amplified input signals when battery supply voltage drops to avoid unwanted output signal distortion. By using reference signals for battery power and amplified signal input, the amplifiers of the driver circuit can be automatically adjusted until an equilibrium is reached.
    Type: Application
    Filed: September 18, 2012
    Publication date: March 20, 2014
    Applicant: Broadcom Corporation
    Inventors: Minsheng Wang, Iuri Mehr, Jungwoo Song, Vinay Chandrasekhar
  • Patent number: 8669810
    Abstract: When a time difference is amplified by a time difference amplifier, slew rates of internal output voltages are changed according to a phase combination of digital input signals so that a time gain is determined by a ratio between the slew rates and the slew rates can be controlled from an outside. After a voltage is charged to the level of a power supply voltage in first and second charging capacitors, the charged voltage of the first charging capacitor is decreased with a first slew rate when a first digital input signal transitions, and both charged voltages of the first and second charging capacitors are decreased with a second slew rate when a second digital input signal transitions so that both first and second digital input signals are changed from initial phases, while being compared with a reference voltage to generate first and second digital output signals.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: March 11, 2014
    Assignee: Postech Academy-Industry Foundation
    Inventors: Hye Jung Kwon, Hong June Park
  • Publication number: 20140035670
    Abstract: A FET pair based physically unclonable function (PUF) circuit with a constant common mode voltage and methods of use are disclosed. The circuit includes a first n-type field effect transistor (NFET) and a second NFET. The circuit also includes a first load resistor coupled to the first NFET by a first p-type field effect transistor (PFET) and a second load resistor coupled to the second NFET by a second PFET. The circuit further comprises a closed loop, wherein the closed loop creates a constant common mode voltage.
    Type: Application
    Filed: August 3, 2012
    Publication date: February 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Howard H. Chi, Haitao O. Dai, Kai D. Feng, Donald J. Papae
  • Patent number: 8643434
    Abstract: An adjustable gain audio power amplifying circuit includes an input unit, an audio amplifying unit connected to the input unit, a gain adjusting unit connected to the audio amplifying unit, a controlling unit connected to the gain adjusting unit, a comparing unit connected between the gain adjusting unit and the controlling unit and an output unit connected to the audio amplifying unit. The comparing unit compares an outputted signal of the output unit with a common-mode reference voltage, outputs a gain adjustment controlling signal and sends the gain adjustment controlling signal into the controlling unit. When the outputted signal equals the common-mode reference voltage, the gain adjustment controlling signal turns over and then the controlling unit detects the turnover and sends a received gain adjustment signal into the gain adjusting unit. Based on the received gain adjustment signal, the gain adjusting unit controls gains of the adjustable gain audio power amplifying circuit.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: February 4, 2014
    Assignee: IPGoal Microelectronics (Sichuan) Co., Ltd.
    Inventor: Guojun Zhu
  • Patent number: 8638165
    Abstract: A switched-capacitor DC blocking amplifier is disclosed. In an embodiment, an integrated circuit is provided that includes an amplifier having an amplifier input and an amplifier output, a capacitor connected to the amplifier input and configured to receive an input signal, and a switched capacitor circuit coupled to provide a resistance between the amplifier input and the amplifier output. In one implementation, the switched capacitor circuit is configured with a feed forward circuit to reduce aliasing. In another implementation, the switched capacitor circuit includes a switched impedance circuit to reduce noise.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: January 28, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Peter J Shah, Shahin Mehdizad Taleie, Gerrit Groenewold, Guoqing Miao, Eunyung Sung
  • Patent number: 8633765
    Abstract: This application describes a system for minimizing the common mode voltage drift at the input of a fully differential amplifier. An impedance component is coupled to the inputs and outputs of the differential amplifier. The impedance component optimizes the common mode resistance or impedance to ground without significantly affecting the differential impedance, matches the input common mode voltage to the output common mode voltage and reduces the input common mode voltage drift in presence of leakage currents.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: January 21, 2014
    Assignee: Infineon Technologies AG
    Inventors: Andrea Fant, Luca Sant, Patrick Vernei Torta
  • Publication number: 20140009223
    Abstract: A bias voltage source for a differential circuit has low output impedance at DC, but considerably higher output impedance within the frequency band of the differential signal being processed, to provide an accurate, well-matched common-mode bias voltage to each component of a differential signal path, while providing a low noise current, minimizing the conversion between common-mode and differential modes, and preserving available headroom, and all without requiring the use of large resistors.
    Type: Application
    Filed: July 6, 2012
    Publication date: January 9, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventor: Daniel Rey-Losada
  • Patent number: 8618877
    Abstract: In various embodiments, a pilot signal generation circuit is provided having an operational amplifier buffer connected via a first resistor to receive a source reference voltage. A differential amplifier is connected at a first input to receive the source reference voltage and at a second input to an output of the operational amplifier buffer. A first shunt transistor is connected to shunt the source reference voltage at the operational amplifier buffer in response to pulse width modulated signal. A second shunt transistor is connected to the differential operational amplifier so as to shunt the source reference voltage in response to an output of the first shunt transistor. The output of the differential amplifier provides a pulse width modulated bipolar signal at precision voltage levels in response to the pulse width modulated signal.
    Type: Grant
    Filed: October 14, 2012
    Date of Patent: December 31, 2013
    Assignee: AeroVironment, Inc.
    Inventor: Albert Flack
  • Publication number: 20130336650
    Abstract: An optical transceiver and/or optical network, and methods of monitoring optical transceivers, may be useful for increasing the dynamic range and/or determining the received signal strength and/or link budget of the optical transceiver and/or a different optical transceiver in the optical network. The circuitry generally comprises a photodiode configured to generate a first current responsive to an optical signal, a current mirror configured to produce a second current equal or proportional to the first current, and a nonlinear element configured to produce a first voltage from the first current.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Inventor: Mohammad AZADEH
  • Publication number: 20130335141
    Abstract: Apparatus and methods for electronic amplification are provided. In one embodiment, a method of electronic amplification includes amplifying a differential input voltage signal to generate a feed-forward signal, chopping the feed-forward signal at a chopping frequency to generate a chopped feed-forward signal, notch filtering the chopped feed-forward signal at the chopping frequency to generate a notched signal, generating an input offset correction signal based at least partly on the notched signal, and amplifying the differential input voltage signal using a signal amplification block to generate an output signal. Amplifying the differential input voltage signal using the signal amplification block includes chopping the input signal at the chopping frequency to generate a chopped input signal and combining the chopped input signal and the offset correction signal to reduce input offset error of the signal amplification block.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 19, 2013
    Applicant: Analog Devices, Inc.
    Inventor: Fazil Ahmad
  • Patent number: 8611561
    Abstract: An external audio signal is input to an input terminal which is connected to the first terminal of a first resistor. The first terminal of a second resistor is connected to the second terminal of the first resistor. An operational amplifier is arranged such that its inverting input terminal is connected to the second terminal of the second resistor, and a reference voltage is applied to its non-inverting input terminal. A third resistor is arranged between the output terminal and the inverting input terminal of the operational amplifier. A first diode is arranged between the second terminal of the first resistor and a power supply terminal such that its cathode is on the power supply terminal side. Furthermore, a second diode is arranged between the second terminal of the first resistor and the ground such that its cathode is on the second terminal side of the first resistor.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: December 17, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Mitsuteru Sakai
  • Patent number: 8604871
    Abstract: This invention discloses circuit and methods of a NAND-based 2T-string NOR flash cell structure as a building block for a fast random-read NOR flash memory. The key concept of this new set of bias conditions in cell array improves over the critical concern of punch-through issue when cell is migrating to the more advanced technology node of next generation. The invention adopts a novel preferable symmetrical 2T-string NOR flash cell. Each NAND or NAND like cell of this 2T-string NOR cell is to store 2 bits and is preferable to be made of N-channel device. The cell is preferable to use Fowler-Nordheim Tunneling scheme for both erase and program operations- The invention is to provide a novel 2T-string NOR flash cell structure made of N-channel device offering most flexible erase sizes in unit of byte, page, sector, block and chip with the least program and erase disturbances.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: December 10, 2013
    Assignee: Dialog Semiconductor GmbH.
    Inventor: Andrew Myles
  • Patent number: 8604882
    Abstract: A circuit for single ended to differential conversion is disclosed. The circuit comprises a source for providing a single ended signal; and a transformer for receiving the single ended signal. The transformer includes first and second inductors. The first and second inductors are mutually coupled. When the operating frequency changes, a phase difference of currents flowing through the inductors changes, and therefore a phase difference between effective impedance of the first and second inductors changes to maintain a substantially 180 degree phase difference due to the mutual coupling.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: December 10, 2013
    Assignee: Ralink Technology Corporation
    Inventor: Eric Chiyuan Lu
  • Patent number: 8593218
    Abstract: Aspects of the present invention provide apparatuses and methods to provide slew rate enhancement during an initial stage of operation of an amplifier and processing of an input signal with low noise introduction during a subsequent amplification stage of operation. During the initial stage, a high bandwidth component of the amplifier can be engaged to provide slew rate enhancement of the overall amplifier. The adaptive slew rate enhancement can be based on a detected imbalance of an output of a low bandwidth component of the amplifier. Once a desired operating state of the amplifier is achieved, the high bandwidth component can be disengaged. The low bandwidth component can then solely operate on a received input signal during the amplification stage. The low bandwidth component can be low power and can introduce low levels of noise, thereby ensuring minimal noise introduction and corruption of the amplified output signal of the amplifier.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: November 26, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Padraig Cooney
  • Patent number: 8581661
    Abstract: A reconfigurable amplifier comprising a first operational amplifier having two inputs and an output. A second operational amplifier having two inputs and an output. A plurality of switches coupled to the two inputs and the output of the first operational amplifier and the two inputs and the output of the second operational amplifier, wherein a first configuration of the plurality of switches causes the first operational amplifier and the second operational amplifier to operate as an inverting differential input amplifier, and wherein a second configuration of the plurality of switches causes the first operational amplifier and the second operational amplifier to operate as a non-inverting differential input instrumentation amplifier.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: November 12, 2013
    Assignee: Conexant Systems, Inc.
    Inventors: Brian W. Friend, Christian Larsen
  • Publication number: 20130293294
    Abstract: A programmable gain amplifier (“PGA”) may include a differential amplifier, a pair of input capacitors, a pair of feedback capacitors provided in feedback configuration about the amplifier, a first chop circuit, provided at an input of the PGA and an output of the PGA and a second chop circuit provided at an output of the PGA. The PGA also may include circuit systems to sample voltages across the input capacitors in a sampling phase. The sampled voltages may correspond to a difference between a common mode voltage of input signals to the PGA and a common mode voltage of the differential amplifier. The sampled voltage, thus, defines a common mode voltage at the amplifier's inputs during other phases of operation, when the chop circuits are operational.
    Type: Application
    Filed: August 22, 2012
    Publication date: November 7, 2013
    Applicant: ANALOG DEVICES, INC.
    Inventors: Colin G. LYDEN, Roberto S. MAURINO, Damien J. MCCARTNEY
  • Publication number: 20130293293
    Abstract: Compensation methods and systems for voltage-feedback amplifiers provide improved dynamic performance (i.e., increased bandwidth and the elimination or alleviation of a slew limitation) at high gains by direct feedback of an AC signal (i.e., an intermediate voltage) to an amplifier input without being attenuated by feedback resistor network.
    Type: Application
    Filed: May 4, 2012
    Publication date: November 7, 2013
    Inventor: Quan Wan
  • Patent number: 8576002
    Abstract: Embodiments of the present invention provide a sample and hold amplifier that provides a preamplifier with a multi-stage zeroing architecture. The multi-stage architecture reduces effects of parasitic capacitance exponentially over prior attempts, which yields increased accuracy.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: November 5, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Sanjay Rajasekhar
  • Publication number: 20130278331
    Abstract: A reference potential converter circuit comprises: a first resistor (resistance value R1) serving as a feedback resistor for an operational amplifier; a second resistor (resistance value R2) connected to the first resistor and a reference voltage; and a third resistor (reference value R3) and a fourth resistor (reference value R4) connected between a power supply and ground. A difference voltage between Vout and Vref is divided by an R1/R2 ratio and applied to an inverting input terminal of the operational amplifier. A power supply voltage is divided by an R3/R4 ratio and applied to a non-inverting input terminal of the operational amplifier. The R1/R2 ratio and the R3/R4 ratio are equal.
    Type: Application
    Filed: April 22, 2013
    Publication date: October 24, 2013
    Inventor: Masaaki Kamiya
  • Patent number: 8552799
    Abstract: A power amplifying circuit includes first and second operational amplifiers. The power amplifying circuit includes first to fourth feedback resistor. The power amplifying circuit includes a fully differential operational amplifier that is connected to the output terminal of the first operational amplifier at a non-inverting input terminal thereof, to the output terminal of the second operational amplifier at an inverting input terminal thereof, to a first signal output terminal at a non-inverting output terminal thereof, and to a second signal output terminal at an inverting output terminal thereof and maintains a constant differential gain. The power amplifying circuit includes a switching circuit. The power amplifying circuit includes first and second input resistors. The power amplifying circuit includes a midpoint potential controlling circuit that monitors a power supply voltage and controls the switching circuit.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: October 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Tsurumi
  • Publication number: 20130249627
    Abstract: When a time difference is amplified by a time difference amplifier, slew rates of internal output voltages are changed according to a phase combination of digital input signals so that a time gain is determined by a ratio between the slew rates and the slew rates can be controlled from an outside. After a voltage is charged to the level of a power supply voltage in first and second charging capacitors, the charged voltage of the first charging capacitor is decreased with a first slew rate when a first digital input signal transitions, and both charged voltages of the first and second charging capacitors are decreased with a second slew rate when a second digital input signal transitions so that both first and second digital input signals are changed from initial phases, while being compared with a reference voltage to generate first and second digital output signals.
    Type: Application
    Filed: June 28, 2012
    Publication date: September 26, 2013
    Applicant: POSTECH ACADEMY- INDUSTRY FOUNDATION
    Inventors: Hye-Jung KWON, Hong-June PARK
  • Patent number: 8541733
    Abstract: The invention provides a laser light detection circuit that prevents a peak output occurring when the circuit switches between the operation stop mode and the operation mode so as to prevent the breakdown or malfunction of the next-connected circuit. A laser light detection circuit has a differential amplifier that amplifies and outputs a signal corresponding to the intensity of laser light, a drive transistor having a base to which the output of the differential amplifier is applied, a second constant-current source connected to the emitter of the drive transistor, an output transistor having a base connected to the emitter of the drive transistor, a bypass transistor connected between the emitter of the drive transistor and the ground, and a control circuit. The control circuit forms a bypass current route from the second constant-current source to the ground through the bypass transistor by turning on the bypass transistor when the circuit switches from the operation stop mode to the operation mode.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: September 24, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventors: Rui Kurihara, Takahiro Kawashima
  • Publication number: 20130241638
    Abstract: A signal amplifier circuit for USB port includes a USB controller, an amplifier circuit, a USB port and a signal regulator circuit. The USB controller includes a super speed transmitter differential pair and a super speed receiver differential pair. The amplifier circuit includes two first input terminals, two second input terminals, two first output terminals, and two second output terminals. The USB port includes two first differential signal receiving terminals and two first differential signal transmitting terminals. The super speed transmitter differential pair and the super speed receiver differential pair are electrically connected to the first input terminals and the second output terminals. The first output terminals and the second input terminals are electrically connected to the first differential signal receiving terminals and the first differential signal transmitting terminals. The signal regulator circuit regulates amplitude and jitter of differential signals amplified by the amplifier circuit.
    Type: Application
    Filed: November 16, 2012
    Publication date: September 19, 2013
    Inventors: ZHI-MING ZHU, TING WANG
  • Publication number: 20130241637
    Abstract: An amplifier having an inverting input and a non-inverting input; a capacitor coupled to inverting input of the amplifier; an input voltage conveyance control circuit, having a first switch and a second switch, the first switch coupled to the capacitor, and the second switch coupled to the non-inverting input of the amplifier; a reference voltage conveyance control circuit having a third switch and a fourth switch, a shared node coupled between third switch and fourth switch, the fourth switch coupled to the non-inverting input of the amplifier; a fifth switch coupled to an output of the amplifier; a leakage control circuit having a sixth switch and seventh switch, the sixth switch coupled between the inverting amplifier input and the fifth switch, the seventh switch coupled to the sixth switch and the capacitor; and a first resistor coupled from the output of the amplifier to the first switch.
    Type: Application
    Filed: July 25, 2012
    Publication date: September 19, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vadim Valerievich Ivanov, Brian Phillip Lum-Shue-Chan, Karthik Kadirvel
  • Publication number: 20130244606
    Abstract: A receiving apparatus in a wireless communication system includes: an antenna configured to receive a wireless frequency signal including a first frequency band signal and a second frequency band signal; a low noise amplifier (LNA) configured to amplify the wireless frequency signal, output the first frequency band signal as a differential phase signal, and output the second frequency band signal as a common phase signal; a differentiator configured to pass only the differential phase signal between the signals outputted from the LNA; and a combiner configured to pass only the common phase signal between the signals outputted from the LNA.
    Type: Application
    Filed: March 19, 2012
    Publication date: September 19, 2013
    Inventors: Sang-Gug Lee, Yuna Shim
  • Patent number: 8525591
    Abstract: A signal level conversion circuit 1 includes a first differential amplifier circuit 10 and a second differential amplifier circuit 20. The first differential amplifier circuit 10 multiplies a potential difference between a first input signal and a second input signal by G1 thereby providing an output signal. The second differential amplifier circuit 20 multiplies a potential difference between the output signal of the first differential amplifier circuit 10 and the second input signal by G2 thereby providing an output, where the two gains satisfy the relation of G1×G2<0 and 0<?(G1+1)×G2<2.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: September 3, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Yoshinao Yanagisawa, Takayuki Kikuchi
  • Patent number: 8519785
    Abstract: A differential amplifier replicates the input stage and cross-connects the inputs, so that the input-to-output delay will be balanced in an averaged sense. The outputs of each of the two input stages are then summed after an open loop delay matched inversion has taken place. The result is a reduction in the duty cycle distortion of the receiver amplifier over process voltage and temperature (PVT) variation. This is enabled by the fact that a full swing CMOS delay cell can be made to have good delay matching over PVT, whereas the input stage to a differential amplifier may, depending on architecture, have poor delay matching because of impedance mismatches within the amplifier.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: August 27, 2013
    Assignee: Cavium, Inc.
    Inventor: Scott Meninger
  • Publication number: 20130214867
    Abstract: A power amplifier device includes an input terminal for a RF input signal. The power amplifier device includes an output terminal a RF output signal. The power amplifier device includes a first power amplifier connected to the input terminal, amplifies the RF input signal with a first gain, and outputs a first amplified signal. The power amplifier device includes a second power amplifier that amplifies a signal on the basis of the first amplified signal and outputs a second amplified signal with a second gain. The power amplifier device includes a low-pass filter or a band-pass filter that filters the second amplified signal. The power amplifier device includes an amplitude comparator to compare the first amplitude of the first comparison signal generated from the RF input signal with the second amplitude of the second comparison signal generated from the filtered signal and to output an amplitude comparison signal.
    Type: Application
    Filed: September 5, 2012
    Publication date: August 22, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Shouhei KOUSAI
  • Patent number: 8509629
    Abstract: The invention relates to amplifiers and in particular, to a transimpedance amplifier for high rate applications. Disclosed is a two stage transimpedance amplifier having a first stage comprising an amplifier and a load and a second stage comprising an amplifier and a resistor. Negative feedback is provided through a feedback resistor. Only two voltage conversions occur which reduces phase distortion, as compared to three stage transimpedance amplifiers which perform 3 voltage conversions.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: August 13, 2013
    Assignee: Mindspeed Technologies, Inc.
    Inventors: Hehong Zou, Krishna Shivaram, Daniel Draper
  • Patent number: 8508217
    Abstract: An output circuit of a charge mode sensor includes a second resistor and an operational amplifier. The second resistor connects an output portion of the charge mode sensor and a ground. The operational amplifier is configured to output a detection signal that varies in accordance with an amount of charge kept in the charge mode sensor. The operational amplifier includes an inverting input portion, a non-inverting input portion, and an output portion. The inverting input portion is connected to the output portion of the charge mode sensor via a sensor cable. The non-inverting input portion is connected to a reference voltage. The output portion is connected to the inverting input portion via a first resistor.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: August 13, 2013
    Assignee: Honda Motor Co., Ltd.
    Inventor: Yoshimasa Eguchi
  • Patent number: 8503967
    Abstract: An amplifier is arranged to receive an input signal and provide an output signal in response, and includes a main amplifier core and an auxiliary circuit. The main amplifier core includes an input node, an output node and a sum node with the input node coupled to the input signal, and is arranged to provide an interior signal to the sum node and output the output signal at the output node in response to signals provided to the sum node. The auxiliary circuit is coupled between the input node and the sum node, and is arranged to match an impedance of the input node and provide a cancelling signal to the sum node in response to the input signal. An associated receiver is also disclosed.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: August 6, 2013
    Assignee: Mediatek Inc.
    Inventor: Chih-Fan Liao
  • Publication number: 20130181772
    Abstract: An error amplifier, a controller using the error amplifier, and a primary-side feedback controlled AC/DC converter using the controller are discussed. When the output voltage of the primary-side feedback controlled AC/DC converter according to present invention changes, the alternating current path enjoys a fast response and adjusts the output voltage quickly with a lower precision, avoiding large voltage fluctuate, then the direct current path functions slowly to reduce equivalent output error. In such a way, the output voltage precision is enhanced while the stability of the primary-side feedback controlled AC/DC converter is maintained.
    Type: Application
    Filed: September 11, 2012
    Publication date: July 18, 2013
    Applicant: FREMONT MICRO DEVICES (SZ) LIMITED
    Inventor: Jianpei Zhu
  • Publication number: 20130181771
    Abstract: According to one embodiment, a light receiving circuit includes a light receiving element, an amplifier, and a first compensator. The light receiving element is configured to output an optical current by receiving an optical signal. The amplifier is configured to convert the optical current into a voltage and amplify the voltage. The first compensator is connected to the amplifier and configured to suppress a variation in an opposite direction from a voltage variation of the amplifier when the optical current increases.
    Type: Application
    Filed: August 27, 2012
    Publication date: July 18, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yukio TSUNETSUGU
  • Patent number: 8487699
    Abstract: Described is an inductive compensating network coupled between the differential inputs of an operational amplifier circuit. The inductive compensating network includes at least one inductive element having an inductance value selected so as to provide proper compensation of the operational amplifier circuit. Also described is a feedback compensation scheme which adjusts loop characteristics by introducing zeros into a system with the addition of inductive or capacitive elements in a feedback path.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: July 16, 2013
    Assignee: Massachusetts Institute of Technology
    Inventors: Douglas Jay Kozak Adams, Rahul Sarpeshkar
  • Patent number: 8489030
    Abstract: A radio apparatus capable of correcting a direct current offset with high accuracy in a short time is provided. A radio apparatus according to an embodiment includes a first amplifier amplifying a signal inputted to an input terminal with amplification gain determined by a variable resistor to generate a first amplified signal, and a second amplifier amplifying the first amplified signal to generate a second amplified signal. Further, the radio apparatus includes a first correcting unit correcting a direct current offset of the first amplifier, and a second correcting unit correcting a direct current offset of the second amplifier.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: July 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumi Moritsuka, Shoji Otaka, Masahiro Hosoya, Hiroaki Ishihara, Tsuyoshi Kogawa
  • Patent number: 8476975
    Abstract: An operational amplifying device comprises an input stage and an output stage. The input stage receives and processes an input voltage to output an amplified voltage. The output stage is electrically connected to the input stage in series. The output stage comprises a first switch and a second switch. The first switch is configured to turn on for transferring the amplified voltage. The second switch is connected in parallel with the first switch and is configured to turn on for transferring the amplified voltage. The second switch is turned off when the first switch is turned on such that the amplified voltage is transferred through the first switch to the first resistor array for gamma correction.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: July 2, 2013
    Assignee: Himax Technologies Limited
    Inventor: Zong-Fu Hsieh
  • Patent number: 8476974
    Abstract: A differential amplifier comprises a first amplifier (A1) with a signal input (Inp) and a signal output (Out1) that is fed back to a first feedback input (In1) of the first amplifier (A1) and is also connected to a first output (outp) of the differential amplifier. Furthermore, a buffer circuit (Buff) is connected to the first output (outp). A nonlinear resistor circuit (Rnl1, Rnl2) is coupled via a first output node (Vmid1) with the first output (outp) and via a second output node (Vmid2) with the buffer circuit (Buff).
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: July 2, 2013
    Assignee: AMS AG
    Inventors: Thomas Carl Froehlich, Wolfgang Duenser
  • Publication number: 20130162240
    Abstract: A system and method for analyte measurement is provided. The system includes: a transimpedance amplifier including: at least one operational amplifier including a first input coupling to a reference voltage, a second input coupling to a sensor for sensing the analyte, and an output; and at least one passive circuit element having a first terminal and a second terminal, the first terminal of the at least one passive circuit element coupling to the second input of the at least one operational amplifier, and a circuit for adjusting a gain of the transimpedance amplifier for the measurement of the analyte.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 27, 2013
    Applicant: On Semiconductor Trading Ltd.
    Inventors: Jakob Nielsen, Dustin Griesdorf
  • Patent number: 8461922
    Abstract: Techniques are disclosed for canceling an offset component (e.g., dc component or dc offset) in an amplifier circuit. For example, an apparatus comprises an amplifier circuit with an amplifier element and a feedback resistor network coupled between an output of the amplifier element and an input of the amplifier element. The apparatus also comprises a current source coupled to the feedback resistor network, the current source generating a current signal that generates a voltage in a first portion of the feedback resistor network that cancels an offset component present in an input signal received by the amplifier circuit. A second portion of the feedback resistor network may be adjustable so that a gain applied to the input signal is adjustable while the offset component is canceled from the input signal. One or more resistors in the feedback resistor network may be composed of the same or substantially similar material as one or more resistors associated with the current source.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: June 11, 2013
    Assignee: LSI Corporation
    Inventor: Robert Alan Norman
  • Patent number: 8456233
    Abstract: A chopper comprises a differential difference amplifier, a first switch, and a second switch. The differential difference amplifier comprises a first input stage and a second input stage. The first input stage comprises a non-inverting input terminal and an inverting input terminal. The second input stage comprises a non-inverting input terminal and an inverting input terminal. The first switch is operable to receive a first input voltage and a second input voltage and selectively transfer the first input voltage to one of the non-inverting input terminal of the first input stage and the non-inverting input terminal of the second input stage. The second switch is operable to receive a third input voltage and a fourth input voltage and selectively transfer the third input voltage to one of the inverting input terminal of the first input stage and the inverting input terminal of the second input stage.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: June 4, 2013
    Assignee: Himax Technologies Limited
    Inventor: Zong-Fu Hsieh
  • Patent number: 8451052
    Abstract: An input stage for an instrumentation system may include a resistor coupled between an input terminal and a summing node, and an amplifier arranged to maintain the voltage at the summing node. In anther embodiment, an instrumentation input system may include an input stage to receive a signal to be measured, and a variable gain amplifier having an input coupled to an output of the input stage, wherein the variable gain amplifier comprises two or more gain stages. A variable gain amplifier may include an attenuator having an input and a series of tap points and a series of low-inertia switches to steer outputs from the attenuator to an output terminal.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: May 28, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Barrie Gilbert
  • Publication number: 20130114665
    Abstract: A variable gain amplifier (VGA) useful in a receiver that recovers transmitted digital signals. A first amplifier in the VGA has a first gain, an input coupled to an input of the VGA, and an output coupled to a load. A second amplifier in the VGA has a second gain, an input coupled to the input of the VGA, and an output coupled to the load. In a first mode of operation, the first gain is substantially zero and the second gain ranges between a maximum gain and a fraction of the maximum gain. In a second mode of operation the first gain is substantially the maximum gain and the second gain ranges between the maximum gain and the fraction of the maximum gain, and an algebraic sum of the first gain and second gain is no greater than the maximum gain to reduce non-linear distortion at low VGA gain.
    Type: Application
    Filed: November 3, 2011
    Publication date: May 9, 2013
    Inventors: Pervez M. Aziz, Hiroshi Kimura
  • Publication number: 20130106506
    Abstract: An adjustable gain audio power amplifying circuit includes an input unit, an audio amplifying unit connected to the input unit, a gain adjusting unit connected to the audio amplifying unit, a controlling unit connected to the gain adjusting unit, a comparing unit connected between the gain adjusting unit and the controlling unit and an output unit connected to the audio amplifying unit. The comparing unit compares an outputted signal of the output unit with a common-mode reference voltage, outputs a gain adjustment controlling signal and sends the gain adjustment controlling signal into the controlling unit. When the outputted signal equals the common-mode reference voltage, the gain adjustment controlling signal turns over and then the controlling unit detects the turnover and sends a received gain adjustment signal into the gain adjusting unit. Based on the received gain adjustment signal, the gain adjusting unit controls gains of the adjustable gain audio power amplifying circuit.
    Type: Application
    Filed: June 13, 2012
    Publication date: May 2, 2013
    Inventor: Guojun Zhu