Relaxation Oscillator Patents (Class 331/111)
  • Patent number: 11095276
    Abstract: A relaxation oscillator with an aging effect reduction technique comprises a comparator (CP) coupled with its input side (CP1, CP2) to a network comprising at least one capacitor (C, C1, C2), a plurality of transistors (M1, M2, M3, M4) and a plurality of controllable switches (SW11, . . . , SW8, SW111, . . . , SW180). The relaxation oscillator uses a switching method such that the roles of current/voltage generator's transistor and current mirror transistor are periodically swapping by the output signal of the relaxation oscillator. Reducing mismatch of operating points between current/voltage generator and current minor transistors achieves a decrease of frequency degradation caused by aging effect.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: August 17, 2021
    Assignee: AMS AG
    Inventor: Tetsuro Okura
  • Patent number: 11043936
    Abstract: A relaxation oscillator includes an adjustable reference circuit generator to produce a reference current which is applied to a charging circuit. The charging circuit is configured to charge a capacitive node as a function of the reference current and a capacitance of an adjustable capacitor that is operably coupled to the capacitive node. A comparator having inputs operatively coupled to a reference voltage node and to the capacitive node, generates a comparator output. A control circuit alternatively enables the charging circuit to charge the capacitive node and to discharge the capacitive node in response to changes in the comparator output. Also, the control circuit outputs and oscillator output signal have an oscillator period as a function of the adjustable capacitance and the adjustable reference current.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 22, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hsien-Hung Wu
  • Patent number: 11012082
    Abstract: A multiphase clock generator includes a current mirror, a voltage controller, a pseudo-resistor circuit and a first delaying circuit. The current mirror includes a receiving terminal, a first mirroring terminal and a second mirroring terminal. The voltage controller is connected with the receiving terminal of the current mirror. A feedback terminal of the voltage controller is connected with the first mirroring terminal of the current mirror. A first terminal of the pseudo-resistor circuit is connected with the first mirroring terminal of the current mirror. A second terminal of the pseudo-resistor circuit is connected with a ground terminal. The first delaying circuit is connected with the second terminal of the pseudo-resistor circuit. An input terminal of the first delaying circuit receives a first input clock signal. An output terminal of the first delaying circuit generates a first delayed clock signal.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: May 18, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Che-Wei Chang
  • Patent number: 11003204
    Abstract: Examples described herein provide for a relaxation oscillator and corresponding methods of operation. In an example, a circuit includes a dynamically controllable current source, a capacitor, and an oscillator generation circuit. The dynamically controllable current source includes a digitally tunable current mirror configured to generate a current. The digitally tunable current mirror includes multiple transistors configured to be selectively electrically connected in parallel to alter a gain of the digitally tunable current mirror to control the current. The capacitor is selectively electrically connected to the dynamically controllable current source. The oscillator generation circuit is electrically connected to the capacitor. The oscillator generation circuit is configured to generate an oscillation signal in response to a voltage of the capacitor.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: May 11, 2021
    Assignee: XILINX, INC.
    Inventors: Ionut C. Cical, Edward Cullen, Brendan Farley
  • Patent number: 10979033
    Abstract: A current-controlled oscillator receives an input current. Ramp voltage generating circuitry generates first and second ramp voltages in response to the input current. Selecting circuitry selects one of the first and second ramp voltages depending on their relative values. Switching circuitry receives a selected ramp voltage, generates a signal based on the selected ramp voltage relative to a reference voltage, and outputs a clock signal. In one embodiment, a comparator receives the reference voltage, one of the first and second ramp voltages, and outputs a comparison signal. Logic circuitry controls the ramp voltage generating circuitry to output one of the ramp voltages during one half of a clock cycle and to output the other ramp voltage during another half cycle of the clock signal based on the comparison signal and logic states of the logic circuitry.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 13, 2021
    Assignee: NXP USA, Inc.
    Inventors: Andre Luis Vilas Boas, Felipe Ricardo Clayton
  • Patent number: 10956538
    Abstract: The present disclosure relates to a low-power measuring device. In one implementation, the low-power measuring device includes a first sensor for measuring a first value, the first value being a measurement of a variable, and a counter unit for generating a first counter value indicative of a first elapsed time since the first value is measured by the first sensor. The low-power measuring device further includes at least one processor configured to send the first value to a remote apparatus, send the first counter value to the remote apparatus, cause the remote apparatus to determine the first elapsed time based on the first value and the first counter value, and cause the remote apparatus to determine a first obtained time at which the first value is measured by the first sensor based on the determined first elapsed time and a reference time of the remote apparatus.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: March 23, 2021
    Assignee: Verily Life Sciences LLC
    Inventor: Russell Mirov
  • Patent number: 10938393
    Abstract: An oscillator is configured to generate a signal with a frequency sweep, the oscillator having circuitry comprising a set of capacitors, each capacitor of the set of capacitors being switchably connectable in parallel in the circuitry so that the frequency of the signal has an intrinsic dependence on the number of the capacitors connected, a shift register controllable by a clock line and comprising a number of bits, each bit of the number of bits controlling connection of a respective capacitor of the set of capacitors so that the capacitors are connectable or disconnectable in a pre-determined order by shifting, respectively, activation or de-activation bits into the shift register, wherein the shifting is paced by the clock line; and a clock signal generator configured to output a clock signal with a time modulation on the clock line.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: March 2, 2021
    Assignee: Stichting IMEC Nederland
    Inventors: Wilfried Zomagboguelou, Paul Mateman, Yao-Hong Liu
  • Patent number: 10879858
    Abstract: An oscillator circuit uses a comparator, and the oscillator circuit controls charge-discharge of the Miller capacitance between the gate and the drain of a MOSFET serving as an amplifier of the gain unit and the gate capacitance of the MOSFET, and enables the comparator output to follow a relatively high-frequency control signal that is input externally. The oscillator circuit uses a comparator having a differential unit and a gain unit. The oscillator circuit includes a charge-discharge control unit that connects to the output of the differential unit and is configured to control charge-discharge of the Miller capacitance between the gate and the drain of a MOSFET (N2) serving as an amplifier of the gain unit and the gate capacitance of the MOSFET, and an output control unit configured to control the output of the gain unit.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: December 29, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Kenji Nakagomi
  • Patent number: 10873292
    Abstract: Relaxation oscillators with delay compensation are provided herein. In certain embodiments, a relaxation oscillator includes a capacitor, a current source that outputs a charging current, and control circuitry that operates to selectively charge the capacitor with the charging current. The control circuitry includes a primary or main comparator operable to compare a charging voltage of the capacitor to a threshold voltage. The relaxation oscillator further includes delay compensation circuitry coupled to the capacitor and operable to adjust the threshold voltage to provide compensation for a delay of the control circuitry.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: December 22, 2020
    Assignee: Analog Devices International Unlimited Company
    Inventor: Issa Niakate
  • Patent number: 10852199
    Abstract: The temperature-dependent resistance of a MEMS structure is compared with an effective resistance of a switched CMOS capacitive element to implement a high performance temperature sensor.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: December 1, 2020
    Assignee: SiTime Corporation
    Inventors: Michael H. Perrott, Shungneng Lee
  • Patent number: 10854149
    Abstract: A method of driving a light-source module includes adjusting a frequency of a boosting switching signal based on a dimming signal which controls luminance of a light-emitting diode (“LED”) string of the light-source module, where the LED string comprises a plurality of LEDs connected to each other in series, and controlling a main transistor in response to the boosting switching signal to transfer a driving voltage to the LED string.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: December 1, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung-Wan Kim, Min-Soo Choi, Gwang-Teak Lee, Tae-Gon Im, Myoung-Soo Kim, Hwan-Woong Lee, Seung-Young Choi
  • Patent number: 10848133
    Abstract: An oscillator includes a constant current generator configured to generate a constant current by maintaining a predetermined potential difference between both a first end and a second end of a resistor, and an oscillating element configured to output a clock signal corresponding to a charge and discharge cycle of a capacitor based on a bias current corresponding to the constant current.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: November 24, 2020
    Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation Sungkyunkwan University
    Inventors: Jonghan Kim, Chisung Bae, Jaemin Choi, Yoonmyung Lee, Jung-Hoon Chun
  • Patent number: 10839888
    Abstract: Systems and methods relate to interpolating values in a transfer function between a first parameter (e.g., temperature) and a second parameter (e.g., voltage). A decoder is configured to receive a temperature value and multiple trim codes each corresponding to one temperature. Decoder and adder circuitry is configured to receive the temperature value from the decoder and to receive two closest trim codes of the plurality of trim codes corresponding to two closest temperatures of the temperatures that are closest to the temperature value. The decoder and adder circuitry then calculates an output trim code based at least in part on the two closest trim codes; outputs the trim code.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Dong Pan
  • Patent number: 10833654
    Abstract: The oscillator circuit comprises first and second integrator units with a first capacitor charged at a first integration node and a second capacitor charged at a second integration node. A comparator unit is arranged between a first switching unit, which is connected to the integration nodes and to a reference signal (VREF), and a second switching unit. The comparator unit compares a signal from the first or second integration node with the reference signal. The second switching unit is connected to a logic unit configured to provide signals controlling the first integrator unit, the second integrator unit, the first switching unit and the second switching unit, so that a periodic operation is generated by alternatingly activating the first integrator unit and the second integrator unit.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: November 10, 2020
    Assignee: ams AG
    Inventors: Josip Mikulic, Gregor Schatzberger
  • Patent number: 10833630
    Abstract: Apparatuses and methods for temperature independent oscillator circuits are disclosed herein. An example apparatus may include a pulse generator circuit configured to provide a periodic pulse based on the charging and discharging and discharging of a capacitor and further based on a reference voltage. The pulse generator circuit may include a capacitor coupled between a first reference voltage and a first node, wherein the capacitor is configured to be charged and discharged through the node in response to the periodic pulse, a resistor and a diode coupled in series between a second node and a second reference voltage, and a comparator coupled to the first and second nodes and configured to provide the periodic pulse based on voltages on the first and second nodes, wherein a period of the periodic pulse is based at least on the resistor and the a current.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jun Wu, Dong Pan
  • Patent number: 10826474
    Abstract: A clock generation circuit and a clock adjustment method thereof are provided. The clock generation circuit includes a fixed clock source, a variable clock source, a timing adjustment circuit, and a pulse width signal generator. The fixed clock source generates a reference clock signal having a fixed frequency. The variable clock source receives a frequency setting signal to correspondingly generate an operational clock signal having a variable frequency. The timing adjustment circuit determines whether a frequency of the operation clock signal is N times of a target frequency according to the reference clock signal to set a frequency of the operation clock signal. The pulse width signal generator divides the operating clock signal to generate a pulse width modulation signal having the target frequency.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: November 3, 2020
    Assignee: Nuvoton Technology Corporation
    Inventors: Ta-Chin Chiu, Chieh-Sheng Tu
  • Patent number: 10819344
    Abstract: A logic cell, including a first capacitor connected between an application node for applying a supply voltage of the cell and a floating node for providing an output logic signal of the cell, and, connected in parallel with the first capacitor, an association in series of a second capacitor and a first variable-resistance element, the first variable-resistance element including a control electrode connected to an application node for applying a first input logic signal of the cell.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: October 27, 2020
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Hervé Fanet, Gaël Pillonnet
  • Patent number: 10778199
    Abstract: Techniques for compensating temperature-dependent aspects of oscillator circuits are provided. In an example, an oscillator circuit can include an oscillator capacitor, a comparator and overshoot compensation circuitry for providing an oscillation period insensitive to a temperature-dependent comparator overshoot. The oscillator capacitor can be charged during a charging portion of the oscillation period and can be discharged during a discharging portion of the oscillation period. The comparator can determine when the oscillator capacitor has been charged to a first threshold. The overshoot compensation circuitry can store an indication of temperature-dependent comparator overshoot and, in response, generate and apply an adjustable reference voltage or pre-charge to a terminal of the oscillator capacitor.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: September 15, 2020
    Assignee: Analog Devices International Unlimited Company
    Inventors: Yihui Chen, Alex Xiao, Wendy Mao, Jie He
  • Patent number: 10769642
    Abstract: Briefly, an intelligent label is associated with a good, and includes one or more permanent and irreversible electrochromic indicators that are used to report the condition of that good at selected points in the movement or usage of that good. These electrochromic indicators provide immediate visual information regarding the status of the good without need to interrogate or communicate with the electronics or processor on the intelligent label. In this way, anyone in the shipping or use chain for the good, including the end user consumer, can quickly understand whether the product is meeting shipping and quality standards. If a product fails to meet shipping or quality standards, the particular point where the product failed can be quickly and easily identified, and information can be used to assure the consumer remains safe, while providing essential information for improving the shipping process.
    Type: Grant
    Filed: June 17, 2018
    Date of Patent: September 8, 2020
    Assignee: Chromera, Inc.
    Inventors: Paul Atkinson, James Kruest
  • Patent number: 10763785
    Abstract: Embodiments can provide individualized controlling of noise injection during startup of a crystal oscillator. In some embodiments, a simple learning block can be placed in parallel to a crystal oscillator circuit to control noise injection during the startup of the crystal oscillator. The learning block can be configured to control the noise injection during the startup of the crystal oscillator by determining whether the crystal oscillator has been stabilized. In some implementations, an adjustment block may be employed to adjust the count determined by the learning block based on one or more characteristics of the crystal oscillator during a startup of the crystal oscillator. In some embodiments, a simple block that creates a negative capacitance can be configured in parallel to the crystal oscillator.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 1, 2020
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventors: Amr Abuellil, Janakan Sivasubramaniam
  • Patent number: 10742221
    Abstract: A circuit device includes an oscillation circuit that generates an oscillation signal by using an resonator, a processing circuit that controls the oscillation circuit, and a storage circuit that stores temperature compensation data of an oscillation frequency of the oscillation signal. The processing circuit generates specific PUF information of the circuit device on the basis of the temperature compensation data.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: August 11, 2020
    Assignee: Seiko Epson Corporation
    Inventors: Toshiya Usuda, Masayuki Kamiyama
  • Patent number: 10742200
    Abstract: In an embodiment an oscillator circuit comprises a first integrator-comparator unit, a second integrator-comparator unit, and a logic circuit. The first integrator-comparator unit is prepared to provide a first signal as a function of a first integration of a first charging current and a subsequent comparison of a first integration signal resulting from the first integration with a reference signal. The second integrator-comparator unit is prepared to provide a third signal as a function of a second integration of a second charging current and a subsequent comparison of a second integration signal resulting from the second integration with the reference signal. The logic circuit is adapted to provide a clock signal, a first and a second measurement signal for respectively controlling the first and the second integrator-comparator unit.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: August 11, 2020
    Assignee: ams AG
    Inventors: Josip Mikulic, Gregor Schatzberger
  • Patent number: 10727822
    Abstract: The invention provides a comparator and a relaxation oscillator. The comparator comprises a comparator circuit. The comparator circuit comprises a current mode comparator circuit. The current mode comparator circuit comprises a first current mode comparison circuit and a second current mode comparison circuit. Both the first current mode comparison circuit and the second current mode comparison circuit are electrically connected with a first input end and a second input end of the comparator circuit; the first current mode comparison circuit comprises two N-type MOS transistors; gate electrodes of the two N-type MOS transistors are electrically connected with each other; the second current mode comparison circuit comprises two P-type MOS transistors; and gate electrodes of the two P-type MOS transistors are electrically connected with each other. The oscillator comprises the comparator.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: July 28, 2020
    Assignee: ALLWINNER TECHNOLOGY CO., LTD.
    Inventor: Suyan Fan
  • Patent number: 10720885
    Abstract: Relax oscillation circuits have at least one comparison circuit that is structured with a flipped gate transistor and a normal MOS transistor wherein the two transistors having different threshold voltages. The relaxation oscillators are configured for charging and discharging capacitances between the threshold voltages of the flipped gate transistor and the normal MOS transistor by toggling the state of a latching circuit to control the charging and discharging of the capacitances.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: July 21, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Daisuke Kobayashi, Julian Tyrrell
  • Patent number: 10707843
    Abstract: This invention provides a relaxation oscillator, including a first comparator, a second comparator, an SR latch, and a capacitor control module. Input ends of the two comparators are coupled with the capacitor control module and an external reference threshold voltage, and two output ends are coupled with the input ends of the SR latch; output ends of the SR latch are coupled with input ends of the capacitor control module; According to the external reference threshold voltage, a first comparison signal generated by the first comparator and a second comparison signal generated by the second comparator are inputted into the SR latch to generate a control signal. According to a bias current of the external bias current source and the control signal outputted by the SR latch, periodic charging and discharging of a first capacitor and a second capacitor are controlled to generate oscillating signals.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: July 7, 2020
    Assignee: AMPLIPHY TECHNOLOGIES LIMITED
    Inventors: Hehong Zou, Yichao He, Qingping Li
  • Patent number: 10693394
    Abstract: A driving apparatus of a vibration-type actuator includes a driving circuit configured to drive a vibration unit including a plurality of vibrators, a detection unit configured to detect a sum of power consumption consumed by the plurality of vibrators, and a driving frequency setting unit configured to set a driving frequency within a frequency range depending on the sum of power consumption detected by the detection unit.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: June 23, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Akio Atsuta
  • Patent number: 10686373
    Abstract: Systems and methods are provided for regulating a power converter. An example system controller includes: a driver configured to output a drive signal to a switch to affect a current flowing through an inductive winding of a power converter, the drive signal being associated with a switching period including an on-time period and an off-time period. The switch is closed in response to the drive signal during the on-time period. The switch is opened in response to the drive signal during the off-time period. A duty cycle is equal to a duration of the on-time period divided by a duration of the switching period. One minus the duty cycle is equal to a parameter. The system controller is configured to keep a multiplication product of the duty cycle, the parameter and the duration of the on-time period approximately constant.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: June 16, 2020
    Assignee: On-Bright Electronics (Shanghai) Co., Ltd.
    Inventors: Qian Fang, Cong Lan, Lieyi Fang
  • Patent number: 10666235
    Abstract: A temperature compensated oscillation circuit is provided. The temperature compensated oscillation circuit generates a first delay voltage and a second delay voltage according to the first resistance value. A first order term of a temperature change function of the first resistance value is eliminated. The temperature compensated oscillation circuit generates a reference voltage according to a first reference resistance value and a second reference resistance value. A first order term of a temperature change function of the first reference resistance value is set to equal to a first order term of a temperature change function of the second reference resistance value. The second reference resistance value is adjusted such that variation of the reference voltage matches a second order term of the temperature change function of the first resistance value, thereby providing a clock that does not vary due to a variation in temperature.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: May 26, 2020
    Assignee: ITE Tech. Inc.
    Inventors: Chia-Yuan Chou, An-Chi Tsai
  • Patent number: 10651831
    Abstract: An oscillation circuit small in circuit scale and in the influence of temperature on its oscillation frequency is provided. The oscillation circuit includes: a constant current circuit configured to supply a current based on a first depletion MOS transistor; a charge/discharge circuit having a first capacitor, a second capacitor, a second depletion MOS transistor, and a third depletion MOS transistor provided in a current path for charging the second capacitor, the first to third depletion MOS transistors having the same threshold voltage and the same temperature characteristics of the threshold voltage; and an RS latch circuit configured to output a waveform that falls by input of the reset signal and rises by input of the set signal.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: May 12, 2020
    Assignee: ABLIC INC.
    Inventor: Kotaro Watanabe
  • Patent number: 10606560
    Abstract: Deterministic asymmetry in a random number generator can be mitigated by a circuit that includes a first inverter, a second inverter, a first capacitor, a second capacitor, a first switch, and a second switch. The first inverter can include a first input terminal and a first output terminal. The first inverter can have a first inverter threshold voltage. The second inverter can include a second input terminal and a second output terminal. The second inverter can have a second inverter threshold voltage. The first capacitor can be conductively coupled between the first output terminal and the second output terminal. The second capacitor can be conductively coupled between the second output terminal and the first input terminal. The first switch can be conductively coupled between the first input terminal and the first output terminal. The second switch can be conductively coupled between the second input terminal and the second output terminal.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: March 31, 2020
    Assignee: VERILY LIFE SCIENCES LLC
    Inventors: Nathan Pletcher, Robert Wiser, Alireza Dastgheib
  • Patent number: 10601408
    Abstract: In described examples, a sawtooth waveform generator generates a sawtooth waveform having a first rise time. A comb waveform circuit has a power terminal coupled to receive the sawtooth waveform from an output of the sawtooth waveform generator. The comb waveform circuit generates a comb waveform in response to the sawtooth waveform. The comb waveform has a second rise time that is faster than the first rise time.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: March 24, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rajat Chauhan, Vipul Kumar Singhal, Vinod Joseph Menezes, Mahesh Madhukar Mehendale
  • Patent number: 10601407
    Abstract: A comparator-based oscillator generates an output frequency that is relatively independent of comparator offset voltages. Charging/discharging circuitry controls the comparator input voltage, and logic circuitry generates the oscillator output (e.g., clock) signal and controls the charging/discharging circuitry. During an oscillator charging cycle, the charging/discharging circuitry drives the voltage at the comparator input node from a relatively low initial charging voltage level up to the comparator reference voltage. During an oscillator discharging cycle, the charging/discharging circuitry drives the voltage at the comparator input node from a relatively high initial discharging voltage level down to the comparator reference voltage. The initial charging and discharging voltage levels depend on the comparator reference voltage, such that a comparator offset voltage directly affects the initial charging and discharging voltage levels, thereby keeping the output frequency relatively unchanged.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: March 24, 2020
    Assignee: NXP USA, Inc.
    Inventors: Bodh Raj Gautam, Kaushlendra Trivedi
  • Patent number: 10581441
    Abstract: A clock signal generator includes ramp and threshold voltage generators. The clock signal generator further includes a comparator configured to initiate a first phase of a clock signal based on the ramp and threshold voltages applied to its first and second inputs, respectively. The comparator is further configured to initiate a second phase of the clock signal based on the ramp and threshold voltages applied to its second and first inputs, respectively. Because the application of the ramp and threshold voltages to the inputs of the comparator is swapped per phase of the clock signal, any offset voltage in the comparator does not affect the period of the clock signal because they cancel out after two-half periods. This ensures that the clock signal has a substantially constant frequency. Other features include enabling the high power consuming comparator during a small window to achieve low jitter and low average power consumption.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: March 3, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Yu Pu, Jongrit Lerdworatawee, Chunlei Shi
  • Patent number: 10523184
    Abstract: An oscillator for a pulse width modulation (PWM) controller includes an oscillation circuit including a capacitor and configured to generate a first pulse signal by charging and discharging the capacitor, a frequency divider configured to generate a second pulse signal based on the first pulse signal, the second pulse signal having a lower frequency than the first pulse signal, and an oscillation control circuit coupled to the oscillation circuit and the frequency divider and configured to generate control signals for holding the charging and discharging of the capacitor during an oscillation holding operation.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: December 31, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Wookang Jin, Sungwon Yun, Youngmo Yang
  • Patent number: 10461724
    Abstract: A relaxation oscillator can provide a smaller and cheaper alternative to a crystal oscillator circuit in a wide variety of applications. A sawtooth relaxation oscillator can include overshoot error integration. Separate and distinct oscillator capacitor charging, overshoot error integration, and reset phases can be provided using separate comparators for first and second oscillation capacitors. Potential advantages can include high accuracy high-frequency clock, convenient trimming during initial calibration, clock frequency stability over temperature and time, fast startup with low overshoot, high power supply rejection, low power, or low noise/jitter. The oscillator can charge an oscillation capacitor up to a target voltage, then interrupt charging before beginning an error integration phase that adjusts the target voltage by integrating an overshoot error of a voltage on the oscillation capacitor. After completing the overshoot error integration, the voltage on the oscillation capacitor can be reset.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: October 29, 2019
    Assignee: Analog Devices Global
    Inventors: Jonathan Ephraim David Hurwitz, Sean B. Brennan
  • Patent number: 10430159
    Abstract: A hardware random number generator comprises a gas discharge tube, an average voltage generator, and a comparator. The gas discharge tube includes first, second, and third terminals and may generate a variable voltage on the second terminal when a supply voltage is applied to the first and third terminals. The average voltage generator receives the variable voltage from the gas discharge tube and may generate an average voltage equal to a moving average value of the variable voltage over successive periods of time. The comparator receives the variable voltage and the average voltage and may generate a random stream of data bits, such that a value of each bit varies according to the relative magnitudes of the variable voltage and the average voltage.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: October 1, 2019
    Assignee: Honeywell Federal Manufacturing & Technologies, LLC
    Inventor: Lawrence Christopher Crosier
  • Patent number: 10389337
    Abstract: A ramp generator includes a current generator, a current mirror, and a first capacitor. The current generator has an input for receiving a clock signal, and an output for providing a current proportional to a frequency of the clock signal using a first transistor having first and second current electrodes and a control electrode, an amplifier that establishes a reference voltage on the second current electrode of the first transistor, and a variable resistor coupled between the second current electrode of the second transistor and ground whose resistance is set according to the frequency of the clock signal. The current mirror has an input coupled to the first terminal of the first transistor, and a second terminal. The first capacitor has a first terminal coupled to the output of the current mirror and providing a ramp signal, and a second terminal coupled to the first power supply voltage terminal.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: August 20, 2019
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Hua Zhu, Kaiwei Yao
  • Patent number: 10348277
    Abstract: There is provided an oscillator which includes a current source, a capacitor coupled between the current source and a reference ground, a first switch coupled to the capacitor in parallel, an error amplifier, a comparator and a one-shot circuit. The error amplifier is coupled to the capacitor and configured to generate a regulation voltage based on a reference voltage and the voltage across the capacitor. The comparator is configured to compare the voltage across the capacitor with the regulation voltage and generate a comparison signal. The one-shot circuit is coupled to the comparator, wherein based on the comparison signal, the one-shot circuit generates a trigger signal to control the first switch.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: July 9, 2019
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventor: Li Xu
  • Patent number: 10325634
    Abstract: The present invention provides a differential sensing circuit with a dynamic voltage reference for a single-ended bit line memory is disclosed. The exemplary differential sensing circuit comprises: a dynamic voltage reference generating unit and a differential sensing amplifying unit. The dynamic voltage reference generating unit is coupled to an input voltage, and utilized for receiving a setting signal to generate the dynamic voltage reference. The differential sensing amplifying unit is coupled to the single-ended bit line memory and the dynamic voltage reference generating unit, and utilized for receiving at least an input signal from the single-ended bit line memory and the dynamic voltage reference from the dynamic voltage reference generating unit, so as to generate at least an output signal accordingly.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: June 18, 2019
    Assignee: MediaTek Inc.
    Inventors: Shih-Huang Huang, Rei-Fu Huang
  • Patent number: 10260957
    Abstract: A time domain integrated temperature sensor described by the present invention adopts a shaped clock signal to control the charging time of capacitors, so that the capacitors generate charging time delay signals related to the cycle of an input clock, and a pulse signal related to pulse width, temperature and the cycle of the input clock is generated through logical XOR (Exclusive OR) operation on a time delay signal generated when the capacitors are charged by one way of PTAT (Proportional To Absolute Temperature) current in an above control manner and a time delay signal generated when the capacitors are charged by one way of CTAT (Complementary To Absolute Temperature) current in the same manner; then, the same input clock signal is adopted for quantifying the pulse width of the pulse signal, the relevance of the obtained quantization result and the cycle of the input clock is completely offset, namely, an output value of the temperature sensor is unrelated to the input clock signal, thereby solving the pr
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: April 16, 2019
    Assignees: EXCELIO TECHNOLOGY (SHENZHEN) CO., LTD., WUXI EXCELIO TECHNOLOGY CO., LTD.
    Inventors: Bill Ma, Patrick Bian Wu, Fuqiang Han
  • Patent number: 10230351
    Abstract: Apparatus and methods for distributing spurious tones through the frequency domain are disclosed. One such apparatus can include a dithering circuit configured to generate a sequence of numbers that exhibit statistical randomness and a variable frequency circuit configured to adjust a frequency of an output based on the sequence of numbers so as to spread energy of spurious tones in a frequency response of the output to lower a noise floor. In one example, spurious tones can be reduced in a negative voltage generator of a radio frequency (RF) attenuator.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: March 12, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Thomas Obkircher, William J. Domino, Bipul Agarwal
  • Patent number: 10201698
    Abstract: Systems and methods for the concurrent treatment of multiple oral diseases and defects while promoting general oral hygiene utilizing electricity are provided for non-human animals. Electrodes are used to deliver an electrical current to the gingival tissues of a mouth in order to achieve a number of therapeutic, prophylactic, and regenerative benefits. These benefits include killing oral microbes, increasing oral vasodilation, reducing oral biofilm, improving oral blood circulation, reversing oral bone resorption, promoting oral osteogenesis, treating gum recession, and fostering gingival regeneration. Other benefits include the treatment of gingivitis, periodontitis, and oral malodor, and other systemic diseases correlated with oral pathogens.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: February 12, 2019
    Assignee: Animal Oralectrics LLC
    Inventors: Paul L Ruflin, Michael J Keller, Michael V Kaminski, Scott Mizer, Robert Armstrong
  • Patent number: 10153728
    Abstract: A circuit includes a first digital controlled oscillator and a second digital controlled oscillator coupled to the first digital controlled oscillator. A skew detector is connected to determine a skew between outputs of the first digital controlled oscillator and the second digital controlled oscillator, and a decoder is utilized to output a control signal, based on the skew, to modify a frequency of the first digital controlled oscillator using a switched capacitor array to reduce or eliminate the skew. A differential pulse injection oscillator circuit and a pulse injection signal generator circuit are also provided.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: December 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lan-Chou Cho, Huan-Neng Chen, Chewn-Pu Jou, Feng Wei Kuo
  • Patent number: 10141914
    Abstract: An oscillation circuit includes a delay circuit that includes a first inverter having an input terminal connected to a first node, a delay adjustment circuit including first and second current supply paths through which the first node is charged in response to an output signal of the delay circuit. During charging of the first node, a current with positive temperature characteristics is supplied to the first node through the first current supply path, and a current with negative temperature characteristics is supplied to the first node through the second current supply path.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: November 27, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Chen Kong Teh
  • Patent number: 10128794
    Abstract: An oscillator produces an oscillator output signal usable as a clock signal, otherwise as a frequency reference on an integrated circuit. The oscillator includes an RC network with a voltage-controlled element, such as a voltage-controlled resistor, voltage-controlled capacitor or a combination including a voltage-controlled resistor and voltage-controlled capacitor. Also, a tunable element having an adjustable resistance determined by a first static parameter is included in the RC network. The oscillator also includes a feedback circuit which can include a frequency-to-voltage converter. The feedback circuit generates a control signal for the voltage-controlled element. The feedback circuit includes a feedback reference circuit having a reference output determined by a second static parameter, and a loop amplifier responsive to the reference output and the oscillator output signal.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 13, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hsien-Hung Wu
  • Patent number: 10027312
    Abstract: A relaxation oscillator for generating a low temperature coefficient (LTC) clock signal includes a reference voltage generator and an oscillator. The reference voltage generator generates an LTC current and a bandgap reference voltage. The reference voltage generator includes positive temperature coefficient (PTC) resistors to compensate for the effects of temperature variations. The oscillator receives the LTC current and the bandgap reference voltage, and generates a clock signal. In another embodiment, the reference voltage generator generates a charge current that varies with temperature. The oscillator receives the charge current and generates first and second output signals. Set and reset comparators include PTC resistors that determine the gains of the set and reset comparators. The PTC resistors compensate for variation in the first and second output signals due to the temperature variations by varying the gains of the set and reset comparators.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: July 17, 2018
    Assignee: NXP USA, INC.
    Inventors: Yang Wang, Jianzhou Wu, Yizhong Zhang, Hao Zhi, Bin Zhang, Zhengxiang Wang, Yan Huang
  • Patent number: 10028054
    Abstract: An application specific integrated circuit (ASIC) is used with an acoustic device. An input clock signal is received. The frequency of the input clock signal is determined, and the frequency is indicative of one of a plurality of operational modes of the ASIC. Based upon the determined frequency, an amount current provided to one or more operational blocks of the ASIC is changed.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: July 17, 2018
    Assignee: Knowles Electronics, LLC
    Inventors: Claus Erdmann Furst, Aziz Yurttas, Svetslav Gueorguiev, Anders Mortensen
  • Patent number: 10002359
    Abstract: Briefly, an intelligent label is associated with a good, and includes one or more permanent and irreversible electrochromic indicators that are used to report the condition of that good at selected points in the movement or usage of that good. These electrochromic indicators provide immediate visual information regarding the status of the good without need to interrogate or communicate with the electronics or processor on the intelligent label. In this way, anyone in the shipping or use chain for the good, including the end user consumer, can quickly understand whether the product is meeting shipping and quality standards. If a product fails to meet shipping or quality standards, the particular point where the product failed can be quickly and easily identified, and information can be used to assure the consumer remains safe, while providing essential information for improving the shipping process.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: June 19, 2018
    Assignee: Chromera, Inc.
    Inventors: Paul Atkinson, James Kruest
  • Patent number: 10002360
    Abstract: Briefly, an intelligent label is associated with a good, and includes one or more permanent and irreversible electrochromic indicators that are used to report the condition of that good at selected points in the movement or usage of that good. These electrochromic indicators provide immediate visual information regarding the status of the good without need to interrogate or communicate with the electronics or processor on the intelligent label. In this way, anyone in the shipping or use chain for the good, including the end user consumer, can quickly understand whether the product is meeting shipping and quality standards. If a product fails to meet shipping or quality standards, the particular point where the product failed can be quickly and easily identified, and information can be used to assure the consumer remains safe, while providing essential information for improving the shipping process.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: June 19, 2018
    Assignee: Chromera, Inc.
    Inventors: Paul Atkinson, James Kruest
  • Patent number: 9996779
    Abstract: Briefly, an intelligent label is associated with a good, and includes one or more permanent and irreversible electrochromic indicators that are used to report the condition of that good at selected points in the movement or usage of that good. These electrochromic indicators provide immediate visual information regarding the status of the good without need to interrogate or communicate with the electronics or processor on the intelligent label. In this way, anyone in the shipping or use chain for the good, including the end user consumer, can quickly understand whether the product is meeting shipping and quality standards. If a product fails to meet shipping or quality standards, the particular point where the product failed can be quickly and easily identified, and information can be used to assure the consumer remains safe, while providing essential information for improving the shipping process.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: June 12, 2018
    Assignee: Chromera, Inc.
    Inventors: Paul Atkinson, James Kruest, Anoop Agrawal, John P Cronin, Lori L Adams, Juan Carlos L Tonazzi