Abstract: A controller of a switching power supply can include: a frequency-jittering control circuit configured to generate a frequency-jittering signal adaptively; a comparator having two input terminals for respectively receiving an inductor current sampling signal and a feedback control signal, and being configured to compare the signals of the two input terminals to generate a switching control signal, in order to control a power transistor in the switching power supply; and a superimposing circuit configured to superimpose the frequency-jittering signal on one of the two input terminals of the comparator, where a switching frequency of the switching power supply varies within a preset range under different load conditions.

Abstract: Low temperature coefficient capacitors are described. In an embodiment, a capacitor includes several metal-oxide-semiconductor (MOS) transistors, where each of the several MOS transistors includes a gate, a source and a drain terminal, and where the source and drain terminals of each of the several MOS transistors are connected; several switches, where each of the switches includes two terminals; where first terminals of each of the switches from the several switches are connected together; and where a second terminal of each of the switches from the several switches is connected to a gate terminal of each of the several MOS transistors.

Abstract: A frequency locked loop circuit, comprising an operational circuit, a first impedance circuit, a second impedance circuit, a switching circuit and a frequency generation circuit. The operational circuit is configured to output an operational signal according to a voltage difference between a positive terminal and a negative terminal. The switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other one of the first impedance node and the second impedance node. The frequency generation circuit is configured to periodically sample the operational signal to generate a sample signal to generate a clock signal. An operational frequency of the operational signal is an integer multiple of a sampling frequency of the frequency generation circuit.

Abstract: An oscillator circuit includes a first integrator unit to charge a first capacitor at a first integration node, a second integrator unit to charge a second capacitor at a second integration node, a chopped comparator unit and a logic unit. The chopped comparator unit includes a switching unit, a sensing comparator and a replica comparator. The switching unit is configured to couple the first integration node, the second integration node and a reference voltage VREF to the sensing comparator and the replica comparator, depending upon a phase determined by a first input clock signal C1 and a second input clock signal C2, which have opposite phases. The logic unit is configured to generate signals C1, C2, D1, D2, E1, E2 for controlling each integrator unit.

Abstract: Provided is a semiconductor integrated circuit including an oscillation circuit configured to output an oscillation signal, a heater configured to heat the oscillation circuit, a temperature sensor configured to detect a temperature of the oscillation circuit, and a nonvolatile memory configured to store temperature correction data. The oscillation circuit controls a frequency of the oscillation signal based on an output signal of the temperature sensor and the temperature correction data.

Abstract: A temperature sensor circuits includes a temperature sensing module, a current generator, a current controlled oscillator, and a counter. The temperature sensing module is sensitive to temperature changes. The current generator respectively generates a positive temperature coefficient current positively related to temperature and a negative temperature coefficient current negatively related to temperature according to the temperature sensed by the temperature induction module. The current controlled oscillator oscillates according to the positive and the negative temperature coefficient currents respectively and outputs a positive and negative temperature coefficient oscillation signals.

Abstract: A spread spectrum clock generation device that may reduce electromagnetic interference (EMI) includes: a first comparator configured to compare an input signal with a first reference voltage and output a first comparison signal; a second comparator configured to compare the input signal with a second reference voltage and output a second comparison signal; a latch configured to receive the first and second comparison signals as inputs and output an output signal; and a delaying circuit configured to generate the input signal by delaying the output signal to have a different delay time for each time interval.

Abstract: A thermally compensated circuit includes a first adjustable circuit, like an adjustable current source, to produce a first adjustable signal, such a reference current. The circuit includes a second adjustable circuit to produce a second adjustable signal, such as a reference voltage. Circuitry responsive to the first and second adjustable signals produces an output, such as a clock signal. A tunable circuit in the first adjustable circuit and a tunable first element of the second adjustable circuit set an operating characteristic, such as a clock period, of the output to a target level at a first temperature. A tunable second element of the second adjustable circuit sets the operating characteristic of the output signal at the target level at a second temperature. Tuning of the second tunable element at the second temperature does not substantially change the operating characteristic of the output signal at the first temperature.

Abstract: An oscillator equipped with a temperature compensation circuit is illustrated. Through the temperature compensation circuit, a transistor of a current mirror circuit of the oscillator which outputs a reference current to a voltage matching circuit is controlled by the temperature compensation voltage. Both of the temperature compensation voltage and a reference current decrease as the temperature rises, and a delay time of the oscillation voltage is proportional to the temperature compensation voltage and inversely proportional to the reference current. Therefore, the effects of temperature on the delay time just cancel each other out. The delay time of the oscillating voltage is related to the frequency of the clock signal. Therefore, if the delay time of the oscillating voltage is not affected by temperature, the frequency of the clock signal will not be affected by temperature.

Abstract: An oscillation circuit includes resistors with tap points for high/low reference voltages. An RC network coupled in parallel with the resistors includes a first capacitor to vary a first voltage input and a second capacitor to generate a second voltage input. A first comparator alternately compares the voltage inputs with the low reference voltage to generate oscillation outputs. A PTAT current DAC supplies an injection current to a resistor of the series of resistors that variably modulates the reference voltages. A second comparator alternately compares the voltage inputs with the high reference voltage and controls generation of an adaptive bias current to first comparator near a switching threshold voltage range thereof. A chop switch matrix alternately flips voltage reference inputs to input terminals of first comparator. A multiplexer alternately inverts a polarity of the oscillation outputs in concert with alternately flipping the voltage reference inputs by the chop switch matrix.

Abstract: In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror and an amplifier, where the amplifier is coupled to a pin of the chip. The oscillator circuit also includes a first switch coupled to the pin, a second switch coupled to the pin and to a charging resistor, and a third switch coupled to the amplifier and an internal resistor, where the internal resistor is internal to the chip. The oscillator circuit includes a bias current source coupled to the current mirror. The system includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system also includes an external capacitor coupled to the pin and coupled in parallel to the external resistor, where the external capacitor is external to the chip.

Abstract: Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.

Abstract: A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.

Abstract: An oscillator arrangement is provided, comprising a relaxation oscillator having an active state and an inactive state; a bias current circuit portion arranged to provide a bias current to the relaxation oscillator during said active state; and an electronic switch arranged to isolate said relaxation oscillator from the bias current circuit portion when in said inactive state. The oscillator arrangement is arranged to store an internal voltage value associated with said bias current and the bias current circuit portion is arranged to use the stored internal voltage value to generate the bias current when the oscillator is started up from the inactive state to the active state.

Abstract: A display device of the invention includes pixels each connected to at least one of scan lines and at least one of emission lines, a scan driver providing scan signals to the scan lines, and an emission driver including stages connected to the emission lines, each of the stages providing an emission signal to a corresponding emission line. A first stage among the stages includes a first transistor including a first electrode connected to a first power source line, a second electrode connected to a first emission line, and a gate electrode connected to a first scan line, and a second transistor including a first electrode connected to a first node and a second electrode connected to the first emission line.

Abstract: An oscillator circuit includes a total of N (N?2) class-D oscillator circuits stacked together between a supply voltage node and a reference voltage node. The output ports of adjacent class-D oscillator circuits in the disclosed oscillator circuit are coupled together by capacitors to ensure frequency and phase synchronization for the frequency signals generated by the class-D oscillator circuits. Compared with a reference oscillator circuit formed of a single class-D oscillator circuit, the oscillation amplitude of each of the class-D oscillator circuits in the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit, and the current consumption of the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit.

Abstract: A comparator circuit includes a first comparator configured to compare a voltage based on an input voltage with a first reference voltage, a charge/discharge portion configured to switch between charging and discharging of a capacitor based on an output of the first comparator, a second comparator configured to compare a voltage of the capacitor with a second reference voltage, and a control portion. The control portion is configured to, in a case where the voltage of the capacitor is larger than a predetermined value when the charge/discharge portion performs switching from the charging of the capacitor to the discharging thereof, supply a predetermined voltage instead of the voltage based on the input voltage to the first comparator until the voltage of the capacitor becomes smaller than the predetermined value so that the discharging of the capacitor is maintained by the charge/discharge portion.

Abstract: In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror, an amplifier, and an on-chip resistor, where the on-chip resistor is coupled to a pin on the chip. The oscillator circuit also includes oscillator circuitry coupled to the charging current generator, where the oscillator circuitry includes a comparator, a phase generator, a first capacitor coupled to a first resistor, and a second capacitor coupled to a second resistor. The system also includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system includes an external capacitor coupled to the pin, where the external capacitor is external to the chip.

Abstract: An embodiment provides a circuit of cyclic activation of an electronic function including a hysteresis comparator controlling the charge of a capacitive element powering the function.

Abstract: In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror and an amplifier, where the amplifier is coupled to a pin on the chip, and where the pin is adapted to be coupled to an external resistor, where the external resistor is external to the chip. The oscillator circuit also includes oscillator circuitry coupled to the charging current generator, where the oscillator circuitry includes a comparator, a phase generator, a first capacitor coupled to a first switch, and a second capacitor coupled to a second switch. The oscillator circuit includes leakage circuitry coupled to the current mirror, where the leakage circuitry is configured to draw a current from the current mirror proportional to a leakage current flowing through the external resistor from circuitry internal to the chip.

Abstract: An oscillator circuit includes a first comparator that outputs a first signal indicative of a comparison result between an input potential and a threshold, a second comparator that outputs a second signal indicative of a comparison result between an input potential and the threshold, a RS flip-flop circuit that receives the first signal and the second signal and outputs first and second oscillation signals, a first charge/discharge unit that charges and discharges a first capacitor based on the first oscillation signal, a second charge/discharge unit that charges and discharges a second capacitor based on the second oscillation signal, a first dummy switch controlled to be on and off according to the second oscillation signal and adding a predetermined capacity to a first node, and a second dummy switch controlled to be on and off according to the first oscillation signal and adding a predetermined capacity to a second node.

Abstract: A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

Abstract: The present invention provides a pressure detection circuit including an oscillator unit, configured to output an oscillation signal as a count clock signal of a counter unit; and the counter unit, connected to the oscillator unit and configured to acquire a frequency of the oscillation signal and count.

Abstract: A timing generator includes a first current source, a first switch, a second current source, a second switch, a third switch, a capacitor, a signal synthesizer, and a timing difference extractor. The first current source is for generating a first current according to the input voltage. The second current source is for generating a second current according to the input voltage. The first switch includes a control terminal for receiving a charging signal. The second switch includes a control terminal for receiving a timing difference signal. The third switch includes a control terminal for receiving a reset signal. The capacitor is coupled between a charging terminal and a ground terminal. The signal synthesizer is for generating a timing signal according to a charging voltage and a reference voltage. The timing difference extractor is for generating a timing difference signal according to the timing signal and a deformed timing signal.

Abstract: An oscillation circuit includes first and second constant current circuits, first and second switch circuits, first and second MOS transistors, and an output port. The first constant current circuit is connected to one port of a capacitor. The first MOS transistor has a gate and a drain connected to the second constant current circuit and a source connected to another port of the capacitor. The second MOS transistor has a gate connected to the gate of the first MOS transistor, and a drain connected to the one port of the capacitor. The second switch circuit is connected between a source of the second MOS transistor and a second power supply terminal. The output port outputs a signal based on a voltage of the one port. Turn-on and turn-off of the first and second switch circuits are controlled by the signal of the output port and an inverted signal.

Abstract: In an example, a system includes an amplifier configured to produce a bandgap voltage reference. The system also includes a current source configured to provide a current to bias the amplifier. The system includes a switching circuit configured to receive a first current replica signal and a second current replica signal, the switching circuit further configured to cause the current source to provide the current to bias the amplifier based on either the first current replica signal or the second current replica signal.

Abstract: A signal generator includes a first voltage generator, a second voltage generator, an operational amplifier, and an oscillator. The first voltage generator generates a first voltage, and the second voltage generator generates a second voltage. The operational amplifier generates an amplified error signal based on the first voltage and the second voltage, and the oscillator generates a periodic signal based on the amplified error signal. The first voltage generator and the second voltage generator are configured to generate their respective voltages based on the periodic signal. As a result, frequency deviation in the periodic signal may be corrected, for example, without increasing the source current of the oscillator or the gain of the operational amplifier. Also, improved phase noise performance may also be achieved through an increase in loop gain.

Abstract: The present disclosure relates to an oscillator including a charge and discharge circuit which generates a first oscillation signal according to a clock signal using a first constant current and a second oscillation signal according to an inverted clock signal using a second constant current, an integrating circuit which generates a first comparison voltage reflecting an amount of change in the first oscillation signal based on a comparison reference voltage and a second comparison voltage reflecting an amount of change in the second oscillation signal based on the comparison reference voltage, and a comparison circuit which generates the clock signal and the inverted clock signal according to a result of comparison between the first oscillation signal and the first comparison voltage and a result of comparison between the second oscillation signal and the second comparison voltage.

Abstract: A multiplier has a pair of charge reservoirs. The pair of charge reservoirs are connected in series. A first charge movement device induces charge movement to or from the pair of charge reservoirs at a same rate. A second charge movement device induces charge movement to or from one of the pair of reservoirs, the rate of charge movement programmed to one of add or remove charges at a rate proportional to the first charge movement device. The first charge movement device loads a first charge into a first of the pair of charge reservoirs during a first cycle. The first charge movement device and the second charge movement device remove charges at a proportional rate from the pair of charge reservoirs during a second cycle until the first of the pair of charge reservoirs is depleted of the first charge. The second charge reservoir thereafter holding the multiplied result.

Abstract: A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

Abstract: In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror and an amplifier, where the amplifier is coupled to a pin of the chip. The oscillator circuit also includes a first switch coupled to the pin, a second switch coupled to the pin and to a charging resistor, and a third switch coupled to the amplifier and an internal resistor, where the internal resistor is internal to the chip. The oscillator circuit includes a bias current source coupled to the current mirror. The system includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system also includes an external capacitor coupled to the pin and coupled in parallel to the external resistor, where the external capacitor is external to the chip.

Abstract: Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.

Abstract: According to the embodiments of the present disclosure, there is provided a sensor for detecting a temperature. The sensor comprises a switch circuit; a charge/discharge circuit connected to the switch circuit, and configured to be charged and discharged under control of the switch circuit; a sensing circuit connected to the charge/discharge circuit, and configured to cause a charge/discharge period of the charge/discharge circuit to change with a temperature of the sensing circuit; and an oscillation circuit connected to the switch circuit and the charge/discharge circuit, and configured to generate, under action of the charge/discharge circuit, an oscillation signal for controlling the switch circuit, wherein an oscillation frequency of the oscillation signal is dependent on the charge/discharge period and thus indicates the temperature of the sensing circuit.

Abstract: The disclosure relates to a square wave RC oscillator circuit, example embodiments of which include an oscillator circuit for generating an output square wave signal (OUT) having first and second voltage output levels (L, H), the oscillator circuit comprising: a comparator having an output and first and second inputs; a switching circuit configured to provide an oscillatory waveform at the first input of the comparator; and a feedback circuit arranged to sample the first input of the comparator each time the output square wave signal (OUT) switches between the first and second voltage output levels (L, H) and to compare this sampled voltage with first and second reference voltages (VA, VB) to adjust a voltage provided to the second input of the comparator.

Abstract: An apparatus, system, and method for connecting an auxiliary device to a model vehicle are provided. The apparatus includes an accessory port connected to an electronic speed controller and an accessory connector connected to the auxiliary device. The system further includes a battery and accessory port connected to an electronic speed controller. An accessory connector connected to the auxiliary device is designed to connect to the accessory port. The electronic speed controller provides control to the auxiliary device. The method includes providing an electronic speed controller connected to an accessory port and connecting an accessory connector to the accessory port. The accessory connector is further connected to the auxiliary device. The method further includes attaching the auxiliary device to the model vehicle and controlling the auxiliary device via the electronic speed controller.

Abstract: Provided is an oscillation circuit including: a first current source circuit; a second current source circuit; a resistor between the output terminal of the first current source circuit and a second power source; a first capacitor; a second capacitor; a first comparator circuit having a first input terminal to which is a voltage across the resistor is applied as a reference voltage and a second input terminal to which a voltage of the first capacitor is applied; a second comparator circuit having a first input terminal to which is the reference voltage is applied and a second input terminal to which a voltage of the second capacitor is applied; an RS latch; a first and a second switches switching a destination, of an current supplied from the second current source circuit, selected from the first and the second capacitors.

Abstract: A tunable oscillator includes a current bias circuit configured to generate a reference bias current, a variable voltage bias circuit configured to receive the reference bias current and generate a bias voltage varied based on a voltage control signal, an oscillation signal generator circuit configured to generate an oscillation signal based on the reference bias current and a switching control signal, and a switching control circuit configured to generate the switching control signal based on the bias voltage and the oscillation signal. A frequency of the oscillation signal is varied based on a magnitude of the bias voltage.

Abstract: A circuit for a neuron of a multi-stage compute process is disclosed. The circuit comprises a weighted charge packet (WCP) generator. The circuit may also include a voltage divider controlled by a programmable resistance component (e.g., a memristor). The WCP generator may also include a current mirror controlled via the voltage divider and arrival of an input spike signal to the neuron. WCPs may be created to represent the multiply function of a multiply accumulate processor. The WCPs may be supplied to a capacitor to accumulate and represent the accumulate function. The value of the WCP may be controlled by the length of the spike in signal times the current supplied through the current mirror. Spikes may be asynchronous. Memristive components may be electrically isolated from input spike signals so their programmed conductance is not affected. Positive and negative spikes and WCPs for accumulation may be supported.

Abstract: A frequency variable oscillator generates a clock having a frequency according to a control signal. A reference current source generates a reference current. A path selector distributes the reference current to a first path and a second path in a time-sharing manner in synchronization with the clock. An F/V conversion circuit includes a capacitor connected to the first path, and charges or discharges the capacitor with the reference current and generates a detection voltage. The reference voltage source includes a resistor connected to the second path, and outputs a reference voltage according to a voltage across the resistor. A feedback circuit adjusts a control signal so that the detection voltage approaches the reference voltage.

Abstract: An oscillator circuit comprises differential amplifiers connected in series and an auxiliary start circuit. A first output terminal and a second output terminal of each differential amplifier are respectively coupled to a first input terminal and a second input terminal of the next differential amplifier. Said first output terminal of the last differential amplifier is coupled to said second input terminal of the first differential amplifier. Said second output terminal of said last differential amplifier is coupled to said first input terminal of said first differential amplifiers. Said auxiliary start circuit generates a first disturbance signal and a second disturbance signal to said first input terminal and said second input terminal of a second differential amplifier according to said signal state of said first input terminal of a first differential amplifier. Said first different amplifier is one of said differential amplifiers. Said second differential amplifier is another differential amplifier.

Abstract: A relaxation oscillator with an aging effect reduction technique comprises a comparator (CP) coupled with its input side (CP1, CP2) to a network comprising at least one capacitor (C, C1, C2), a plurality of transistors (M1, M2, M3, M4) and a plurality of controllable switches (SW11, . . . , SW8, SW111, . . . , SW180). The relaxation oscillator uses a switching method such that the roles of current/voltage generator's transistor and current mirror transistor are periodically swapping by the output signal of the relaxation oscillator. Reducing mismatch of operating points between current/voltage generator and current minor transistors achieves a decrease of frequency degradation caused by aging effect.

Abstract: A relaxation oscillator includes an adjustable reference circuit generator to produce a reference current which is applied to a charging circuit. The charging circuit is configured to charge a capacitive node as a function of the reference current and a capacitance of an adjustable capacitor that is operably coupled to the capacitive node. A comparator having inputs operatively coupled to a reference voltage node and to the capacitive node, generates a comparator output. A control circuit alternatively enables the charging circuit to charge the capacitive node and to discharge the capacitive node in response to changes in the comparator output. Also, the control circuit outputs and oscillator output signal have an oscillator period as a function of the adjustable capacitance and the adjustable reference current.

Abstract: A multiphase clock generator includes a current mirror, a voltage controller, a pseudo-resistor circuit and a first delaying circuit. The current mirror includes a receiving terminal, a first mirroring terminal and a second mirroring terminal. The voltage controller is connected with the receiving terminal of the current mirror. A feedback terminal of the voltage controller is connected with the first mirroring terminal of the current mirror. A first terminal of the pseudo-resistor circuit is connected with the first mirroring terminal of the current mirror. A second terminal of the pseudo-resistor circuit is connected with a ground terminal. The first delaying circuit is connected with the second terminal of the pseudo-resistor circuit. An input terminal of the first delaying circuit receives a first input clock signal. An output terminal of the first delaying circuit generates a first delayed clock signal.

Abstract: Examples described herein provide for a relaxation oscillator and corresponding methods of operation. In an example, a circuit includes a dynamically controllable current source, a capacitor, and an oscillator generation circuit. The dynamically controllable current source includes a digitally tunable current mirror configured to generate a current. The digitally tunable current mirror includes multiple transistors configured to be selectively electrically connected in parallel to alter a gain of the digitally tunable current mirror to control the current. The capacitor is selectively electrically connected to the dynamically controllable current source. The oscillator generation circuit is electrically connected to the capacitor. The oscillator generation circuit is configured to generate an oscillation signal in response to a voltage of the capacitor.

Abstract: A current-controlled oscillator receives an input current. Ramp voltage generating circuitry generates first and second ramp voltages in response to the input current. Selecting circuitry selects one of the first and second ramp voltages depending on their relative values. Switching circuitry receives a selected ramp voltage, generates a signal based on the selected ramp voltage relative to a reference voltage, and outputs a clock signal. In one embodiment, a comparator receives the reference voltage, one of the first and second ramp voltages, and outputs a comparison signal. Logic circuitry controls the ramp voltage generating circuitry to output one of the ramp voltages during one half of a clock cycle and to output the other ramp voltage during another half cycle of the clock signal based on the comparison signal and logic states of the logic circuitry.

Abstract: The present disclosure relates to a low-power measuring device. In one implementation, the low-power measuring device includes a first sensor for measuring a first value, the first value being a measurement of a variable, and a counter unit for generating a first counter value indicative of a first elapsed time since the first value is measured by the first sensor. The low-power measuring device further includes at least one processor configured to send the first value to a remote apparatus, send the first counter value to the remote apparatus, cause the remote apparatus to determine the first elapsed time based on the first value and the first counter value, and cause the remote apparatus to determine a first obtained time at which the first value is measured by the first sensor based on the determined first elapsed time and a reference time of the remote apparatus.

Abstract: An oscillator is configured to generate a signal with a frequency sweep, the oscillator having circuitry comprising a set of capacitors, each capacitor of the set of capacitors being switchably connectable in parallel in the circuitry so that the frequency of the signal has an intrinsic dependence on the number of the capacitors connected, a shift register controllable by a clock line and comprising a number of bits, each bit of the number of bits controlling connection of a respective capacitor of the set of capacitors so that the capacitors are connectable or disconnectable in a pre-determined order by shifting, respectively, activation or de-activation bits into the shift register, wherein the shifting is paced by the clock line; and a clock signal generator configured to output a clock signal with a time modulation on the clock line.

Abstract: An oscillator circuit uses a comparator, and the oscillator circuit controls charge-discharge of the Miller capacitance between the gate and the drain of a MOSFET serving as an amplifier of the gain unit and the gate capacitance of the MOSFET, and enables the comparator output to follow a relatively high-frequency control signal that is input externally. The oscillator circuit uses a comparator having a differential unit and a gain unit. The oscillator circuit includes a charge-discharge control unit that connects to the output of the differential unit and is configured to control charge-discharge of the Miller capacitance between the gate and the drain of a MOSFET (N2) serving as an amplifier of the gain unit and the gate capacitance of the MOSFET, and an output control unit configured to control the output of the gain unit.

Abstract: Relaxation oscillators with delay compensation are provided herein. In certain embodiments, a relaxation oscillator includes a capacitor, a current source that outputs a charging current, and control circuitry that operates to selectively charge the capacitor with the charging current. The control circuitry includes a primary or main comparator operable to compare a charging voltage of the capacitor to a threshold voltage. The relaxation oscillator further includes delay compensation circuitry coupled to the capacitor and operable to adjust the threshold voltage to provide compensation for a delay of the control circuitry.

Abstract: A method of driving a light-source module includes adjusting a frequency of a boosting switching signal based on a dimming signal which controls luminance of a light-emitting diode (“LED”) string of the light-source module, where the LED string comprises a plurality of LEDs connected to each other in series, and controlling a main transistor in response to the boosting switching signal to transfer a driving voltage to the LED string.