Abstract: A crystal oscillation circuit that is capable of operating stably with a low power consumption includes a signal inversion amplifier and a power control circuit that controls the power voltage of this signal inversion amplifier in accordance with an oscillation output. The power control circuit includes a power voltage generation circuit that outputs a plurality of power voltages of different values; a determination control portion that determines the optimal value of the power voltage to be applied to the signal inversion amplifier, based on the oscillation output; and a multiplexer that controls the switching of the power voltage applied to the signal inversion amplifier from the power voltage generation circuit, based on the result of that determination.
Abstract: In a temperature-compensated crystal oscillator wherein a temperature-compensated crystal oscillation circuit is driven by a constant voltage generation circuit, the constant voltage generation circuit comprises a differential circuit, a dc load for supplying feedback signals to the differential circuit, a first driver for driving the dc load under control of the differential circuit, a phase-compensation capacitor coupled between a control terminal of the first driver and an output terminal thereof and a second driver for driving the temperature-compensated crystal oscillation circuit. The second driver is the same kind of device as is used for the first driver, and is under control by the same control signal as a control signal for the first driver, sent out by the differential circuit.
Abstract: A universal crystal-oscillator input/output (I/O) circuit is provided for use with an ASIC (Application Specific Integrated Circuit) device, and which can help enhance the electrostatic discharge (ESD) protection on the ASIC device in Charge Device Mode (CDM). This universal crystal-oscillator I/O circuit can help reduce the total number of I/O components in the ASIC library used to construct the IC device, allowing the design and management of ASIC library to be more simplified and convenient, making ASIC more cost-effective to implement. Moreover, this universal crystal-oscillator I/O circuit can help improve the performance of the oscillator circuit, allowing ASIC designers to have more convenience and flexibility in ASIC design. It can be fast in starting oscillation and low in power consumption.
Abstract: A low power clock oscillator circuit for driving microprocessors and other digital circuits is provided. The clock oscillator includes a resonant network for providing a sinusoidal waveform at a predetermined frequency. A first amplifier for amplifying the sinusoidal input waveform provides an output to a second amplifier. The second amplifier converts the amplified sinusoidal waveform to a continuous pulse output having a level-shifted voltage level greater than the amplitude of the sinusoidal waveform. The first amplifier is powered from a power source having a voltage level that is less than the power source that powers the second amplifier. Additionally, the second amplifier includes an enable input for disabling the continuous pulse output to permit decreased power operation with fast restart capability.
Abstract: A simple carrier recovery circuit capable of accurately detecting and synchronizing an incoming carrier frequency without the use of a phase locked loop (PLL) is provided. Instead of a PLL, the carrier recovery circuit includes an injection locked oscillator. The injection locked oscillator includes an input for connection to the received modulated signal. The gain of an inverter stage of a amplifier in the injection locked oscillator is modulated by the received modulated signal using an injection transistor connected between the power source and the output of the inverter stage. The gate of the injection transistor receives a signal corresponding to the received modulated signal.
Abstract: An oscillator circuit for preventing noise from occurring in an output clock signal. The oscillator circuit contains an amplifying unit and a control signal generator. The amplifying unit contains a first amplifying circuit having a first gain and a second amplifying circuit having a second gain connected in parallel. The amplifying unit inputs an oscillating input signal and amplifies it based on an overall gain of the amplifier unit to produce an oscillating output signal. The control signal generator inputs an input control signal and generates an output control signal, and the operational state of the first amplifying circuit is switched when a value of the output control signal switches. The overall gain is based on the first gain when the first operational state of the first amplifying circuit is an enabled state and is not based on the first gain when the operational state of the first amplifying circuit is a disabled state.
Abstract: An integrated circuit (IC) comprising an oscillator (OSC) has a first amplifier (AMP.sub.1) and a second amplifier (AMP.sub.2). The first and the second amplifier (AMP.sub.1, AMP.sub.2) each have a non-inverting input, an inverting input, and an output. The output of the first amplifier (AMP.sub.1) is connected to the non-inverting input of the first amplifier (AMP.sub.1) and also to the non-inverting input of the second amplifier (AMP.sub.2). The output of the second amplifier (AMP.sub.2) is connected to the inverting input of the first amplifier (AMP.sub.1) and also to the inverting input of the second amplifier (AMP.sub.2). The first amplifier (AMP.sub.1) is loaded with a capacitor (C) connected between the output of the first amplifier (AMP.sub.1) and an external power supply terminal (1). The second amplifier (AMP.sub.2) is loaded with a further capacitor (C.sub.F) connected between the output of the second amplifier (AMP.sub.2) and the external power supply terminal (1).
Abstract: An apparatus comprising a storage circuit, a load circuit and an oscillator circuit. The storage circuit may be configured to store a number of configuration bits configured to provide one or more control signals. The load circuit may be configured to provide a variable magnitude load in response to the one or more control signals. The oscillator circuit may be configured to provide an output signal, where the output signal has (i) a frequency determined in response to the magnitude of the load circuit and (ii) a magnitude generated in response to a current generated in response to an output of a clamp circuit.
Abstract: An oscillation circuit comprising a control circuit that utilizes the body effect of a substrate bias to control the source potential of a MOSFET that configures a signal inversion amplifier. This control circuit controls the threshold voltage of this MOSFET to be low when power is first applied to the oscillation circuit, and controls the threshold voltage of the MOSFET to be high after the oscillation of the oscillation circuit has stabilized. This makes it possible to ensure that the oscillation circuit oscillates stably and at a low power consumption.
Abstract: An oscillator having an adjustable output frequency comprises a resonator, an inverting amplifier coupled to the resonator, a variable capacitance coupled to the resonator and to the amplifier, and a shift register coupled to the variable capacitance. The variable capacitance comprises a first bank of switchable capacitors coupled to an input of the oscillator and a second bank of switchable capacitors coupled to an output of the oscillator. The shift register includes a plurality of bits and is configured such that the logic state of each bit determines the switching state of a corresponding capacitor from each bank of switchable capacitors. By shifting the bits in the shift register, the variable capacitance is varied, causing an adjustment in the output frequency of the oscillator.
Abstract: A low power oscillator having fast start-up times. The low power fast starting oscillator uses an oscillator circuit having an input and an output for generating a signal of a desired frequency. A start-up detect circuit is coupled to the output of the oscillator circuit for detecting when the oscillator circuit has reached steady state operation and for generating a start-up circuit output signal which adjusts the gain of the oscillator circuit when steady state operation has been reached by the oscillator circuit. A noise generator is coupled to the input of the oscillator circuit and to the start-up detect circuit for inputting a noise pulse into the oscillator circuit. The noise pulse is used for biasing the input of the oscillator circuit to approximately an optimal bias voltage level. The noise generator is further used for sending an enable start-up detect signal to the start-up detect circuit to activate the start-up detect circuit.
Abstract: A Voltage Controlled Oscillator (VCO) mitigates the effects of package parasitics by providing positive feedback connections, to sustain a desired oscillation, external to the IC package, thereby mitigating the effect of the bond wires and internal parasitics to allow the oscillation to be controlled by the desired external components. The VCO includes an electronic circuit with gain that is at least part of an integrated circuit (IC) and a package for the IC. A passive resonant circuit may be provided external to the IC package. The positive feedback of the electronic circuit is provided through at least one additional lead of the package, such that the connection is external to the package.
Abstract: A crystal oscillation circuit that oscillates stably with a low power consumption includes an inverting amplifier, a crystal oscillator, and a feedback circuit that inverts the phase of an output from this inverting amplifier and feeds it back as an input. The inverting amplifying includes first and second semiconductor switching elements. The sum of the absolute value of the threshold voltage of the first semiconductor switching element and the absolute value of the threshold voltage of the second semiconductor switching element is set to be greater than or equal to the absolute value of the potential difference between first and second potentials, in order to prevent the first and second semiconductor switching elements from being on simultaneously.
Abstract: A controllable reactance implemented within an integrated circuit includes a first sub-circuit (20) comprising a reactive element, for example a capacitor 12, coupled in series with a transistor (14). A controllable current source (16) injects a controllable bias current through the transistor (14) to vary the effective resistance of the transistor (14) and hence the effective complex impedance of the capacitor combination. A second transistor (18) amplifies the current to increase the effective capacitance. Preferably, a second sub-circuit (24) includes corresponding components (26, 28, 30) to mirror the real component of the current flowing in the first sub-circuit (20), and transistors (32 and 34) to reflect an inverse current to the coupling node line (22) to cancel the real component of the current at the node, to thus simulate a purely capacitive circuit. An oscillator embodying this circuit is also disclosed.
Abstract: There is disclosed an oscillator circuit comprising the first load capacitor with one electrode there of being connected with an input side of a CMOS inverter within a quartz oscillator circuit, and the second load capacitor with one electrode there of being connected with the output side of the inverter, wherein the inverter is coupled to a lower potential side via a current-limiting device, and the other electrodes of the first and second load capacitors are coupled to a lower potential side via the above-described current-limiting device. Thus, variations in the power-supply voltages synchronized with oscillation are reduced with realization of lower current consumption.
Abstract: A temperature compensated crystal oscillation circuit adapted to be contained within a small device package and providing an output frequency accuracy of approximately +/-2 ppm over a temperature range or less than 2 minutes per year over the temperature range. The device includes a crystal and a single integrated circuit wherein the integrated circuit has a temperature sensing circuit with a digital output, control circuitry, a memory circuit and a switched capacitor array for compensating the oscillation of the crystal oscillator over temperature.
March 23, 1998
Date of Patent:
November 30, 1999
Dallas Semiconductor Corporation
Douglas Gene Cole, Ranganath Bagade, Titkwan Hui
Abstract: An integrated circuit configuration for producing a clock signal includes an integrated inverter connected between an input terminal and an output terminal. A crystal is externally connected to the oscillator circuit. A feedback path of the inverter contains a phase-shifting element which effects a phase shift through 180.degree., so that conditions for oscillation continue to be provided if the crystal breaks.
Abstract: A fast start-up oscillator has an oscillator for generating a signal having a desired frequency. A prestress biasing circuit is coupled to the oscillator. The prestress biasing circuit is used for prestressing a piezoelectric resonator of the oscillator and for placing a bias voltage on the oscillator after the piezoelectric resonator of the oscillator has been prestressed.
Abstract: In a high current, high frequency integrated circuit chip characteristic of producing an excess of internal on-chip circuit induced noise with respect to a low current, low frequency circuit implemented on the high current, high frequency integrated circuit chip, a method is disclosed for reducing noise in the low current, low frequency circuit. The method includes placing noise sensitive components of the low current, low frequency circuit external to the integrated circuit chip, corresponding to an off-chip placement. An exclusive power supply reference line V.sub.(REF) tapped off of a power supply bus internal to the integrated circuit chip is provided. The exclusive power supply reference line V.sub.(REF) is tapped off the internal power supply bus on-chip at a physical location proximate the low current, low frequency circuit and routed off-chip. The noise sensitive components are connected between the low current, low frequency circuit and the power supply reference line V.sub.
Abstract: An oscillating circuit includes a low power inverting amplifier (10) having an input (208) and an output (209) and having a relatively high resistance d.c. biasing path (2) associated therewith. A relatively low resistance path (3) can be switched so as to couple the amplifier input (208) and output (209) together during a bias settling phase of the circuit. A detector (50) detects the voltage at either the amplifier input (208) or the output (209) and switches the relatively low resistance path (3) so that it does not couple the input (208) and output (209) together when the detected voltage reaches a level just before a required operating voltage level.
Abstract: A clock signal generating circuit of the present invention switches the threshold value of a buffer circuit included in an output buffer section substantially when the oscillation output of an oscillating section is stabilized, thereby generating a clock signal. The clock signal plays the role of a clock signal for a stabilization detecting circuit at the same time. Therefore, once the oscillation is stabilized, clock components other than a clock signal whose duty cycle is 50% and which would bring about noise are obviated. This allows the clock signal output from the clock signal generating circuit to remain stable.
Abstract: A CMOS oscillator includes two differential input transistors (150) and (152) which have the sources thereof coupled through a resonator element (196). Active loads (166) and (178) provide a squaring up of the output which then drives an output transistor (202). The gates of the differential input transistors (150) and (152) are biased to predetermined voltage levels with bias circuits, with the positive input of the comparator configuration coupled through a feedback capacitor (208) to the output (204). This provides sufficient instability to initiate oscillation with a gain of the device controlled by resonator circuit (196) to be optoimum at the resonant frequency of the resonator circuit.
Abstract: A crystal-stabilized integrated-circuit oscillator which uses a filtered analog coupling to automatically disable the bias current to an auxiliary gain after startup. Positive feedback is used to ensure that the switchover is completed once it starts. Thus the device sizes and biases of the primary gain stage can be selected for very low-power operation, while assuring that the oscillator will always start-up whenever poser is valid.
Abstract: An oscillator circuit, having an inverter with input and output terminals interconnected through a feedback resistance, operates in two modes. In a first mode, the input and output terminals are coupled to an external crystal resonator. In a second mode, an external clock signal is supplied to the input terminal. In the second mode, the input terminal is disconnected from the output terminal, and in addition, the output-drive capacity of the inverter is reduced, or the output terminal of the inverter is held at a fixed potential.
Abstract: A control circuit includes: a temperature 30; a temperature sensing section 32; a memory 36, an amplifying section 31 to which the memory and the temperature sensor are electrically connected; a first D/A converting section 38 electrically interposed between the memory and the temperature sensing section; a second D/A converting section electrically interposed between the memory and the amplifying section 31, The amplifying section 31 includes: a polarity inverting circuit 33 connected to the temperature sensor; and a variable attenuator 34, an offset adjusting circuit 100, and an amplifying circuit 35 that are connected sequentially to the polarity inverting circuit. The amplifying section 31 is connected to a sample hold circuit 41 through a displacement buffering means 101. The memory has 8 or less working control voltage setting groups.
November 5, 1997
Date of Patent:
February 23, 1999
Matsushita Electric Industrial Co., Ltd.
Abstract: An electronic device (1) has a substrate (2) of monocrystalline silicon on which is an integrated circuit (3). The integrated circuit is an oscillator containing a resonator, a maintenance circuit to cause the vibration of the resonator, and a frequency division chain. The maintenance circuit as well as the division chain are manufactured as CMOS circuits. The resonator is an integrated resonator (4) formed of a body cut out in a delimited surface part of reduced thickness (14) of the substrate (2), of a thin layer of piezoelectric material (10) deposited on at least a part (6) of the body, and of a thin metallic layer (11) deposited on the piezoelectric layer (10) so as to form an electrode.
Abstract: An oscillator in which the transconductance of an amplification transistor (T0) is limited through a measurement of the potential at the input electrode (G0) of the amplification transistor (T0) by means of a differential pair (T1, T2) for safeguarding the starting of the oscillator.
Abstract: An oscillator provided with an amplitude controller (AMPREG1) which is coupled by an input (G1) to an amplitude reference terminal (AMPREF1). The amplitude of the oscillator signal at the output terminal (KU) can be adjusted through coupling of a voltage-generating means to the amplitude reference terminal (AMPREF1).
Abstract: The invention relates to a digitally adjustable crystal oscillator having a quartz crystal and a monolithic integrated oscillator circuit including a series combination of a first frequency-adjusting capacitor C1 and a second frequency-adjusting capacitor C2 connected in parallel with the quartz crystal and comprising parallel-connected first capacitance stages and parallel-connected second capacitance stages, respectively, and an inverter circuit connected in parallel with the quartz crystal and comprising a feedback resistor R.sub.K, the output of the innverter circuit being connected to a load resistor. The inverter circuit comprises parallel-connected inverter stages, and switching elements are provided within the inverter stages and cqapacitor stages in such a way that a respective one of the inverter stages as well as a first capacitance stage C.sub.1i and a second capacitance stage C.sub.2i are switchable into or out of circuit by means of a control signal I.sub.i.
Abstract: Crystal oscillator circuitry provides a very fast start-up function requiring less than 100 mS. The crystal oscillator circuitry enters a stop mode when a control signal transitions from a first logic level to a second logic level thereby causing a crystal to stop oscillating. In order to initiate the fast start-up function, a pulse is provided to the gate of a transistor which is electrically connected between a first node and a second node, thus causing the voltage of the first node to move towards the voltage level of the second node and the second node to move towards the voltage level of the first node. Upon initiation of the start-up function, the energy at the crystal of the crystal oscillator circuitry is at least four times higher than the energy required in a steady state mode. The crystal oscillator circuitry has a VT (threshold voltage) independent high feedback resistance which provides stable oscillation frequency over a wide range of Vcc supply voltage.
Abstract: A crystal-controlled oscillator circuit is modified by the present invention by replacing the crystal with the first signal port of a two-port SAW resonator filter that has a low-loss primarily inductive characteristic and taking the oscillation output from the other port of the filter to provide an oscillator frequency with harmonics that are reduced significantly when compared to the output of a crystal-controlled oscillator.
Abstract: A power-saving IC-type oscillation circuit is disclosed. It contains (a) a quartz oscillator circuit which contains an inverter and a feedback circuit: and (b) an output modulation circuit connected to an output terminal of the quartz oscillator circuit. The output modulation circuit is structured such that, after a sinusoidal wave is received from the output terminal, it will judge the level of the sinusoidal wave in a manner that when the level is high, a high state signal will be sent out to a CMOS transistor, and, when the level is low, a low state signal will be sent out. The output modulation circuit allows the CMOS transistor, which is to be driven by the oscillation circuit, to quickly move out of the power-consuming condition to thus reduce electrical current consumption.
Abstract: A low power, fast starting oscillator (10) of the Colpitts type includes an amplifier (12) that provides voltage gain and feeds a source follower circuit (14) that provides a desirable output impedance. A crystal (16) is coupled from an output of the source follower circuit (14) back to the amplifier's input (32). The voltage gain of the amplifier (12) and the output impedance of the source follower circuit (14) are independently selectable to provide an optimum transconductance for the oscillator (10) to start quickly. When oscillations reach a threshold value, the transconductance may be reduced to save power.
December 23, 1996
Date of Patent:
June 23, 1998
Raymond Louis Barrett, Jr., John Wayne Simmons, Barry Herold, Grazyna A. Pajunen
Abstract: The present invention provides for a voltage-controlled crystal oscillator (VCXO) which, other than the crystal itself, is full integrated. The VCXO has a pre-amplifier block, a gain stage, a first MOS transistor, a first capacitor, a second MOS transistor, and a one second capacitor. The pre-amplifier block receives an input tuning voltage and the gain stage is connected across the terminals of the oscillating crystal. The first MOS transistor and first capacitor are connected between one of the terminals of the oscillating crystal and a reference voltage. The second MOS transistor and the second capacitor are connected between the second crystal terminal and the reference voltage. The gates of both MOS transistors are connected to the output node of the pre-amplifier block. The first and second MOS transistors connect the first and second capacitors to the first and second terminals of the gain stage for a portion of the time responsive to the input tuning voltage.
Abstract: A low power consumption oscillator circuit is provided with an oscillator. The oscillator responds to a voltage by producing an oscillating signal at its output having an amplitude that depends on the level of the voltage. Furthermore, the low power consumption oscillator circuit has a level shifter. Illustratively, according to one embodiment, the level shifter includes a pull-up driver and a pull-down driver connected in parallel between the oscillator output and an output of the level shifter. The pull-up driver is configured so as to refrain from conducting current between a biasing input of the pull-up driver and the level shifter output simultaneously with the pull-down driver when the oscillating signal exceeds a certain voltage level. The level shifter illustratively includes an intrinsic PMOS device.
December 9, 1996
Date of Patent:
May 26, 1998
Industrial Technology Research Institute
Abstract: A multiple-frequency local oscillator for providing an LO signal at one of a multiple of predetermined resonant frequencies associated with a number of resonators is disclosed. It includes a number of LO input ports for coupling to a plurality of resonators, respectively, each resonator having a predetermined resonant frequency; the local oscillator is controlled to selectively provide at its LO output port an output LO signal at any one of the resonant frequencies.
November 23, 1994
Date of Patent:
May 5, 1998
John Thomas Bayruns, Raymond Mitchell Waugh, Phillip W. Wallace, Robert J. Bayruns, Thomas D. DeNigris
Abstract: A voltage-controlled oscillator is provided having a semiconductor integrated circuit and a piezoelectric resonator. A variable-capacitance diode may be connected in series with the piezoelectric resonator. The variable-capacitance diode may be further mounted a land of a lead frame. The piezoelectric resonator, variable-capacitance diode and lead frame may be resin molded into a single unit. In operation, a signal may be applied to a node located between the variable-capacitance diode and the DC-cutting capacitor.
Abstract: An apparatus and a method are provided to obtain oscillations from a crystal at a particular frequency by introducing real and imaginary components of voltage to the crystal. The imaginary component of voltage is different from the real component of voltage by a particular phase angle such as 90.degree.. The voltage introduced to the crystal is processed to produce a first current having characteristics corresponding to such voltage and to produce a second current having characteristics related to the imaginary component of such voltage. The first and second currents are combined to produce a first current corresponding to the real component of the voltage introduced to the crystal. This current is shifted through a phase angle of 90.degree. to produce a second current corresponding to the imaginary component of the voltage introduced to the crystal. The first current is converted to a first voltage which is regulated to provide a particular gain.
Abstract: A CMOS inverter capable of reducing a through current therein including an E-type PMOS transistor, an E-type NMOS transistor and a D-type NMOS transistor. In the E-type PMOS transistor, the gate and the drain are connected to input and output terminals. In the E-type NMOS transistor, the gate and the drain are connected to the input and the output terminals and the source to the ground. In the D-type NMOS transistor, the source is connected to the source of the E-type PMOS transistor, the gate to the ground, and the drain to a power source.
Abstract: A semiconductor integrated circuit has a constant voltage generation circuit and an oscillation circuit for generating a clock signal. The constant voltage generation circuit supplies a first voltage to the oscillation circuit until the clock signal is stabilized and the constant voltage generation circuit supplies a second voltage lower than the first voltage to the oscillation circuit after the clock signal has been stabilized.
Abstract: A switching oscillator constituted by two inverters is provided with a system of current mirrors each arranged to provide a small proportion of load current from the load of one transistor to the load circuit of the other such as to drive the load currents into equilibrium.
Abstract: A single pin integrated oscillator circuit includes an amplifier having a first input terminal to which an external crystal may be connected, and a second input terminal which receives a feedback path from an output terminal of the amplifier. An oscillator output signal having a relatively large voltage swing is provided from the first input terminal through a buffer. The oscillator operates over a wide range of voltages and process variations, and it can accept an input signal from an external crystal or can accept any clock signal having a swing of approximately 1 V.
Abstract: In a digital temperature compensated crystal oscillator, ADC circuit and DAC circuit are combined into a data conversion circuit which comprises a first section for DA conversion, a second section for converting an analog temperature voltage signal into a digital form in cooperation with the first section, and a third section for supplementing the DA conversion of the first section and thereby generating an analog control voltage for a VCO from a digital temperature compensation data. There is further provided a switch circuit for connecting the output of the first section to either of the second and third section.
Abstract: A one-pin integrated crystal oscillator in a Colpitts configuration employs a differential amplifier, provided with a feedback network, as an input gain stage. This achieves an enhanced stability and independence from temperature variation, a high Q figure, and a short start-up with a relatively small area of integration.
Abstract: A CMOS delay cell with feedback circuitry to ensure that the delay cell is operating in saturation mode. A voltage controlled oscillator (VCO) comprising a loop of an odd number of delay cells, where the VCO is operating in a saturation mode. Under normal operation any intermediate node in the VCO will generate an output signal from a delay cell with reduced supply noise. The output signal can be used to generate a PLL clock signal with a lower phase jitter than prior art VCO's operating at low supply potentials.
Abstract: An inverter is connected between the control nodes of two transistors in a current mirror system which forms a closed current feedback loop. Any difference between the bias voltages at the input and output of the inverter is reduced to zero. The self-biasing inverter amplifier may comprise the active part of an oscillator but may also be used as a level shifter or a reference circuit.
Abstract: A one pin on-chip crystal oscillator circuit and a method of operating that oscillator are provided. The oscillator makes use of the gate-source capacitance of a MOS transistor to provide capacitance which would otherwise need to be provided by one of two oscillator capacitors. The MOS transistor is provided with a floating well by coupling its body to its source, so that the gate-source capacitance does not change substantially when the transistor is turned off. In another aspect of the invention, the MOS transistor is provided with a floating well using a parallel combination of MOS transistor elements, so as to minimize the coupling resistance of the MOS transistor to other elements of the circuit.
Abstract: The output frequency (14) of an oscillator circuit (10) can be controlled by replacing at least one of the reactive components (40), such as a capacitor or inductor, with a synthesized element (22). The synthesized element creates a signal that corresponds to the response of the reactive component it is replacing. The synthesized element may be a current source (44), such as a field effect transistor, that is capable of operating at low voltages.
Abstract: A power efficient class A-B amplifier provides 20 dB amplification for a low capacitive load such as a 40 to 80 MHz clock signal in a crystal oscillator circuit. The amplifier includes two bias-and-clamp circuits coupled between an input stage and the gates of an N-channel transistor and a P-channel transistor. The N-channel and P-channel transistors are connected in series between VCC and ground and form an output stage. The bias-and-clamp circuits bias the N-channel and P-channel transistors in weak inversion for maximum amplification and clamp an input voltage to increase noise immunity and reduce power use. In one embodiment, each bias-and-clamp circuit includes two pairs of series connected transistors. A first pair is connected in series with a constant current source and form current mirrors with a second pair of transistors. A node between transistors in the second pair is connected to the gate of a transistor in the output stage and to the input voltage.
Abstract: A differential delay stage for a ring oscillator utilizes a resonant circuit formed by an inductor and a capacitor consisting of two varactor diodes connected back-to-back. A common cathode connection is connected to a variable voltage source to vary the capacitance of the diodes. Other forms of capacitors may replace the varactor diodes. Varying the capacitance value varies the resulting oscillation frequency of the ring oscillator. When several delay stages, each incorporating the resonant circuit, are connected together in a ring, the net effect is to allow only a signal at the resonant frequency of the resonant circuits to propagate around the ring. Other oscillator circuits employing a resonant circuit are disclosed.