Abstract: A vibrating type transducer wherein an H-shaped vibrator, formed integrally with a silicon substrate and having a hollow chamber provided therearound, is kept self oscillating at its natural resonance frequency together with an amplifier. A physical quantity, such as force, pressure, differential pressure, or the like, which is applied to the silicon substrate is detected by a change in the natural frequency arising at the vibrator corresponding to the physical quantity. The invention also includes a method for manufacturing such transducer using a semiconductor technique, including steps for keeping a vacuum internally in the hollow chamber, imparting an initial tension to the vibrator, and then operating the amplifier to have stable self oscillation.

Abstract: An oscillator including a CMOS inverter, a feedback reactance connected between the input and output terminals of the CMOS inverter and a CMOS transfer gate connected as a feedback resistor between the input and output terminals of the CMOS inverter, a power source terminal section to which an external voltage is applied, and a power control unit for converting the external voltage to a first internal voltage which is supplied as a power source voltage to the CMOS inverter. The power control unit converts the external voltage to a second internal voltage independently from the first internal voltage and supplies the second internal voltage as a gate control voltage to the CMOS transfer gate.

Abstract: A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during start-up.

Abstract: A dual bandwidth crystal controlled oscillator is described having a first transconductance amplifier providing sufficient gain to maintain oscillation with an oscillator crystal at a minimum current drain. A second transconductance amplifier is provided which can be selectively coupled to the first transconductance amplifier, thereby augmenting the gain of the first transconductance amplifier to provide the capability for rapid oscillator start-up following battery saver operation. The dual bandwidth crystal controlled oscillator can be utilized in conventional oscillator and frequency synthesizer applications.

Abstract: Maximum frequency range in a VLSI voltage controllable crystal oscillator is obtained with a two-stage amplifier with feedback across both stages. The first stage is implemented by an MOS transistor connected in source-follower configuration to minimize input capacitance, and the second stage is implemented by a bipolar transistor to provide the needed gain. A bidirectional voltage limiter connected to a crystal node limits the oscillations to a symmetrical waveform. The bias of an output buffer amplifier may be selectively shifted to maintain optimum duty cycle with the different triggering levels of diverse logic driven by the oscillator, and the bias may be dynamically driven by an analog signal to provide a duty cycle-modulated output.

Abstract: A reflection oscillator is provided which employs an active device operated in its roll-off region and two resonant circuits. For an oscillator employing a bipolar transistor, the emitter is connected to a series resonant capacitor-crystal network and the base is connected to an L-C tank circuit with the transistor being operated in the roll-off region of its gain versus frequency curve. This will provide a very high frequency of operation with a relatively inexpensive, low frequency, active device. These oscillators are easily tuned, stable, and require little d.c. power.

Abstract: A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during start-up.

Abstract: An oscillator has an oscillating circuit including a NOT circuit having first and second inputs and one output and is placed into an operable condition in response to a trigger signal applied to the first input of the NOT circuit. A frequency determining circuit is connected between the second input and the output of the NOT circuit so that the output of the NOT circuit generates an oscillation signal of a frequency which is determined by the frequency determining circuit. A comparator has a threshold level which is different from that of the NOT circuit and is connected to the output of the NOT circuit so as to generate a control signal when the oscillation signal exceeds the threshold of the comparator. Further, an output circuit is connected to the outputs of the oscillating circuit and the comparator for receiving the trigger signal for outputting the oscillating signal after the trigger signal is received and the control signal is generated.

Abstract: A field-effect transistor performs four functions, namely signal demodulation, generation of a local oscillator signal, generation of harmonics of this local oscillator signal through frequency multiplication, and mixing of the demodulated signal with either the local oscillator signal or one of its harmonics to produce a signal at a lower intermediate frequency; the field-effect transistor being the key element in a demodulator-downconversion circuit.

Abstract: A crystal oscillator comprising a crsytal and an inverter amplifier which utilizes a current mirror to provide a voltage output having a frequency double the frequency of the voltage waveform present in the inverter amplifier.

Abstract: A crystal oscillator circuit having an accurate duty cycle at very high frequency is provided. An oscillator stage is provided which receives regenerative feedback from an inverter to sustain oscillation. The oscillator stage provides an AC output signal having a first average DC value determined by the regenerative feedback. The AC signal is coupled to a clipping circuit which symmetrically clips the AC signal about a predetermined second average DC level at first and second predetermined voltage levels. The inverter receives the clipped signal and provides an oscillating clock signal with an accurate duty cycle in response thereto.

Abstract: A fully integrated, adjustable oscillator circuit for use with a crystal is disclosed in which a crystal oscillator, such as a Pierce oscillator, is arranged to utilize a tuning network that includes at least one integrated varactor (voltage-variable-capacitor) as a shunt element for providing at least one type of adjustment of the oscillating signal. More than one type of adjustment can be provided by including a bank of varactors for each of the shunt elements of the tuning network, in which various individual varactors are selected in binary (on-off) fashion to effect digital as well as analog adjustment of the crystal oscillator.

Abstract: A trimmable semiconductor device includes a plurality of capacitors or resistors, each of which has a predetermined value, and a plurality of programmable switches each of which is operatively associated with the corresponding one of the plurality of capacitors or resistors. All of the capacitors or resistors and the programmable switches are fabricated internally and thus on the same chip or substrate. Thus, when the plurality of programmable switches are selectively programmed, the corresponding ones of the plurality of capacitors or resistors are selected and thus connected to a circuit formed on the substrate, thereby carrying out required adjustments electrically.

Abstract: A dual FET oscillator includes a first J-FET and a second J-FET connected to it as a source follower. A turned circuit is connected to the gate of the first J-FET and to the second J-FET. Bias voltage is supplied to both J-FET's. Schottky diodes are connected to both J-FET's to limit gate-source voltage.

Abstract: A constant voltage circuit comprises a capacitor connected between one end of a MOS transistor controlled by an operation-stop control signal and an output terminal of an inverter for inverting the operation-stop control signal. When, in the circuit having this arrangement, the transistor for operation-stop control is turned off and the hold mode is ended, the potential at one end of the transistor is quickly lowered to the ground potential. The result is to quicken the start of operation of the constant voltage circuit and hence the rise of the constant voltage output.

Abstract: For producing a pulse train consisting of pulses each having a constant pulse height, there is provided a pulse generating circuit comprises an oscillation circuit having an amplification stage and operative to produce a raw pulse train consisting of pulses including pulses with insufficient pulse heights, and an elimination circuit having a pulse height monitoring circuit operative to produce a dummy voltage level, a flip-flop circuit operative to produce an activating signal under the application of the dummy voltage level higher than a threshold voltage thereof and a logic gate operative to produce the pulse train based on the raw pulse train in the presence of the activating signal, the pulse height monitoring circuit is provided with field-effect transistors identical in characteristics with corresponding component field-effect transistors forming part of the amplification stage, then the eliminating circuit can eliminate pulses with insufficient pulse heights even if the voltage source is decreased in v

Abstract: A digitally temperature compensated oscillator (TCO) system is provided which is capable of ascertaining and memorizing in an EEPROM-based look-up table, appropriate digital values of a temperature-compensating tuning voltage to the TCO during calibration. An on-board temperature sensing mechanism tracks variations in temperature in the TCO and produces an analog voltage value corresponding to the instantaneous temperature. The voltage value of the sensor output is digitized and designated to constitute an address into the EEPROM based look-up table. As the temperature changes, the digitized output of the temperature sensor and hence the address to the EEPROM changes accordingly.

Abstract: A CMOS data clock oscillator circuit is disclosed which provides a simple, inexpensive, high-specification oscillator with an accurate duty cycle. The data clock oscillator 100 includes an oscillator stage 121 providing an AC output signal having an average DC value determined by an applied bias voltage, a limiting stage 124 having MOSFETs 102 and 103 configured to form a back-to-back limiter network to limit the amplitude of the AC output signal, a CMOS biasing stage 122 including complementary MOSFETs 104 and 105 configured to form an active resistor voltage divider network providing the bias voltage for the oscillator stage, and a CMOS buffer stage 123 including complementary MOSFETs 106 and 107 configured to form an inverting amplifier network having a predefined input switching threshold. Buffer stage MOSFETs 106 and 107 have conduction types, geometries, and device parameters matched to those of bias stage MOSFETs 104 and 105, respectively.

Abstract: An overtone crystal oscillator includes a crystal vibrator, a CMOS circuit connected in parallel to the crystal vibrator, and two load capacitors connected to the input and output of the CMOS circuit, respectively. The capacitors have respective capacitances C.sub.g and C.sub.d determined to satisfy at least one of following two conditions wherein the first condition is that an oscillation starting resistance R.sub.KN of a desired N-th overtone is sufficiently larger than an effective resistance R.sub.QN of the crystal vibrator of the N-th overtone, the oscillation starting resistance being expressed as:R.sub.KN =K/(.omega..sup.2 .multidot.C.sub.g .multidot.C.sub.d)(.omega.: oscillating frequency, K: constant determined by mutual conductance of the CMOS circuit) and the second condition is that an effective resistance R.sub.Qn of the crystal vibrator of another n-th overtone except the desired N-th overtone satisfies the following relationR.sub.Qn >N.sup.2 .multidot.R.sub.KN /n.sup.2.

Abstract: The present invention provides a circuit which facilitates fast and reliable start-up of an oscillator crystal without the amplification of undesirable frequencies of noise. A crystal is provided which is connected in parallel to an amplifying inverter having an input and an output. Grounded capacitors are connected respectively to the input and output of the inverter for stability. A first high resistance feedback path and a second low resistance feedback path are provided between the output of the inverter and the input of the inverter. A switch is also provided for selectively engaging or disengaging the low resistance feedback path with the inverter at preselected points in time. During operation of the circuit in the preferred manner, the switch engages the low resistance feedback path with the inverter to allow maximum charge build-up at the stabilizing capacitors upon turn-on of a supply voltage, thus quickly generating a large input voltage at the inverter.

Abstract: An oscillator circuit in a semiconductor substrate of an integrated circuit, includes a gain correction circuit portion connected between the output terminal of the feedback circuit portion and the input end of the amplifier circuit portion composed of MOS transistors. The gain correction circuit portion suppresses the excessive amplitude of the output signal of the feedback circuit portion, so that the characteristic of the waveform of the output signal of the oscillator device is improved.

Abstract: A CMOS crystal controlled oscillator includes a CMOS inverter composed of series connected MOS FETs and a crystal connected between signal input an output nodes of the inverter. First and second capacitors are respectively connected between the signal input and output nodes of the inverter and a feedback resistor is connected between the signal input and output nodes of the inverter. A first current limiting circuit is connected between a MOS FET of the inverter and a power source potential and a second limiting circuit is connected between another MOS FET of the inverter and a ground potential. A control register is provided for controlling the first and second current limiting circuits based on data contained within an internal data bus.

Abstract: A method and means for reducing noise in a GaAs FET oscillator circuit is described. The circuit of the present invention achieves low noise oscillator operation by driving the gate input of the GaAs FET oscillator circuit with a source of voltage which exhibits a low impedance at baseband frequencies and driving the drain input with a source of current which exhibits a high impedance at said frequencies. The present invention further operates to control the D.C. voltage present on the drain terminal of the GaAs FET device regardless of the drain current, while simultaneously maintaining a constant D.C. drain current at some predetermined value which corresponds to optimum low-noise operation.

Abstract: A reference pulse generator comprises a quartz crystal oscillator, a frequency divider connected to the oscillator for frequency dividing the oscillator output, and a constant current generator connected in series both with the oscillator and the frequency divider to control the current applied to the oscillator from a power source. The constant current generator comprises a current limiting element, such as a MOSFET, which is controlled by a reference voltage produced by a reference voltage generator.

Abstract: An oscillator circuit operable in different modes. The oscillator circuit, when operated as a crystal oscillator, is initially operated as a standard inverter oscillator requiring a low start-up voltage. Once the circuit oscillates, an hysteresis feedback network is inserted in the amplifying section of the oscillator providing a clock signal with sharper leading and falling edges. The circuit thus enables the start up of the oscillator at low voltages and ensures greater noise immunity following start-up. The oscillator circuit, when operated as an RC oscillator, may be operated as a Schmitt-trigger oscillator as soon as the oscillator is turned-on.

Abstract: A one-pin crystal oscillator 20 is designed to be used as a clock generator for digital integrated circuits. Unlike the prior art, this oscillator requires only one package pin to connect the crystal as opposed to the usual two pin requirement and, except for the crystal, can be completely fabricated on a chip so as to require no other external components.

Abstract: We disclose and claim a novel high efficiency oscillator circuit and method of operation wherein output signal distortion is minimized by applying the weighted sum of currents flowing in an input complementary transistor pair to each transistor in an output complementary pair. This operation is accomplished using a novel summing current mirror stage to interconnect the input and output complementary pairs, and the channel width-to-length, W/L, ratios of transistors in the mirror stage sets the value of the weighted sum of currents applied to the complementary pair output stage.

Abstract: A circuit configuration is provided for reducing noise sidebands in the output of an oscillator due to modulation of the oscillation signal by characteristic noise produced by the amplifying element. A gallium arsenide field-effect transistor that produces characteristic noise is operated as a linear amplifier. Positive feedback to the input of the amplifier is provided by a resonator. The amplitude of the oscillation signal is limited by a distinct limiting circuit in the feedback loop, the input to which is isolated from the amplifier by a high pass filter, thereby divorcing the non-linear limiting function of the oscillator from the amplifying function where noise is generated.

Abstract: A high frequency oscillator circuit is provided using a low cost junction type field effect transistor (T.sub.1) with a tuned circuit connected to its gate. The frequency of operation is determined by the tuned circuit and the capacitance reflected from the source to the gate. The transistor is matched to the frequency of operation so that this frequency falls within the roll-off portion of the transistor's transconductance verses frequency curve, preferably somewhat above the 3 db point in frequency. Phase shifting necessary to sustain oscillation occurs due to the operation of the transistor in the roll-off portion of the curve and the addition of a phase shifting network (R.sub.1, C.sub.1) at the source. The resulting oscillator is small, stable, linear and inexpensive.

Abstract: An FET oscillator wherein a bias circuit is connected to a drain of a field-effect transistor and a source circuit including a transmission line and a self-bias circuit is connected to a source of the transistor, so that the source is substantially open-circuited at an oscillation frequency and the field-effect transistor operates as a two-terminal (the gate and drain) element exhibiting a negative resistance, and wherein a resonant circuit is connected to the gate of the transistor. With the source circuit connected to the transistor source, the oscillator can have a high unloaded Q-value of Qo and a high externally-loaded Q-value of Q.sub.ext, whereby the oscillation frequency is stable. According to this oscillator, only a single bias circuit for the drain is required without the need of a bias circuit for the gate.

Abstract: An MOS crystal controlled oscillator circuit is provided which includes a pair of MOS transistors coupled together in complementary fashion to form a first non-inverting stage. The output of the first non-inverting stage is coupled to the input of a second non-inverting stage including a MOS transistor exhibiting a source follower configuration or a bipolar transistor exhibiting an emitter follower configuration. The output of the second non-inverting source follower stage is coupled via a feedback element, for example, a piezoelectric crystal, to the input of the first non-inverting stage. A feedback loop is thus formed which causes the circuit to resonate at a frequency determined by the piezoelectric crystal feedback device. This oscillator configuration results in a degree of insensitivity to variations in parasitic impedance of the piezoelectric crystal feedback device.

Abstract: A highly stable voltage variable crystal controlled oscillator adapted for stand-alone use or for use with an atomic clock for further stabilizing the oscillator. A novel Colpitts crystal oscillator configuration is employed and utilizes an FET amplifier and bipolar emitter follower configured for power gain without phase shift in the feedback circuit. The oscillator output signal is derived through the crystal which then acts as its own low pass filter to improve the purity of the output signal. A novel buffer/amplifier circuit including a grounded gate FET amplifier and coupling transformer assure frequency stability despite wide ranging load impedance variations. A resilient thermal foam material is used to enclose the temperature and shock sensitive components of the oscillator to provide further frequency stability and rugged construction.

Abstract: An integrated circuit for a controllable frequency oscillator using integrated variable-capacitance capacitors.The circuit is a MOS type. Each of the variable capacitance capacitors comprises a n.sup.+ -p junction at the interface of a first region of n.sup.+ conductivity type and a second region of p conductivity type, which are formed in a semiconductor substrate of n type. The first and second regions emerge at the surface of the semiconductor wafer. A decoupling capacitor is associated with the variable-capacitance capacitor by the formation of a stack arrangement comprising the portion of insulating oxide layer covering the surface portion of the wafer at which said first region emerges and an electrically conducting layer covering said insulating layer portion.

Abstract: A low current electronic oscillator system includes an oscillator tuning element, such as a piezoelectric crystal, operable at a predetermined frequency and an oscillator control circuit for cooperating with the tuning element to provide an oscillating electrical signal at the predetermined frequency. The control circuit includes first and second electrical charge storage devices coupled to a first portion of the tuning element; a first current drive device connectable to a first terminal of an applied electric potential and responsive to a first voltage on the first charge storage device for applying a first drive current to a second portion of the tuning element; and a second current drive device connectable to a second terminal of the electric potential and responsive to a second voltage on the second charge storage device for applying a second drive current to the second portion of the tuning element.

Abstract: A device mounted on a power transmission device of a vehicle is utilized for transmitting an RF signal when a predetermined parameter exists in the power transmission device wherein the RF signal is capable of being received at a remote location. An electromagnetic transducer provides alternating voltage as power which is applied to an oscillator including a crystal filter, a junction field effect transistor and a resistor. The alternating voltage is applied across a drain and a source of the junction field effect transistor. The crystal filter is connected between the drain and the gate of the junction field effect transistor while the resistor is connected between the gate and the source of the junction field effect transistor. A wire antenna has a first end which is connected to the drain of the junction field effect transistor and a second end which is connected to the source of the junction field effect transistor to prevent transmission of any RF signal until the predetermined parameter is exceeded.

Abstract: A converter (300) for converting an a.c. voltage (SP) into a direct current (i.sub.3), characterized in that it comprises a first elementary converter (21) which, in response to the a.c. voltage (SP), provides a pulsed direct current (i.sub.1), the mean value (i.sub.1) of which is a steeply rising function of the amplitude A of the a.c. voltage (SP), and a second elementary converter (22) which, in response to the current i.sub.1 provides a current i.sub.3, the value of which is a steeply falling function of i.sub.1.Used for regulating the amplitude of the oscillation signal of an oscillator.

Abstract: A C-MOS oscillator circuit having input and output terminals adapted to be connected to a resonator and two active MOS transistors of complementary types connected in series between the supply terminals of the circuit, which supply terminals are connected to the positive and negative poles of a source of d.c. voltage, the sources of the transistors being connected to a supply terminal and the drains being connected to the output terminal. The d.c. bias and the a.c. voltage control of each of the active transistors are ensured by a MOS transistor of the same type connected as a diode between its gate and its drain, a current source connected between its gate and the supply terminal to which the source of the other active transistor is connected, and a capacitive voltage divider which is connected between the supply terminal, to which its source is connected, and the input terminal, and the intermediate point of which is connected to its gate.

Abstract: A two transistor CMOS inverter has the two transistor gates coupled together by a coupling capacitor. D-C gate bias is supplied to each transistor through high value resistors. The P-channel transistor is biased one threshold below V.sub.DD and the N-channel transistor is biased one threshold above ground. The biasing voltages are developed through the use of a current mirror so that the biasing is independent of processing variables and temperature. This form of biasing renders the circuit class B regardless of the source to drain voltage and ensures low current operation. A crystal oscillator created using such an inverter and biasing will operate at voltages substantially below sum of P and N thresholds and at a current level about one-fifth of that of a conventional CMOS oscillator.

Abstract: A watch circuit arrangement for conserving battery power includes a feedback connection between the crystal oscillator of the watch circuit and the display voltage generator which is responsive to the crystal oscillator output to develop sufficient output voltage for the watch display. Specifically, the output of the display voltage generator, which may be a voltage multiplier, is sensed by a display voltage sensing circuit which controls the gain of the crystal oscillator. Initially, when battery power is applied to the watch circuit, the voltage multiplier has zero output voltage, which conditions the crystal oscillator to have a sufficiently high gain to start the oscillator. After several cycles of oscillator signal, the voltage multiplier output increases, which conditions the crystal oscillator to have a lower gain for reducing power consumption while sustaining oscillation.

Abstract: In an NMOS integrated circuit (10), a basic Pierce-type oscillator stage (16) which includes an inverter stage with a quartz crystal resonator (34) is coupled to a transistor-transistor logic output stage (22) through a comparator (18) and a level shifter (20) to achieve a circuit having the combination of a relatively high tolerance to parasitic capacitances and resistances and a well-controlled output duty cycle of nearly 50 percent.

Abstract: An overtone crystal oscillating circuit is disclosed which includes a complementary MOS inverter formed of P and N channel MOS transistors, a crystal resonator and a feedback resistor which are connected between input and output terminals of the complementary MOS inverter, and first and second capacitors respectively connected to the input and output terminals of the complementary MOS inverter. The crystal oscillating circuit is further provided with a series circuit formed of an inductor and a capacitor and connected in parallel with the first or second capacitor to form a parallel resonant circuit.

Abstract: A very low current Pierce oscillator has two pairs of complementary field-effect transistors (FET's) and a two-terminal quartz crystal. The gates of the first complementary FET pair are coupled through individual capacitors to one terminal of the quartz crystal, their drains being connected together and to the other quartz crystal terminal. Current flow through the crystal oscillator is minimized by a novel oscillator bias loop connected between the gates of the first FET pair. Amplification is provided by the second FET pair which have a commonly connected drain comprising the oscillator output node. The gates of the second FET pair are each connected to a respective one of the gates of the first FET pair. The oscillator bias loop minimizes the source-to-drain current through the first FET pair by reducing the P-channel FET gate voltage in response to the source-to-drain current.

Abstract: An amplifier includes an inverter with two transistors of complementary types. The first transistor is biased through a third transistor of the same type of conductivity by a first reference voltage, the third transistor being biased by a third voltage of reference. The second transistor is biased through a fourth transistor of the same type of conductivity by a second voltage of reference, the fourth transistor being biased by a fourth voltage of reference. The first and second voltages of reference are determined so that without any alternating input signal the current in the first and second transistors of the inverter is minimum. The third and fourth voltages of reference are determined so that the equivalent resistances of the third and fourth transistors are very high.

Abstract: A quartz crystal oscillator for a timepiece including a complementary field effect transistor (FET) pair, wherein one field effect transistor is constant current-biased and the other field effect transistor is self-biased, with high impedance negative feed back loop circuit. The gates of the field effect transistor pair are AC coupled by a condenser, and the drains of the field effect transistor pair are connected to cooperate for AC amplification. The constant current-biased field effect transistor assures a low constant mean current and low start voltage for the oscillator, and the self-biased field effect transistor assures a sure amplifying operation. The AC coupling of the gates assures a high amplification factor and high efficency in excitation of a quartz crystal resonator of an oscillator, whereby the constitution of this invention is simple and easy to form in a monolithic IC chip for a timepiece.

Abstract: In an electronic timepiece having a quartz crystal controlled standard frequency oscillator and a device which temporarily imposes a heavy load on the battery when activated, means are provided for changing a value of a circuit constant in the oscillator circuit, such as capacitance or resistance, when the load device is activated. This change in circuit constant value serves to decrease the value of the minimum battery supply voltage below which the oscillator circuit ceases to function, thereby ensuring reliable operation of the oscillator circuit when the timepiece battery voltage drops due to current being supplied to the load device.

Abstract: In a crystal oscillator for solid state wristwatches, the input of an impedance converter is connected to the output of a complementarily connected transistor amplifier which performs linear operation within its essential operating range, to thereby stabilize and decrease the output impedance of the amplifier on the average. The impedance converter includes one or more active elements such as MOSFET's, junction type FET's and bipolar transistors. A quartz resonator is connected between the input of the complementarily connected transistor amplifier and the output of the impedance converter.

Abstract: A single-stage inverter forming a closed loop together with a crystal resonator fails to provide sufficient gain and hence, power consumption becomes high during stable oscillation. If inverters are coupled together in a three-stage cascade-connection, on the other hand, the gain becomes excessively high and undesired high frequency oscillation takes place at the start of oscillation. This invention provides a crystal oscillator circuit which, in order to solve these problems, uses a single-stage inverter to form a closed loop with a crystal resonator at the start of oscillation and uses three-stage inverters cascade-connected with each other during stable oscillation.

Abstract: A complementary amplifier circuit includes a p-channel MISFET and an n-channel MIS connected in series. The gate of the p-channel FET transistor is D.C. biased by a high impedance resistor connected between the gate and drain electrodes, and the gate of the n-channel FET is D.C. biased by a current mirror circuit formed by another n-channel FET. This complementary amplifier circuit has the advantages that the operational lower limit voltage thereof is equal to the threshold voltage of one of the MOSFETs and that stabilized operation of the amplifier is easily obtained.

Abstract: An improved oscillator circuit utilizes an inverter which includes a pair of series connected MOS-FETs of differing conductivity types. A switching circuit is operable to supply the gate bias voltages from one of two separate sources, one of which is used during periods of start-up or unstable oscillation to decrease start-up time, and the other of which is used during periods of stable oscillation to decrease current consumption.

Abstract: A complementary inverter amplifier circuit comprising a complementary inverter including a p-channel MIS FET connected to a first source potential, an n-channel MIS FET connected to a second source potential, the gate of the two FETs being applied with a common linear input, respective load resistors connected to the drains of the complementary FETs, an output being derived from the interconnection point of the load resistors or from the drains of the FETs, and a bias resistor connected between the gate and the drain of each of the complementary FETs, the input being supplied to the gates of the FETs through respective capacitors. The p-channel FET and n-channel FET are individually biased so that the circuit may serve as a class B push pull amplifier of low power consumption.