Abstract: An oscillation circuit employs a piezo-electric crystal connected in parallel with an amplifier having a gain equal to or less than that needed to maintain a steady-state operation of the amplifier when operated at the maximum output. One or more controllable amplifiers are connected in parallel with the amplifier and controlled according to the level of the oscillation signal, to rapidly amplify an initial oscillation to steady-state operation level and to keep it there without exceeding the output level of the crystal while minimizing the energy supplied to the entire oscillation circuit.

Abstract: An oscillator circuit (30, 40) for starting-up and operating at low voltages has been provided. The oscillator circuit includes an inverter circuit(31, 41) coupled across first and second terminals of a resonant circuit (14). The inverter circuit includes a push-pull driver stage having a P-channel transistor (18) and an N-channel transistor (20). The common drain electrodes of each are coupled to the second terminal of the resonant circuit. The source electrodes of the P- and N-channel transistors are respectively coupled to first and second supply voltage terminals. The gate electrode of the first transistor is coupled to the first terminal of resonant circuit. The inverter circuit further includes a circuit (32, 42) for shifting the voltage level applied to the gate electrode of the second transistor, relative to the voltage applied to the gate electrode of the first transistor, by a predetermined voltage.

Abstract: A digital control system such as a digital temperature compensated crystal oscillator (DTCXO) system is arranged to offer superior oscillating performance with reduced size and cost. For example, to reduce the memory capacity, a memory 31 receives upper 6 bits of temperature data, and a decoder 32 calculates temperature compensation data from lower 4 bits and output data from the memory (FIGS. 1-11). For a one-chip configuration and low power consumption, a MOS type Colpitts oscillator (FIG. 16) is provided with a circuit for adjusting the source resistance of the MOS. For size reduction and fine frequency adjustment, a DTCXO is provided with sections such as an adder 341, an up-down counter 342 and an auxiliary frequency control section (AFC) 332 (FIGS. 20, 21, 24 and 25). An adding section 415 is provided between a D/A converting section 414 and a capacitance varying section 416 to obtain superior linearity with respect to a control voltage and quality of offset.

Abstract: A dynamic bias stabilization device providing significant control of the operating point and frequency stability of a low-power crystal oscillator includes an inverting CMOS amplifier as its primary gain element and a filtered resistive current source to supply the inverting amplifier with operating power. A number of MOS transmission gates and integrated capacitors configured in a T-type network are used as the amplifier feedback element. The control voltages for these feedback transmission gates are derived from the current source which also supplies power to the crystal oscillator amplifier.

Abstract: A crystal oscillator circuit including a quartz vibrator; an inverter circuit connected in parallel to the quartz vibrator and comprised of at least two transistors connected at their output ends to a first power-supply potential or a second power-supply potential lower than the first power-supply potential; a first current mirror circuit, with one current input-output end connected to a connection line with the inverter circuit of the first power-supply potential, the other current input-output end connected to the output end of the oscillator circuit; and either a second current mirror circuit having two current input-output ends, one current input-output end connected to a connection line with the inverter circuit of the second power-supply potential, the other current input-output end connected to the output end of the oscillator circuit, current flowing to one current input-output end, current flowing to the other current input-output end, and the level of the output end of the oscillator circuit being s

Abstract: Oscillation is easily and reliably initiated in an oscillator by increasing the gain of the circuit at startup time. For example, the gain of an oscillator circuit may be increased at startup by reducing the value of a user controlled impedance until oscillation commences. Alternatively, or in combination, the input impedance of an amplifier used in the oscillator may be reduced at startup to facilitate the initiation of oscillation.

Abstract: An oscillation circuit in which the driving performance of a CMOS transistor therein for enabling/disabling an oscillating function is enhanced without unstabilizing the oscillation operation, by applying a higher potential to the back gate of the CMOS transistor when a signal other than an oscillation signal is inputted/outputted, and a lower potential when generating the oscillation signal.

Abstract: A Pierce crystal oscillator circuit for a digital integrated circuit has a capacitance element (such as a field effect capacitor) of an appropriate capacitance value disposed on-board the integrated circuit. One lead of the capacitance element is coupled to the input lead of the gain stage of the Pierce oscillator circuit whereas a second lead of the capacitance element is coupled to the output lead of the gain stage. Providing the capacitance element facilitates oscillator startup and reliability by effectively eliminating the upper gain limit for oscillation. Specific circuit embodiments are also disclosed.

Abstract: A temperature compensated oscillator circuit includes an oscillator (1) which is controlled by a processor (8) . The output frequency (fx) of the oscillator (1) or an external reference frequency (fref) are used as reference signal in conjunction with a dual mode oscillator (9) which can be switched to provide temperature dependent fundamental (f1) and third (f3) harmonic frequencies. By the use of switches (S1, S2 S3), a divider (2) and first and second counters (3, 10) both calibration and temperature compensation of the oscillator (1) are carried out via the processor (8), using the substantially linear temperature dependence of the frequency difference between the third harmonic (f3) and three times the fundamental frequency (3f1).

Abstract: The LOW POWER CRYSTAL OSCILLATOR shown here reduces power consumption of a Pierce oscillator which has an inverter preferably made of an NFET N0 and a PFET P0 in series. A load, preferably an NFET N1 with its gate wired to its source, is placed in parallel with a switch, preferably a PFET P1, between P0 and Vcc. A clamp, preferably a PFET P2 with its gate wired to its source, is placed in parallel with a switch, preferably an NFET N2, between N0 and ground. The switches are enabled during power-up, thereby providing quick turn-on of the oscillator. They are then disabled, thereby reducing the voltage across the crystal XTAL and consequently reducing the power consumed.

Abstract: A controller circuit adjusts the output signal duty cycle of an oscillator circuit. The controller circuit changes the effective bias voltage of an amplifier in a Pierce oscillator by enabling a sequence of transistor stages. Changes to the amplifier bias voltage proportionally alter the duty cycle of the oscillator output signal. Each transistor stage includes a first and second transistor selectively coupled in parallel with the amplifier. Each transistor in the circuit has smaller process parameters than the amplifier transistors so that the amplifier bias voltage can be incrementally increased or decreased to produce an output signal with a high precision duty cycle.

Abstract: A clock generator circuit for producing a clock signal while drawing reduced current drain is disclosed. The clock generator circuit includes a crystal oscillator which produces a periodic signal having a relatively small voltage swing, controlled by one or more reference voltages; the reference voltages are preferably produced by a sub-threshold biased voltage reference circuit. The small signal output of the crystal oscillator is applied to the first of a series of frequency divider stages, prior to amplification by a level shift circuit. Each divider stage includes a current switch which switches the current drawn through current divider legs to produce output signals to latches in the divider stage. Each divider stage also includes one or more current source switched latches, each controlled by current sources that are switched by the current switch.

Abstract: A low-power inverter (53) reduces power consumption over known inverter designs and is especially well-adapted for serving as a buffer in a Pierce crystal oscillator with a large load capacitance. The inverter (53) includes P- and N-side source-follower stages (310, 320) driving CMOS output transistor pairs (350, 360). The source followers are current-limited through current sources (311, 313, 321, 323) which are biased by a stable reference voltage such as a bandgap reference voltage. Clamping devices (331, 332) are provided to limit the voltages on the gates of the output transistors (350, 360), thereby limiting maximum currents thereof. In addition, a helper device (332) is connected to the gate of a P-channel output transistor (350). The P-channel output transistor (350) typically has a large gate area and thus a large capacitance, and the helper device (332) quickly increases the voltage at the gate when an input signal changes to a high voltage.

Abstract: An oscillator circuit provides a symmetrical signal without halving the frequency of a crystal oscillator 12. The input 14 of the crystal oscillator 12 is low pass filtered, and the output 18 of the filter 16 is differential voltage compared with the input 14 of the crystal oscillator 12. The output 22 of the differential voltage comparator 20 is symmetrical and of the same frequency as the crystal oscillator 12. The crystal oscillator 12 is preferably a Pierce oscillator.

Abstract: Disclosed herein is an oscillator circuit generating an oscillation signal in response to a resonant element in a first mode and to an external clock signal in a second mode. This oscillator circuit comprises a tri-state inverter circuit and a transfer circuit between the input and output nodes of the tri-state inverter circuit, and the output node of the tri-state inverter circuit is brought into a high impedance condition when an external clock signal is used and into an active state when the resonant element is employed.

Abstract: A crystal oscillator circuit that provides a low distortion clocking signal. The oscillator circuit incorporates an inverter circuit in combination with a diode connected transmission gate circuit. The transmission gate circuit includes two MOSFETs connected between input and output nodes of the inverter circuit. When the current at the input node goes high and the current at the output node goes low, one of the two transmission gate circuit MOSFETs will begin conducting such that current at the input node will be transferred to the output node, thus decreasing the voltage difference between the two nodes. Likewise, when the current at the output node goes high and the current at the input node goes low, the other MOSFET of the transmission gate circuit will begin to conduct such that current is transferred from the output node to the input node, again reducing the voltage difference between the input and output node.

Abstract: A clock pulse generator has a three-state inverter and a transfer gate forming in combination a feedback loop for oscillating an output clock signal in cooperation with a quartz resonator in an internal oscillation mode, and the three-state inverter enters into high-impedance state in an external oscillation mode so that an external clock signal is transferred to the output node of the three-state inverter without malfunction.

Abstract: A tuneable crystal oscillator arrangement includes a piezo-electric, e.g. quartz, crystal and drive current means therefor. A reactance is arranged in series with the crystal and is fed with a current corresponding to the crystal drive current. The corresponding voltage developed across the impedance is fed via a variable gain amplifier back to the crystal. The reactance comprises a number of impedances, there being current steering means for dividing the current between the impedances. This determines the effective value of the reactance and provides a control or adjustment of the crystal frequency.

Abstract: A micro-miniature resonator-oscillator is disclosed. Due to the miniaturization of the resonator-oscillator, oscillation frequencies of one MHz and higher are utilized. A thickness-mode quartz resonator housed in a micro-machined silicon package and operated as a "telemetered sensor beacon" that is, a digital, self-powered, remote, parameter measuring-transmitter in the FM-band. The resonator design uses trapped energy principles and temperature dependence methodology through crystal orientation control, with operation in the 20-100 MHz range. High volume batch-processing manufacturing is utilized, with package and resonator assembly at the wafer level. Unique design features include squeeze-film damping for robust vibration and shock performance, capacitive coupling through micro-machined diaphragms allowing resonator excitation at the package exterior, circuit integration and extremely small (0.1 in. square) dimensioning.

Abstract: An oscillator circuit having a 50% duty cycle comprises an oscillating stage and an output stage. The output stage comprises a series arrangement of first and second output transistors of complementary conductivity types. The oscillating stage applies a combination of an oscillating signal and a first DC bias to the gate of the first output transistor. The first DC bias is dependent on the amplitude of the oscillating signal. The oscillator circuit also includes a bias-generating circuit for generating a second DC bias at the gate of the second transistor, so as to adjust the input switching level to the median level of the input signal dependent upon the amplitude of the oscillating signal.

Abstract: A microcomputer in which an oscillating circuit provided therein is activated both when the microcomputer is in an activated state and when it is in a disabled state is provided with a changeover circuit for changing over a supply voltage of the oscillating circuit between when the microcomputer is in the activated state and in the disabled state. The changeover circuit supplies to the oscillating circuit a high voltage when the microcomputer is in the activated state and a low voltage when the microcomputer is in the disabled state. As a result, the starting characteristic when the power is turned on is not deteriorated. Further, the power consumption of the oscillating circuit when the microcomputer is in the disabled state is reduced.

Abstract: A phase lock loop operates independent of temperature and process variation by digitally loading a VCO until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit sets the loop node voltage to V.sub.DD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector monitors the output frequency of the VCO and passes control signals to a load control circuit to activate digital loads and slow down the VCO to the desired operating frequency.

Abstract: A crystal oscillator circuit has a sleep mode of operation that reduces power consumption while maintaining oscillation to provide for a fast transition to a normal mode of operation.

Abstract: An oscillation inducing circuit includes a power-on circuit connected to a power supply of V.sub.DD, a plurality of transfer gates, and a capacitor. The power-on circuit (1) supplies a control signal having a first level to the transfer gates so that a capacitor is charged in a first polarity direction to an instantaneous level of the increasing power supply voltage, and (2) supplies a control signal having a second level so that the capacitor is charged in a second polarity direction, opposite to the first direction, to a voltage equal to an addition of the previously charged voltage and the present instantaneous power supply voltage. Together, these two charges produce a relatively high voltage for initializing the circuit and starting an oscillator.

Abstract: A crystal oscillation circuit has a constant-current load type inverter circuit receiving a regulated supply voltage from a voltage regulating circuit and functioning as an inverting amplifier for oscillation; a feedback circuit connected between an input and an output terminal of the inverter circuit and including a resistor and capacitors; and a crystal resonator connected between the input and output terminals of the inverter circuit. The inverter circuit is formed by a constant-current source and a P-channel type MOS-FET or an N-channel type MOS-FET. As the supply voltage from the voltage regulating circuit necessary as an oscillation starting voltage can be set at a low level, the current consumption of the overall oscillation circuit can be effectively reduced.

Abstract: An oscillation circuit having a clocked inverter operating during a predetermined period of time after the start of the oscillation. A feedback circuit is formed by the clocked inverter and another inverter at the start time of the oscillation. The oscillation circuit is therefore driven by a large amount of current and thus the oscillation start time can be shortened and the oscillation start voltage can be lowered. On the other hand, the oscillation circuit is driven only by the other inverter after starting the oscillation. Since a constant current source is inserted serially in the path of the power source of the other inverter. A constant operating current always flows through the other inverter without being affected by the variations of the threshold voltage of the transistors and the variations of the power source voltages. As a result, a low consumption current characteristic of the oscillation circuit can be obtained under low power source voltage.

Abstract: The output of the first CMOS inverter, connected as an oscillator, is applied to the inputs of second and third CMOS inverters that have logic threshold voltages higher and lower than the logic threshold voltage of the first inverter. The outputs of the second and third CMOS inverters are connected to an output circuit via a logic output circuit. The output of the logic output circuit is shorted by an output control circuit, under the control of the outputs of the second and third CMOS inverters, when the output of the oscillator is between the logic threshold voltages of the second and third inverters.

Abstract: Low power oscillator circuits for providing clock signals. The circuits comprise crystal oscillators for providing an input wave form of a specified frequency to the clock circuit, square wave generators having at least two input terminals wherein one of the two input terminals is coupled to the oscillator, and a power output network coupled to the square wave generator for outputting a substantially square wave having substantially the same frequency as the input wave form, the power output network being biased at a high voltage level. Clock circuits described herein provide the advantage of low power oscillation with little power dissipation.

Abstract: A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during startup.

Abstract: A voltage controlled oscillator (VCO 10) is disclosed in a "ring" configuration using two FETs. Two isolated voltage control terminals provide increased tuning bandwidth. The design uses an active feedback topology resulting in greater device size for higher output power and circuit Q.

Abstract: An improved crystal oscillator and output circuit is disclosed. The oscillator has a normal operating mode and a low-power mode. In the low-power mode, a reduced current which is sufficient to maintain oscillation is supplied to the oscillator and the output circuit is disabled. The oscillator can subsequently be returned to normal mode and the output circuit enabled. Since the oscillator is never shut completely off, the time required to resume normal mode oscillations is reduced.

Abstract: A clock generator (30) dynamically generates a system clock in response to a high or a low frequency oscillator. An amplified oscillator input is provided to a first input of a multiplexor (62), a divider (56), and a comparator circuit (58, 60). Divider (56) divides an oscillator input frequency to provide a divided input to a second input of multiplexor (62). Comparator circuit (58,60) compares the input frequency with a reference frequency to determine whether the input frequency is high or low. If the input frequency is low, multiplexor (62) is enabled to provide the oscillator input as the system clock. If the input frequency is high, multiplexor (62) provides the divided input as the system clock. Additionally, comparator circuit (58,60) provides a control signal to enable an amplifier (50) to amplify the oscillator input using a high or low gain factor in accordance with the input frequency.

Abstract: A low-power crystal-controlled CMOS oscillator wherein a long and wide additional transistor is provided in the first stage of the output amplifier. This prevents the output amplifier from diverting too much current from the primary amplifier stage during start-up.

Abstract: On an integrated circuit, a power limiting circuit is added to a crystal oscillator for limiting power dissipation in the crystal to a prescribed safe power dissipation range. The power limiting circuit includes a Pierce design crystal-controlled oscillator coupled to a self-stabilizing circuit. The self-stabilizing circuit detects the oscillation amplitudes of the crystal controlled oscillator. The self-stabilizing circuit prevents the oscillations from exceeding a predetermined maximum power dissipation level for the crystal. The self-stabilizing circuit includes a means for detecting oscillation amplitudes and means for limiting the gain of the crystal controlled oscillator circuit. Therefore, independent of manufacturing tolerances from integrated circuit to integrated circuit, the self-stabilizing circuit assures that the maximum power dissipation level of the crystal is not exceeded.

Abstract: A CMOS oscillator integrated circuit in a Pierce crystal oscillator circuit configuration operates at oscillating frequencies over a wide band frequency range. A single inverter stage (I1) is coupled between the oscillator input (OSC IN) and the oscillator output (OSC OUT). An oscillator feedback circuit coupled between the oscillator output and oscillator input incorporates an oscillator crystal (XTAL). A pullup gain network (PNET) provides a plurality of different parallel pullup gain paths between the pullup transistor (P1) of the inverter stage (I1) and the high potential power rail (V.sub.CC). The pullup gain paths have different pullup gain resistances (RP2, RP3, . . . RPN) in the respective pullup gain paths for implementing different amplifying gains (A.sub.N) by the inverter stage (I1). Digitally addressable pullup gain switches (P2, P3, . . . PN) are coupled in respective pullup gain paths for selecting different gain paths and different amplifying gains (A.sub.N).

Abstract: A simple and broadly applicable method for reducing phase noise in varactor tuned voltage-controlled oscillators (VCOs) is described. In particular, it is shown that by appropriately selecting the inductance of a choke inductor used to isolate the varactor from its DC bias supply, this inductor will also perform a noise filtering function by shunting off part of the internally generated low frequency random electronic noise through the DC supply, thus reducing a primary contributor of oscillator phase noise. Versions of this phase noise reduction method appropriate for the Colpitts, Hartley, and Clapp type LC voltage-controlled oscillator topologies are illustrated.

Abstract: A piezo-electric oscillator includes an oscillatory circuit including a piezo-electric resonator for generating an oscillatory signal, a buffer amplifying circuit for buffering and amplifying the oscillatory signal, the buffer amplifying circuit being connected serially with the oscillatory circuit, and a switching circuit for switching a power supply line. The switching circuit is connected in parallel with the buffer amplifying circuit and selectively short-circuits the buffer amplifying circuit in accordance with an output signal of the oscillatory circuit.

Abstract: A crystal oscillator uses automatic gain control to minimize the operating current through its inverting amplifier. The power supply potential to switching transistors of the amplifier is reduced by the automatic gain control to a level substantially equal to the sum of the switching thresholds thereof which minimizes simultaneous conduction through the switching transistors and associated operating current. The low level output signal of the amplifier becomes sinusoidal about a DC bias point operating at the resonant frequency of the crystal which eliminates undesirable harmonicas interfering with the crystal's natural vibration. The sinusoidal output signal may be buffered and level-shifted to a useable state.

Abstract: An oscillator, such as a crystal oscillator, is presented for low jitter (low phase noise) applications, such as in frequency synthesizers or digital repeaters. The two terminals of a resonator are coupled to the input and output of an amplifier, the amplifier together with other components effecting a negative impedance. The inputs of a comparator are connected to the terminals of the resonator. The output of the comparator, preferably differential, is a signal having a frequency substantially determined by the resonator.

Abstract: The crystal-controlled oscillator circuit of the microprocessor comprises, for the starting resistance, a pair of discrete resistors connected in parallel. The two have respective resistance values which in their parallel circuit connection are effective to cause the initiation of electrical oscillation and which are also individually effective to cause the initiation of electrical oscillation so that in the event that one of the individual resistors experiences an open circuit fault, the oscillation can nonetheless be initiated by the other of the individual resistors. The invention provides improved reliability for automotive vehicle engine control systems.

Abstract: In an oscillator circuit, a high gain, high power driver is placed in parallel with a standard low gain, low power driver for driving the oscillator output. A control signal is derived from the output of the oscillator circuit and fed back to control the high gain driver. After the circuit output has achieved stable oscillations for a predetermined time period, the high gain driver is turned off. Employment of the high gain driver ensures high start-up ability. The overall power consumption remains low since the high gain driver is turned off after stable oscillations have been achieved.

Abstract: A piezoelectric oscillator semiconductor circuit comprises a piezoelectric oscillator which is set to a designated oscillation frequency via electrical coupling to a separate semiconductor element comprising an oscillation circuit. The oscillation circuit in the semiconductor element has a gate lead and a drain lead connected to the piezoelectric oscillator to set the frequency of operation of the piezoelectric oscillator. Included in the semiconductor element are adjustment means comprising one or more frequency adjustment elements which may be selectively connected to one of the connection leads whereby the frequency of operation of the piezoelectric oscillator may be selectively changed without need for replacement or change of the semiconductor element. The frequency adjustment elements may be comprised of one or more fixed, separately formed capacitances provided as part of the semiconductor element but are electrically independent of the oscillation circuit, i.e.

Abstract: A voltage controlled crystal oscillator circuit, such as a Pierce oscillator circuit, includes an amplifier and is balanced by the addition of another varactor connected directly to the amplifier, whereby the frequency pull range is increased. Further, greater linearity can be achieved by adding another pair of varactors to the circuit.

Abstract: An oscillator circuit incorporated in a semiconductor integrated circuit and comprising an oscillation input terminal, an oscillator output terminal, an inverting logic circuit, and a transmission gate. The terminals and are connected to an external oscillator. The inverting logic circuit comprises an N-type MOS transistor and a P-type MOS transistor. The input and output terminals of the logic circuit are connected to the oscilllation input and output terminals, respectively. The transmission gate comprises an N-type MOS transistor and a P-type MOS transistor. Either MOS transistors has a source electrode and a drain electrode, one of which is connected to said oscillation input terminal, and the other of which is said oscillation output terminal. The gate-insulating film at least one of said MOS transistors incorporatedin the transmission gate is thicker than those of other MOS transistors formed on the semiconductor substrate.

Abstract: An oscillator circuit for use with a supply line and a line at a reference potential includes a crystal and a switching stage, the switching stage being closeable to connect the crystal to the supply line via one terminal of the crystal. The other terminal of the crystal is connected to the line at reference potential. Closing of the switching stage is controlled by a drive unit, which has an input to which the output of the switching stage is fed back. The drive circuit causes the switching stage to be briefly closed during a half period of the oscillation. If the oscillator circuit is manufactured as an integrated circuit, only one terminal pin is required for connection to the crystal, thereby saving space.

Abstract: An integratable amplitude-regulated oscillator circuit includes a resonator element, a control element having a control input, an inverter having an output and an input coupled to one another through the resonator element and having a quadrature-axis current component being variable by the control element, an amplitude regulating circuit having an input connected to the input of the inverter and an output connected to the control input of the control element, and an output stage having an input connected to the input of the inverter. The amplitude regulating circuit includes a differential amplifier having an inverting input and a non-inverting input, a first peak value rectifier connected upstream of the inverting input, and a second peak value rectifier connected upstream of the non-inverting input.

Abstract: A differential pair, push-push oscillator for generating clocking signals. This oscillator consists of two, single transistor oscillators that both oscillate at f.sub.o with a 180.degree. phase difference. The phase difference is caused by the direct connection of the transistors' drains. A current source, connected to the transistors' drains, biases the transistors. The common drain connection also serves as an output for the differential pair, push-push oscillator. This output, a stable, relatively high power signal of frequency 2f.sub.o, is a composite of the two signals from the single transistor oscillators.

Abstract: A voltage variable capacitor (VVC) having two terminals in a variable frequency crystal oscillator integrated into a common substrate with the oscillator circuitry and isolated therefrom. The VVC is constructed using the same processing steps as the oscillator circuitry and achieves low series resistance and wide capacitance variation by utilizing a substrate or epitaxial layer (body) having a well with a diffused region therein. The region, of the same conductivity type as the well and a first one of the two terminals, forms a rectangular ring in the well. Over the region and insulated therefrom, a conductive layer is deposited to provide a second one of the two terminals. Both terminals are electrically isolated from the body.

Abstract: A CMOS oscillator is disclosed using an inverter in which a pair of control terminals are employed to invoke various sized devices which control the flow of current. The inverter gain is determined by the size of the CMOS devices employed. A tuned circuit coupled to the inverter causes it to oscillate at the frequency of parallel resonance. The control terminals are coupled to the inverter invoke transistors that are sized as desired to establish the current flow and gain in the inverter. The current flow is controlled to optimize the gain of the inverter in terms of the frequency of oscillation. A Schmitt trigger can be employed to clean up the oscillator output for digital clock source applications.

Abstract: A CMOS crystal oscillator circuit for producing a 32 KHz clock signal operates at low power over a range of power supply voltages without overdriving the crystal. To accomplish this, the complementary MOS transistors in the oscillator inverter are supplied with operating current from a constant low current source. The constant low current is at an optimum value for crystal stability and power consumption and is independent of supply voltage variations. To ensure quick initial start-up of the oscillator circuit, a second current source is connected in parallel with the constant current source; and the second source initially is switched on for a pre-established time interval to supply significantly greater operating current to the oscillator inverter only during initial start-up of the oscillator. After this pre-established time interval, the second current source is rendered inoperative or non-conductive for the duration of the operation of the oscillator circuit.