Abstract: A phase-locked loop circuit is disclosed for use, for example, in the data recovery system of a rotating magnetic disk drive unit employing a phase encoded signal format. The phase-locked loop circuit has a dual mode of operation wherein captive range is assured by providing a first frequency locking mode of operation wherein a voltage controlled oscillator (VCO) is first locked in frequency to a reference signal and a second phase locking mode of operation wherein the VCO is subsequently locked in phase to an MFM signal independently of the frequency assumed by the latter signal. In addition to the VCO, the phase-locked loop circuit includes a frequency detector, a phase detector, a filter, an amplifier, a pair of frequency dividers, a pulse shaping network and a plurality of switches. A potentiometer is coupled to the input of the amplifier and is used to supply a voltage signal to the amplifier which is sized to offset system phase errors caused by the various components in the phase-locked loop circuit.

Abstract: A continuous wave pseudonoise radar system which employs a large word rate to avoid spillover and other noise. Spillover is the electromagnetic energy that is transmitted from the transmitting antenna directly to the receiving antenna. In other words, the spillover is not reflected from the target. The word frequency is thus made higher than the highest expected doppler. The high word rate would normally cause an ambiguous range indication because the word wavelength would be less than twice the maximum expected target range. However, this problem is solved by the use of coarse and fine range indicators. It is an outstanding feature of this invention that the coarse range is obtained by changing the transmitter bit rate. The difference between transmitter and receiver bit frequencies is then integrated over a selected period. The definite integral is directly proportional to range. However, the range turns out to be a function of the transmitter bit frequency only at the integral limits.

Abstract: A non-linear phase detector is disclosed which compensates for gains occuring during tuning a frequency generator of a known phase locked loop circuit which incorporates a Varactor tuned resonant circuit as a VCO. The phase detector is of the sample and hold type and incorporates a Varactor rather than a hold capacator to compensate for non-linear gains which occur when tuning the frequency generator across its band spread. Additionally, bias compensation is provided for the resonant circuit Varactor to offset its contact potential.

Abstract: A system for minimizing synchronization errors in a phase-locked loop having a sequential phase detector for determining the phase difference between the output of the VCO of the phase-locked loop and a periodic control signal. Control circuitry is provided so that the control signal is enabled as an input to said sequential phase detector for a relatively short time window which comprises a small fraction of the control signal cycle period beginning just before a control signal is anticipated and the signal is disabled for the remainder of said control signal cycle period. Provision is made for the phase detector to process only the first control signal in any given enable time window. Additional circuitry is provided to disable the control circuitry when the phase locked loop is detected to be out of lock.

Abstract: A system for decoding a PSK signal comprising a constant amplitude carrier whose phase shifts 180.degree. each time a logical signal is transmitted. The decoder system includes a phase-locked loop including a first phase detector, a loop filter, and a voltage-controlled oscillator. The incoming PSK signal is supplied to the input of the phase-locked loop and through a 90.degree. phase shifter to one input of a second phase detector. The other input of the second phase detector is taken from the output of the voltage-controlled oscillator and the output of the second phase detector will indicate whether a carrier or data is detected. The output of the second phase detector is connected to the inputs of first and second comparators. One comparator has its inputs biased so that it normally outputs a low signal until the second phase detector indicates the detection of a carrier. This output can be used as a source of reconstructed data.

Abstract: In an ultrasonic system for detecting and distinguishing between superimposed and single sheets moving along a transport path, the frequency of the ultrasonic source is kept tuned to the natural frequency of the total system so that the phase displacement detected when a sheet-like object is present between the source and the ultrasonic receiver represents characteristics of the object itself. When no sheet-like object is present the receiver and the source are connected in a feedback circuit producing a certain natural frequency comparable to that which occurs with proximities between a microphone and a loud speaker, and the frequency of an oscillator is tuned to this natural frequency. When a sheet-like object is present the tuned oscillator frequency is applied to the ultrasonic source and its phase is compared with the phase of the ultrasonic signal at the receiver.

Abstract: An integrator and a voltage controlled oscillator produce a variable frequency output signal. A primary loop is locked to an input signal and has a narrow bandwidth allowing the output signal to precisely track the input signal. An initialization loop is locked to an internally generated reference signal and has a wide bandwidth for pulling the frequency of the output signal very close to the frequency of the reference signal. Since the frequency of the reference signal is approximately equal to the frequency of the input signal the initialization loop pulls the frequency of the output signal very close to the frequency of the input signal thus assuring locking of the primary loop. A switch selectively connects components of the primary loop to the integrator when the frequency difference between the reference signal and the output signal is small and connects components of the initialization loop to the integrator when the frequency difference between the reference signal and the output signal is large.

Abstract: A channel selector characterized in that a plurality of receivers capable of simultaneously performing a receiving operation have a main part of a phase-locked loop frequency synthesizer connected in common thereto, the frequency synthesizer having a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider. The frequency synthesizer is controlled so that a local oscillation frequency corresponding to a determined frequency close to a broadcast signal of a desired receiving channel is synthesized, and one of a plurality of search tuning systems searches and tunes the broadcast signal from the local oscillation frequency.

Abstract: A carrier oscillation in the microwave range is stabilized by a sequence of timing pulses produced by a crystal-controlled reference oscillator whose cadence is an aliquot fraction of the nominal carrier frequency. The pulses are used to obtain two phase-representing amplitude samples of the carrier wave from a pair of mutually phase-shifted pilot oscillations of the same frequency in each of a succession of nonconsecutive cycles thereof; a control voltage derived from these amplitude samples is fed back to the microwave oscillator via a frequency-correcting or phase-locking loop.

Abstract: A phase lock loop for a frequency synthesizer operating by counting different frequencies to a common fixed number to generate different time bases. An error signal is generated by counting bits of a first frequency over a given count relative to bits received at a second reference frequency. If an error occurs, a programmed frequency change takes place, otherwise the synthesizer is maintained at the programmed center frequency. Error detection resumes with a new counting period determined by the programmed change.

Abstract: The oscillation frequency of a variable frequency oscillator is swept by a sweep signal from a sweep signal generator and the oscillation frequency is compared with a preset sweep start frequency for detecting coincidence therebetween. Upon detecting the coincidence, the sweep operation of the sweep signal generator is stopped and, at the same time, the oscillation frequency of the variable frequency oscillator is made by phase lock loop means to be phase-synchronized with a reference frequency. When the phase synchronization is established, an error signal in the phase synchronization is held and the loop of the phase lock loop means is cut off and then the error signal is applied to the sweep signal generator to re-start the frequency sweep of the variable freqency oscillator. When coincidence is detected between the oscillation frequency of the variable frequency oscillator and a preset sweep stop frequency, the sweep operation is stopped.

Abstract: A phase locked loop (10) has a phase insensitive frequency comparator (18) including an up/down counter (26) incremented one way by loop frequency pulses (on 28) and incremented the other way by reference frequency pulses (on 30) and which yields error correction signals (on 22 and 24) to adjust loop frequency when the counter overflows or underflows given limits. Timing means (32) is provided at the input (28, 30) to the counter (26) and prevents any clock pulse from being lost by ensuring a sufficient time gap between pulses. A sample and hold phase detector circuit (16) is provided at the data acquisition input to the loop (10) and enables successful acquisition and lock-on even with many zeros between the incoming data bits, and does so with a minimum number of components.

Abstract: Timing pulses are generated from operative synchronous data pulses by means of a crystal oscillator under direct control of the output signal of a D flip-flop. The flip-flop is set or reset depending on the phase of the clock pulse relative to the leading edge of the data pulse.

Abstract: An improved frequency synthesizer utilizes a first order loop and sample-and-hold phase detector with optimized gain to obtain very fast frequency locking characteristics. In addition, synchronization of the programming of the loop divider and of the range shifting the voltage controlled oscillator is also utilized. An adaptive loop filter is provided to allow a first order loop to be used for lock acquisition and still maintain excellent noise performance after lock has been obtained.

Abstract: A second-order phase-locked loop circuit which does not require error voltage amplification is described. The output of a voltage controlled oscillator is accurately phase locked to a reference pulse. The loop phase detector is periodically enabled by a pulse generator and draws current only when enabled. Therefore very little noise may be coupled to the voltage controlled oscillator. The phase detector incorporates a current amplifier which allows very accurate establishment of the instant phase comparison takes place.

Abstract: A frequency synthesizer is controlled by the frequency of an input signal. The input signal is sampled and, either during or at the end of the input signal, the output signal is locked on the frequency of the input signal. Octavely related harmonics are combined to provide tone color.

Abstract: In the free induction technique of this invention, the maser is externally stimulated to allow significant reduction of the size of the maser, and the stimulation is turned off and allowed to decay so that the maser output is free from the external stimulation before the signal is sensed to provide a clock frequency standard. As a result, the invention solves significant problems which otherwise have limited the accuracy of prior art atomic clocks, including the problem of frequency pulling due to amplitude drift in the stimulation signal.

Abstract: The out-of-lock condition of a digital phase locked loop is detected during a plurality of states such that single bit discrepancies, such as a noise pulse, are ignored, and thus the tolerable range of phase detection error is broadened. The present invention is adaptable for use with typical applications of digital phase locked loops, and can be used to control the phase detector of the digital phase locked loop such that error voltages will be introduced into the loop only during selected states.

Abstract: A voltage controlled oscillator (VCO) and reference oscillator are connected in a phase locked loop with a first phase detector, loop switch, and acquisition sawtooth sweep circuit. A second phase detector and fast integrator circuit are connected to the VCO and reference oscillator in quadrature relation with respect to the first phase detector. As the acquisition sweep circuit sweeps the VCO, the fast integrator produces a signal whose magnitude increases as the swept VCO frequency approaches the frequency needed for the phase locked loop to achieve phase lock. When this signal magnitude exceeds a predetermined threshold, an output control signal is produced. This output control signal causes the loop switch to close and make the phase locked loop operational. A delay circuit is connected to the second phase detector and fast integrator. The delay circuit produces a delayed output at a predetermined time after the control signal is produced.

Abstract: A simultaneous multichannel signal generator incorporating phase-locked l frequency correction. For each channel, there is a voltage-controlled oscillator (VCO) set to an appropriate frequency by a tuning signal and modulated by a channel data signal. The output signals from all VCO's are provided to a summer and then are appropriately amplified and filtered for transmission. A single multiplexed frequency correction circuit compares the phase of a reference frequency signal with the phase of a VCO output signal whose frequency has been divided, by a divide-by-N counter, to the reference frequency. If the divided VCO signal is out of phase with the reference frequency signal, an appropriate correction signal is provided to the device providing voltage control for that VCO.

Abstract: A frequency program synthesizing apparatus and method is disclosed for controlling delay circuitry in ultrasonic imaging systems. Each frequency program synthesizer includes an adjustable frequency source for producing the clocking signals and a multichannel memory having a plurality of address channels each allocated for digitally storing a signal representing the frequency corresponding to one of said frequency program steps and circuitry for applying the stored signals in a sequence to cause the adjustable frequency generator to produce the frequency program. Each program synthesizer also includes updating circuitry for adjusting the values of the stored digital frequency representations to compensate for undesirable differences between the frequency of the generated program and a set of predetermined program frequency steps.

Abstract: An improved automatic frequency control arrangement for a missile-borne inverse receiver is shown to include a reference oscillator and a voltage-controlled oscillator with control means for the latter, such means including a frequency-to-voltage converter responsive to the difference frequency between the two oscillators so that the latter may produce a signal representative of the Doppler shift frequency of a target. A starting circuit is also shown to ensure that the frequency of the reference oscillator is always lower than the frequency of the voltage-controlled oscillator.

Abstract: The invention relates to phase locked loops in which a variable-frequency voltage-controlled oscillator (VCO) feeds a phase comparator via an adjustable divider having a division factor N. The comparator compares the phases of the divided frequency (Fd) and a reference frequency (Fr), and adjusts the VCO to produce phase equality. To enable the VCO frequency (FO) to be adjusted in smaller steps than Fr and yet maintain a loop bandwidth greater than the step size with good spurious performance (thus providing a "fractional N synthesizer"), Fo is made slightly more than N.Fr. The phase detector thus produces a phase error signal. At periodic instants, determined by the period of the frequency difference between Fo and N.Fr, a control unit temporarily increases N by unity so as to bring Fd and Fr into phase.

Abstract: A phase-locked loop circuit includes a voltage controlled oscillator responsive to a control voltage for generating a periodic first output signal comprised of pulses occurring at a first frequency determined by the value of said control voltage. In response to the first output signal, a periodic feedback signal is generated comprised of pulses occurring at a second frequency which bears a predetermined relationship toward the first frequency. In response to the feedback signal and to a first input signal having a first periodic interval during which pulses at a third frequency occur and a second periodic interval during which said pulses at the third frequency do not occur, a second output signal is generated comprised of the pulses of the first input signal during the first periodic interval of the input signal and the pulses of the feedback signal during the second periodic interval of the first input signal.

Abstract: A phase comparator for a digital phase locked loop which provides first and second order error signals for phase and frequency correction of a voltage controlled oscillator in the loop with respect to data being read for self synchronization of the data. A first order error signal is generated in a first phase detector which operates only during a VCO "unsafe" condition, i.e., when a data pulse is beyond a present limit. A finer, second order error signal is generated in a second phase detector which operates only during a VCO "safe" condition, i.e., when a data pulse is within a preset limit.

Abstract: A phase regulating circuit in which a phase comparator is supplied with output pulses of a pulse generator over a frequency divider and, for comparison therewith, the timing pulses derived from a displacement pick-up, with the output of the phase comparator being utilized for controlling the pulse generator to regulate the phase of the output thereof, means being provided for interrupting the supply of timing pulse from the frequency divider to the phase comparator in the event of an interruption in the displacement pick-up pulses, and which, upon recurrence of the displacement pick-up pulses, reconnects the frequency divider to the comparator for supplying divider output pulses to the comparator which have been matched in phase as close as possible to that of the displacement pick-up pulses.

Abstract: A master timing generator capable of tracking an externally generated clock signal and of maintaining desired operation during periods of disruption or perturbation of the clock signal by noise or other high-energy disturbances. The master timing generator includes a voltage controlled oscillator controlled by an input dc control voltage to produce an output signal which is maintained in a particular phase relationship with the clock signal by phase lock loop circuitry coupled to the oscillator. A dc standby voltage signal representative of the value of the control voltage applied to the oscillator is retained during operation of the master timing generator in a standby unit which, in the absence of noise affecting the clock signal, is electrically uncoupled from the oscillator.

Abstract: A clock circuit comprising a synchronizable voltage controlled oscillator in combination with a programmable address means, which address means is adjusted commensurate with the acoustic velocity of the workpiece, provides clock pulses from the oscillator having a stable and accurate acoustic velocity dependent frequency. An entrant surface responsive electrical signal responsive to an ultrasonic search signal entering the workpiece is also provided to the clock circuit for assuring that the clock pulses are synchronized with the receipt of the electrical signal.

Abstract: A variable frequency oscillator is disclosed which is electronically and periodically swept from one frequency to another. Prior to the beginning of each sweep, the variable frequency oscillator is phase locked to a reference signal source and the error voltage in the phase lock loop is stored. When the sweep begins the phase lock loop is opened and the error voltage is summed with a sweep voltage to provide for correction of oscillator drift on a sweep by sweep basis.

Abstract: A circuit for synchronizing an oscillator keyed by a pulse is provided with a low amplitude reference oscillation. A phase shift regulating loop has a phase discriminator which is fed, on one hand, with a branched component of the oscillator output and, on the other hand, with the reference oscillation. The phase discriminator compares the phases of the two oscillators and emits a resultant regulating voltage an adjustable reactance for controlling the oscillator frequency during the leading edge of the keying pulse. A phase shift device, adjustable over 180.degree., is connected between the oscillator and the phase discriminator, the phase discriminator having a high-ohmic output which is connected, via an impedance converter, to the adjustable reactance.

Abstract: A variable frequency oscillator including a nonlinear element for varying the frequency has alternately attached thereto a phase lock loop for maintaining the base or starting frequency of the oscillator substantially constant, and a sweep generator with a rate error loop for sensing the frequency linearity of the output sweep and altering the input signal to maintain the output linear.

Abstract: A new and improved apparatus and method for phase detection in binary signal tracking loops wherein two bandpass detectors are alternately interchanged between electrical connection with two local code reference tracking signals in order to cancel any adverse effect of gain imbalance in the bandpass detectors and direct current offset or drift. The incoming signal is multiplied with the two local reference signals in a mixer circuit to form first and second product signals which are each separately provided to two bandpass detectors to form error signals. A dither generator controls a first switching circuit to alternately interconnect the two local reference signals to the mixer circuit during the step of multiplying and also controls a second switching circuit to alternately interconnect the error signals to a summing circuit to form a composite error signal representing a difference in levels of the two error signals from the detectors.

Abstract: Phase-locked loop having a controllable oscillator and a phase detector for generating an output signal which is applied as control signal to the oscillator through a loop filter comprising a storage element, which loop filter is switchable under the control of a control circuit between a first state wherein the loop filter has a wide passband and a second state wherein the loop filter has a narrow passband, provided with an arrangement connected to said storage element for determining the instants at which the instantaneous value of the signal stored in the storage element is equal to the average value of the control signal for the oscillator, the control circuit being arranged such that, after locking, switching-over of the loop filter from the first to the second state is done at one of the instants determined by said arrangement.

Abstract: A phase-locked loop which simultaneously switches both the phase of the reference signal received from the voltage-controlled oscillator of the loop and the sign of the d.c. channel gain. The switching is performed at a frequency lying between the phase of the incident wave and the loop cut-off frequency.

Abstract: The measuring system of the disclosure has two oscillators of different frequencies. The oscillations of the high frequency oscillator are counted for a time corresponding to a portion, for example one-eighth, of the period of the low frequency oscillator. If the count is less or greater than a selected count, for example 4,096, the frequency of the low frequency oscillator is corrected by approximately one high frequency period in the one-eighth low frequency period. By this method the oscillators are brought into near-synchronism, so that there are counted exactly 4,096 high frequency oscillations during the one-eighth period of the low frequency oscillator, but neither 4,097 or more, nor 4,095 or less. The correction is accomplished by excluding or including one at a time, various resistors in the frequency determining portion of the low-frequency circuit by the use of transmission gates in parallel with the resistors. The system may be used to measure, for example, weight.

Abstract: A frequency synthesizer including a phase-locked loop (PLL) is provided which does not use any variable frequency divider. The output of a reference frequency oscillator is applied to a phase comparator in the PLL through a monostable multivibrator. The oscillating frequency of a voltage controlled oscillator (VCO) in the PLL can be selected by controlling a bias DC voltage applied to a control element in the VCO. The output waves from said VCO are counted at a counter during a period of the reference frequency from the reference frequency oscillator of the PLL. The count operation is repeated at a predetermined time interval. After completion of each count operation, the number in the counter corresponding to the least digit column of the decimal number is discriminated to determine whether it is within a predetermined range or not. The range is determined correspondingly to a locking range of the PLL.

Abstract: A frequency synthesizer capable of rapidly changing to a different desired output frequency includes a voltage-controlled oscillator and a variable frequency divider arranged in a phase-locked loop. A first frequency-control voltage is initially applied to the voltage-controlled oscillator to cause a rapid change in its output frequency toward a desired value. Then, the divisor of the variable frequency divider is changed to produce a second frequency-control voltage which precisely sets and maintains the oscillator output frequency at the desired value.

Abstract: A variable oscillator controlled by a phase-locked loop to lock on to a received pulse of radio frequency waves, sample and hold circuitry sampling the control signal in the loop and storing the signal, and a timed switch disconnecting the oscillator from the loop and connecting it to the sample and hold circuit after a predetermined period of time so that the oscillator is locked on to the radio frequency after the single pulse ceases.

Abstract: A phase synchronizing system having a dual mode of operation for use, for example, with "modified frequency modulation" (MFM) encoded signals wherein captive range is assured by providing a first frequency locking mode of operation wherein a voltage controlled oscillator (VCO) is first locked in frequency to a reference signal and a second phase locking mode of operation wherein the VCO is subsequently locked in phase to an MFM signal independently of the frequency assumed by the latter signal.

Abstract: An improved frequency memory system of the type using a voltage controlled oscillator is described. Incoming RF signals are power divided with a first power divided portion applied to a frequency discriminator where a voltage level signal indicative of frequency is derived. This voltage level signal is shaped and applied to the volage controlled oscillator wherein the oscillator is broadly tuned to the incoming frequency. A remaining portion of the power divided signal is applied directly to the RF circuit portion of the VCO oscillator to injection lock the VCO oscillator to the incoming signal.

Abstract: A sample-and-hold circuit has an input terminal connected to a source of analog voltages to be stored, this terminal being connected during a sampling phase via a first switch to an output terminal and to an input of a first amplifier working into a storage capacitor by way of a second switch also closed during that phase. The capacitor is tied to one of two differential inputs of a second amplifier, the other differential input being connected to the output of the first amplifier upon closure of a third switch during a holding phase in which the first and second switches are open.

Abstract: A frequency synthesizer in which the frequency of a variable frequency oscillator is controlled by means of a control signal and wherein means are provided for determining whether any frequency variation results from a drift in the frequency of the variable frequency oscillator means being provided for generating and maintaining an additional drift control signal to compensate for such drift. The drift control signal is inhibited from change either when it is detected that the control signal is in excess of that which would result solely from drift or the control signal is representative only of a quantisation error.

Abstract: A narrow-band tone decoder has a controllable oscillator, connected in a fast-capture phase-locked loop, for generating a signal having a frequency determined by a control signal produced within the loop. A synchronous detector, which responds to an input signal of the tone decoder and to a signal from the controllable oscillator, produces a signal having a magnitude dependent upon the magnitudes of the input signal and of the signal from the controllable oscillator. A window comparator monitors the control signal within the loop for deciding when the generated signal is within a predetermined frequency range.

Abstract: A controllable oscillator is maintained at a center frequency f.sub.o by the inventive system. The oscillator signal is directly coupled to one input of a diode detector via a first path, and is alternately coupled, at a clock signal rate, to the second detector input via second or third paths. The second path has a selected transfer characteristic such that when it passes the oscillator signal the diode detector output is at a null. The third path includes a resonator whereby the oscillator signal passed therethrough results in a null at the detector output only when the oscillator is tuned to f.sub.o. The diode detector output is then phase detected with the clock signal thus producing an output correction signal which, when integrated, is fed back to the oscillator for precise control thereof. Since the system correction is dependent solely on an AC signal, errors due to the DC characteristics of the components, e.g. the detector diodes, may be eliminated.

Abstract: A digitally settable frequency generator comprises a master oscillator whose operating frequency f.sub.Q is variable between a normal value f.sub.Q " and a slightly lower value f.sub.Q ' = (1-p)f.sub.Q " with the aid of a normally disconnected tuning capacitor. The master oscillator works into a frequency divider of fixed step-down ratio m:1 (or 2m:1) to produce a reference frequency f.sub.B. A slave oscillator, generating an output frequency f.sub.A = gf.sub.B, is controlled by a phase-locking loop including a phase comparator to which the reference frequency f.sub.B is fed along with a like frequency obtained from output frequency f.sub.A with the aid of another divider having a digitally variable integral step-down ratio g:1. A fractional value i, which may range from 0 to 100%, is set with the aid of a numerical interpolation selector to determine the number n<m of cycles of operating frequency f.sub.Q within a cycle (or half-cycle) of reference frequency f.sub.

Abstract: Apparatus is provided for determining the frequency of unknown periodic input signals and primarily generally sinusoidal signals which may be accompanied by substantial noise. More particularly a unique traffic radar or doppler radar is provided employing such frequency measuring apparatus. The apparatus includes a phase locked loop in which a frequency multiplier effect is produced and in which a frequency 12 times the periodic input signal being subjected to measurement is employed for taking two independent samples of the input signal and providing a synthetic representation of that signal. The two samples are centered about quadrature time references and are preferably conterminous. This signal can be measured and utilized for speed measuring purposes and other purposes where the accurate measurement of a periodic signal accompanied by noise is desired.

Abstract: Method and apparatus for reducing phaselock loop FM'ing without disturbing the loop filter. After the loop is locked, the loop filter input signal is changed so that high frequency components therein are increased in intensity and yet the average value of this signal is substantially unchanged.

Abstract: Homodyne automatic frequency control circuitry maintains the mean or center output frequency of a controlled oscillator, e.g., the output of a voltage controlled oscillator effecting frequency modulation, equal to the output frequency of a reference oscillator. The composite AFC circuitry employs ganged sampling switches and a common mode error obviating common frequency detector (e.g., a discriminator) to alternately store voltages representative of the reference and controlled oscillator frequencies in capacitors connected to the inputs of a difference amplifier. The difference amplifier acts through an integrator to supply any necessary correction potential to the control port of the controlled oscillator when the signals stored in the two capacitors differ, signalling that the mean output frequency of the controlled oscillator has departed from that of the reference oscillator.

Abstract: Phaselock circuitry including means for providing a frequency variable feedback signal and a phase detector receiving the input signal and the feedback signal. The phase detector provides pulses whose width and average value are dependent on the phase relationship between the input and feedback signals.

Abstract: An oscillation frequency control device which comprises a voltage control local oscillator; a generator for giving forth an output having a predetermined referential frequency; means for periodically generating a gate pulse whose time width is equal to an integral multiple of the period of an output signal from said generator; a gate circuit for permitting the passage of an output signal from the local oscillator only during the time width of said gate pulse, wherein, while the local oscillator continues oscillation at a desired frequency, the number k of waves running through the gate circuit is chosen to be equal to an integral multiple of the counting capacity or the scale type n of a counter; said n-scale counter counts signals which have traveled through the gate circuit in at least one cycle for each supply period of the gate pulse, starting with the prescribed count at which said counter is initially reset; a count obtained in the final cycle is changed into an analog signal; comparison is made between