With Intermittent Comparison Controls Patents (Class 331/14)
  • Patent number: 4679004
    Abstract: A frequency synthesizer comprises a voltage controlled generator (11) for generating an output signal of a desired frequency in response to a control signal and a reference signal generator (13) for generating a reference frequency signal. The output signal is sampled (21) by the reference frequency to produce a sampled signal. The reference frequency signal is frequency divided (22) by a division factor determined by the desired frequency and the reference frequency. The sampled signal and the divided signal are compared (15) in phase and frequency and the control signal is produced depending on the phase difference between the two signals. For the division factor, two different values are determined by the desired frequency and the reference signal and one of the two values is selected according to a selection pattern determined by the reference frequency and the desired frequency.
    Type: Grant
    Filed: September 2, 1986
    Date of Patent: July 7, 1987
    Assignee: NEC Corporation
    Inventors: Atsushi Takahara, Tomoyoshi Ishikawa, Hiroyuki Tanaka, Tamio Okui
  • Patent number: 4677394
    Abstract: A method for calibrating an adjustable frequency generator having a voltage-controlled oscillator which is preceded by a computer via a digital-to-analog converter. The control input of the oscillator is coupled to a calibrating device comprising a series circuit comprising a digital phase detector and a lowpass filter forming a phase-locked loop circuit arrangement. By the computer, a digital-to-analog converter is caused, upon a frequency reference value signal, to deliver a control voltage to the oscillator which corresponds to the output voltage of the lowpass filter prior to the start of the calibrating process. A digital value corresponding to the control voltage is stored in the computer together with a digital reference value corresponding to the given frequency.
    Type: Grant
    Filed: July 21, 1986
    Date of Patent: June 30, 1987
    Assignee: Siemens Aktiengesellschaft
    Inventor: Hans-Ulrich Vollmer
  • Patent number: 4673892
    Abstract: A frequency synthesizer applicable to a radio communication equipment includes a phase comparator adapted to produce a voltage representative of a difference in phase between outputs of a variable and a fixed frequency dividers. The output of the phase comparator is applied through a switch and a low pass filter to a voltage controlled oscillator. A reset circuit produces a reset signal interlocked with a power source of the synthesizer. The variable and the fixed frequency dividers are reset by the reset signal while the switch is closed after the generation of the reset signal and opened upon turn-off of the power source.
    Type: Grant
    Filed: May 7, 1986
    Date of Patent: June 16, 1987
    Assignee: NEC Corporation
    Inventors: Hideo Miyashita, Shigeo Yoshihara
  • Patent number: 4668922
    Abstract: A phase-locked frequency synthesizer (10) having a voltage controlled oscillator (40), a divider circuit (60), and a sample-and-hold phase detector (30, 80, 90, 100, 110) which utilizes gain compensation (90,110) for optimizing phase-locking speed. The sample-and-hold circuit (FIG. 6) also includes circuitry for substantially reducing perturbations at its output. The frequency synthesizer further includes control circuitry (70) and a reference frequency generator (20) for quickly reinitializing the synthesizer in response to a command to change frequency.
    Type: Grant
    Filed: July 17, 1985
    Date of Patent: May 26, 1987
    Assignee: Hughes Aircraft Company
    Inventors: James A. Crawford, Gary D. Frey
  • Patent number: 4667169
    Abstract: In an improved phase-locked loop frequency synthesizer, a voltage is continuously applied from a power source to a fixed divider and a programmable divider respectively composed of such lower electric power consuming means as C-MOS circuitry such that the fixed and programmable dividers preserve the counting value thereof when their inputs are interrupted at the time of changing from a phase-locked loop to an open loop so that phase lock is achieved in a short time with less consumption of electric power.
    Type: Grant
    Filed: July 10, 1986
    Date of Patent: May 19, 1987
    Assignee: NEC Corporation
    Inventors: Takashi Matsuura, Yukio Fukumura
  • Patent number: 4647873
    Abstract: An apparatus and method for generating an output signal having portions thereof being linearly swept in frequency. A controller, responsive to external signals, generates a series of control signals. An oscillator, responsive to each one of the control signals, produces an output signal. The output signal includes a series of output waveforms each linearly swept in frequency and corresponding to a respective one of the control signals. A first servo, responsive to each one of the output waveforms, produces a series of first correction signals each dependent upon the linearity error in a corresponding one of the output waveforms. The first correction signals modify a corresponding control signal as applied to the oscillator so as to correct linearity errors occurring in a corresponding one of the output waveforms. A second servo, responsive to each one of the first correction signals, produces a series of second correction signals each dependent upon the correlations in the first correction signals.
    Type: Grant
    Filed: July 19, 1985
    Date of Patent: March 3, 1987
    Assignee: General Dynamics, Pomona Division
    Inventors: Frederick L. Beckner, Garry N. Hulderman, Darrell K. Ingram
  • Patent number: 4634998
    Abstract: A phase-locked frequency synthesizer (10) having a voltage controlled oscillator (40), a divider circuit (60), and a sample-and-hold phase detector (30, 80, 90, 100, 110) which includes sample-and-hold circuitry (FIG. 6) having variable efficiency. Specifically, the sample-and-hold circuitry provides a sampling pulse of variable width which is controlled to be wider during acquisition and narrower during steady-state operation.
    Type: Grant
    Filed: July 17, 1985
    Date of Patent: January 6, 1987
    Assignee: Hughes Aircraft Company
    Inventor: James A. Crawford
  • Patent number: 4633193
    Abstract: Synchronization of a local timing signal with an incoming reference timing signal is realized by employing a frequency estimator and frequency synthesizer in conjunction with a local fixed oscillator. The frequency estimator includes a first phase-locked loop including an integrator for generating a frequency estimate which is the difference between the frequency of the incoming reference timing signal and the frequency of the fixed oscillator signal. The phase value of the frequency estimate obtained by integrating the frequency estimate is supplied to a second phase-locked loop which includes a digitally controlled oscillator to generate the local timing signal. If the incoming reference timing signal is lost or if there is too large a variation in a phase error signal in the first phase-locked loop, the value of the frequency estimate is held constant. Consequently, the second phase-locked loop never free runs and the local timing signal remains in synchronization with the reference timing signal.
    Type: Grant
    Filed: December 2, 1985
    Date of Patent: December 30, 1986
    Assignee: AT&T Bell Laboratories
    Inventor: Dominick Scordo
  • Patent number: 4631496
    Abstract: A frequency synthesized transceiver capable of tuning to a plurality of communication channels is disclosed. The transceiver includes a receiver and a transmitter section which are coupled to the synthesizer which generates the appropriate injection signals to achieve tuning. A battery saving circuit generates a battery saving signal having a predetermined duty cycle and period and is responsive to the phase detector in the synthesizer to disrupt power to the synthesizer while maintaining precise tuning. The battery saver circuit is also responsive to the transceiver. In a normal receive operation, a battery saving circuit synchronizes its battery saving signal with the hold condition of the phase detector to disrupt power to selected modules in the synthesizer without altering the injection frequency of the receiver. In a standby mode, power is disrupted to all modules in the receiver, the selected modules in the phase locked loop and the voltage controlled oscillator.
    Type: Grant
    Filed: December 13, 1985
    Date of Patent: December 23, 1986
    Assignee: Motorola, Inc.
    Inventors: Jaime A. Borras, Jose I. Suarez
  • Patent number: 4626797
    Abstract: In the disclosed phase-locked loop circuit, a phase detecting circuit produces a control signal for controlling the frequency of an oscillator according to the phase difference between the output of the oscillator and an input signal. The control signal controls the oscillator only during a specific period of time in which there is a phase difference. This eliminates the need for a low pass loop filter and results in a quick response, stable phase-locked loop circuit.
    Type: Grant
    Filed: October 11, 1984
    Date of Patent: December 2, 1986
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tsuguhide Sakata
  • Patent number: 4625180
    Abstract: A frequency synthesizer having an intermittently operated PLL circuit in which power is intermittently applied to a prescaler to reduce power consumption. The PLL circuit is operated such that fluctuations in the frequency synthesizer output frequency do not occur. This stability in the output frequency results from selectively providing signals to the phase comparator within the PLL circuit only during a time period beginning after power is applied to the prescaler and ending before power is removed from the prescaler.
    Type: Grant
    Filed: December 24, 1985
    Date of Patent: November 25, 1986
    Assignee: Fujitsu Limited
    Inventors: Eiji Itaya, Takeshi Takano, Takaharu Nakamura
  • Patent number: 4617527
    Abstract: A phase locking circuit for effecting pull-in of a phase locked loop to a desired frequency component even in the presence of spurious signals includes a phase locked loop, a scanning circuit and a control circuit. The scanning circuit generates a scanning current to the phase locked loop which activates a voltage controlled oscillator (VCO) therein, the VCO output being phase locked to an input signal by operation of the phase locked loop. The control circuit produces a periodic scanning restart signal causing the scanning circuit to periodically generate a second scanning current independent of the phase lock status of the phase locked loop until a phase lock to the desired frequency component is realized. The second scanning current functions to unlock a VCO output locked to a spurious signal.
    Type: Grant
    Filed: June 13, 1985
    Date of Patent: October 14, 1986
    Assignee: Pioneer Electronic Corporation
    Inventor: Ryuichi Naitoh
  • Patent number: 4616192
    Abstract: A phase-locked loop has a phase detector and a clock pulse oscillator. The phase detector multiplies a received reference signal by a comparison signal. It is constituted by a plurality of signal channels 207 each receiving the reference signal and having a cascade arrangement of a switching circuit 208 and a weighting network 209. The switching circuit is controlled by one or more sequences of main control pulses supplied by a pulse distributor circuit receiving clock pulses. Each signal channel has a constant weighting factor. For the k.sup.th signal channel the weighting factor is equal to the signal sample n(t.sub.o +kT.sub.s) of a fundamental signal n(t) which has a fundamental frequency f.sub.o. T.sub.s is the reciprocal of the clock pulse frequency f.sub.s. For each sequence of main control pulses controlling the switching circuit in the k.sup.th signal channel, this signal channel produces a main signal z(k, t). The main signals supplied by all the signal channels are added together.
    Type: Grant
    Filed: April 12, 1985
    Date of Patent: October 7, 1986
    Assignee: U.S. Philips Corporation
    Inventor: Arthur H. M. van Roermund
  • Patent number: 4613826
    Abstract: A variable frequency oscillator includes a RAM which stores a frequency setting data and provides a frequency control data, a VCO circuit which provides an oscillation output having a frequency which is defined by the contents of the frequency control data, a reference oscillator which provides a reference signal having a given frequency and phase, a phase comparator which detects the phase difference between the reference signal and a comparison signal corresponding to the oscillation output, and a logic circuit which combines the frequency control data with a phase data and provides the frequency setting data. The phase comparator provides the phase data whose contents indicate +1 if the phase of the comparison signal is delayed from the phase of the reference signal, indicate -1 if the phase of the comparison signal is advanced to the phase of the reference signal, and indicate 0 if the phase of the comparison signal matches with the phase of the reference signal.
    Type: Grant
    Filed: May 3, 1985
    Date of Patent: September 23, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akinori Masuko, Wataru Kuroiwa, Yasufumi Shimizu, Hideki Hirosawa
  • Patent number: 4602225
    Abstract: The present invention provides apparatus and a method for determining and correcting frequency offset for use in a frequency synthesizer to provide external control and DC frequency modulation of the synthesizer output frequency. The technique provides DCFM capability by unlocking a phase-lock loop (PLL) which provides the synthesizer reference frequency and making the PLL oscillator (VCO) tune line available for external inputs. Utilizing a frequency counting circuit, the exact output frequency of the VCO is determined. The desired VCO frequency is compared with the actual VCO frequency to derive an error signal proportional to any offset in the VCO frequency resulting from unlocking the PLL. The error signal is then utilized to compensate (the synthesizer output signal) for any frequency change as a result of unlocking the PLL.
    Type: Grant
    Filed: June 24, 1984
    Date of Patent: July 22, 1986
    Assignee: Hewlett Packard Company
    Inventors: Brian M. Miller, Charles R. Kogler
  • Patent number: 4600889
    Abstract: A coherent oscillator circuit which samples a signal responsive to phase and frequency of a transmitted pulse of radio frequency energy in an acquisition mode, and regenerates a signal corresponding to the sampled phase and frequency in a save mode is disclosed. A storage element performs the sampling in a relative fast, open loop manner during the acquiring mode. Then, during the save mode a phase locked loop forms which locks when a loop oscillator outputs a signal which corresponds to the sampled signal. The coherent oscillator forms a portion of a demodulator for a coherent-on-receive radar.
    Type: Grant
    Filed: March 13, 1985
    Date of Patent: July 15, 1986
    Assignee: Motorola, Inc.
    Inventor: Thomas W. Rugen
  • Patent number: 4600896
    Abstract: A phase comparator is included with each incoming channel to compare the clock phase of the incoming signal and a local oscillator. The phase comparator of an on-line active unit generates a signal to control the oscillator to maintain its output in phase with the incoming signal. The generated control signal is also connected to capacitor storage in associated channel phase comparators to provide them with an initial starting control voltage when they are switched in to be the receiving channels. Thus eliminating the uncontrolled operation of the oscillator during switching interval.
    Type: Grant
    Filed: September 25, 1984
    Date of Patent: July 15, 1986
    Assignee: GTE Communication Systems Corporation
    Inventor: Giuliano Cellerino
  • Patent number: 4598258
    Abstract: In a circuit arrangement comprising a power source circuit (12) and a phase detector (22), a phase difference signal (PD) is supplied to a first switch (31) repeatedly turned on and off during battery saving operation and to a second switch (32) initially turned on simultaneously with the first switch. First and second intermediate signals are sent through first and second low-pass filters (41, 42; 43, 44) as first and second modified signals (MO.sub.1 and MO.sub.2), respectively, to a voltage-controlled oscillator (25). A bidirectional nonlinear circuit (36, 37) becomes conductive and also sends the second modified signal to the voltage-controlled oscillator when the first intermediate signal becomes high. The voltage-controlled oscillator produces an oscillation signal with a high sensitivity on supply of both the first and the second modified signals and with a low sensitivity on sole supply of the first modified signal.
    Type: Grant
    Filed: June 24, 1985
    Date of Patent: July 1, 1986
    Assignee: NEC Corporation
    Inventor: Sotoaki Babano
  • Patent number: 4598257
    Abstract: A clock pulse generator system for providing a highly stable clock signal consists of two separate redundant clock signal generators which are controlled to operate in dead synchronization with each other. A microprocessor controlled digital phase lock loop operates to control each of the two clock signal generators and selects among a plurality of operating states such that the average dynamic phase difference in the two clock pulse signals generated is practically zero. Furthermore, the instantaneous dynamic phase difference does not exceed the phase noise of the voltage controlled crystal oscillators of the phase lock loops and, in one embodiment, is normally less than ten pico seconds, each phase lock loop comprising means for performing a fine, as well as coarse, phase comparison among internally or externally generated reference signals, only one of which is the highly stable clock signal output.
    Type: Grant
    Filed: May 31, 1983
    Date of Patent: July 1, 1986
    Assignee: Siemens Corporate Research & Support, Inc.
    Inventor: Gary D. Southard
  • Patent number: 4596963
    Abstract: A phase lock loop circuit comprises a variable frequency oscillator having a control input and an output, a divider having an input coupled with the output of the oscillator and an output coupled with the first input of a phase or frequency comparator. The comparator has a second input for a reference frequency (F.sub.REF) and an output coupled with the oscillator control input for providing a signal which is related to the difference in phase or frequency of the signals at the first and second inputs to effect phase locking of the oscillator to the reference signal. A detector provides a switching signal when the control signal falls outside a predetermined range and a switch in the phase lock loop is responsive to the switching signal to open the loop.
    Type: Grant
    Filed: July 13, 1984
    Date of Patent: June 24, 1986
    Assignee: Plessey Overseas Limited
    Inventors: Rodney J. Lawton, Peter W. Gaussen, Ian A. Strachan, Philip I. J. Ainsley
  • Patent number: 4583054
    Abstract: A frequency time standard monitoring system includes three highly accurate standards of substantially identical frequency. These three standards are compared in pairs by three monitoring apparatus. Each such apparatus includes a fine window detector for determining the phase relationship between the two applied frequency standard clock signals, and a phase shifter responsive to the fine window detector for shifting the phase of one of the signals until the signals are phase aligned. When this occurs, the fine window detector is disabled and a coarse window detector monitors the two clock signals to ensure that the clocks do not drift beyond tolerable limits. The output signal of the coarse window detector is applied, along with the corresponding signals from the other two monitoring apparatus, to a select logic which determines which standard should be on-line in the event of a fault detection.
    Type: Grant
    Filed: November 13, 1984
    Date of Patent: April 15, 1986
    Assignee: RCA Corporation
    Inventor: Philip C. Basile
  • Patent number: 4580107
    Abstract: The acquisition of phase lock to a reference frequency by a signal acquisition system is accomplished using a voltage controlled oscillator, a wideband frequency discriminator, a prepositioning circuit, and a phase lock loop. The voltage controlled oscillator is prepositioned within a loop bandwidth of the reference frequency by the prepositioning circuit and the wide band frequency discriminator which provide coarse tuning. The voltage controlled oscillator achieves phase lock with the reference frequency when it receives the fine tune signal from the phase lock loop. Using both the discriminator and the phase lock loop allows fast acquisition without the need to calibrate the voltage controlled oscillator. Since the discriminator pull-in range is much larger than the phase-lock loop bandwidth, the number of bits can be much smaller than in an acquisition circuit using a digital prepositioning circuit alone.
    Type: Grant
    Filed: June 6, 1984
    Date of Patent: April 1, 1986
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Stephen P. Caldwell, Martin J. Decker, Robert A. Jelen
  • Patent number: 4573024
    Abstract: A phase locked loop for bringing an oscillator (1) into phase with an incoming signal. In accordance with the invention there are means which on the one hand determine whether the phase difference between the oscillator output signal and the incoming signal is positive or negative and on the other hand in response thereto cause the oscillator (1) to emit either of two output signal frequencies, one of which is predeterminately higher while the other is predeterminately lower than the incoming signal frequency. The oscillator (1) is hereby brought into phase with the incoming signal when the former emits its two output signal frequencies alternatingly.
    Type: Grant
    Filed: July 22, 1983
    Date of Patent: February 25, 1986
    Assignee: Telefonaktiebolaget L M Ericsson
    Inventor: Bengt R. Carlqvist
  • Patent number: 4567447
    Abstract: To adjust the free running frequency of a voltage controlled oscillator so that it is close enough to a target frequency for a phase locked loop to lock the frequency, a reference signal is derived from a stable external source. A derived signal is generated from the oscillator. The derived signal and the reference signal are applied to a comparison circuit which examines the relationship of a specific edge of the reference signal at times determined by the signal derived from the oscillator. If the oscillator is within its proper frequency range, the edge of the reference signal will have a certain relationship to the times determined by the derived signal. If this relationship is found to be improper, correction signals are applied to the oscillator. In the preferred embodiment, this occurs in a television receiver where the reference signal is based on a 3.58 megahertz signal. The examination which is made takes an output from a counter which divides by 455, specifically, the 160 count.
    Type: Grant
    Filed: June 3, 1983
    Date of Patent: January 28, 1986
    Assignee: Zenith Electronics Corporation
    Inventors: Gopal K. Srivastava, Ronald B. Lee
  • Patent number: 4565975
    Abstract: Transmission lines for digital signals may include a large number--for example, several hundred--of intermediate generators. In this case, telemetering units are provided at the end points and at intermediate points, by means of which the digital telemetry signals are generated and sent over the transmission lines together with the digital information signals. In the event of interference, a problem arises, due to the fact that the telemetry signal that is needed to identify the interference is only available after a comparatively long time. Therefore, according to the invention, a method is recommended for the initial synchronization, at bit rate, of the pulse generators which generate the bit pulse in the telemetering units. The pulse generation is accomplished with a phase-control loop which generates a signal pulse with a comparatively high frequency.
    Type: Grant
    Filed: February 27, 1984
    Date of Patent: January 21, 1986
    Assignee: Siemens Aktiengesellschaft
    Inventors: Peter Gegner, Friedemann Vollnhals
  • Patent number: 4564819
    Abstract: A phase detecting apparatus comprises a first PLL and a second PLL having a response time shorter than the response time of the first PLL. An AC voltage signal produced by the first PLL which is in phase with the detected AC voltage except until the expiration of the response time of the first PLL after an abrupt change in the phase of the detected AC voltage is normally applied to the second PLL. Until expiration of the response time of the first PLL after rising of the detected AC voltage to a certain level, the detected AC voltage is applied, in place of the AC voltage signal produced by the first PLL, to the second PLL. The second PLL provides a digital signal indicative of the phase of the detected AC voltage.
    Type: Grant
    Filed: November 20, 1984
    Date of Patent: January 14, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Syunichi Hirose
  • Patent number: 4563657
    Abstract: In one aspect the invention features a digital synthesizer having clock circuitry to provide a clock pulse train, synthesizer circuitry to provide a synthesized pulse train at a frequency such that multiple clock pulses occur between pairs of successive synthesized pulses, and phase control circuitry to cause an effective shift in the synthesized pulse train frequency by causing, between pairs of successive synthesized pulses, a number of phase shifts in the clock pulse train.
    Type: Grant
    Filed: March 15, 1982
    Date of Patent: January 7, 1986
    Assignee: Codex Corporation
    Inventors: Shahid U. H. Qureshi, Yosef Linde
  • Patent number: 4542351
    Abstract: A phase-locked loop circuit, which obtains a signal synchronized with a phase of an input signal, including a synchronizing portion, and a data portion having a voltage controlled oscillator, a frequency phase comparator, a phase comparator, and a control circuit. The frequency phase comparator detects the phase difference and the frequency difference between the input signal and the output of the voltage controlled oscillator and the phase comparator detects the phase difference between the input signal and the output of the voltage controlled oscillator. The control circuit controls the voltage controlled oscillator, at least during a portion of the synchronizing signal portion, in accordance with the output of the frequency phase comparator, and, during the data signal portion, in accordance with the output of the phase comparator.
    Type: Grant
    Filed: September 8, 1982
    Date of Patent: September 17, 1985
    Assignee: Fujitsu Limited
    Inventor: Toshiro Okada
  • Patent number: 4536722
    Abstract: In a controlled signal generator or specifically a microwave frequency signal generator, which requires a quieting capacitor, improved switching speed without degrading noise performance is provided by switching out the quieting capacitor during frequency changes, precharging it to the new condition, and then reconnecting it for normal operation. Other error causing current drains are also compensated for.
    Type: Grant
    Filed: June 23, 1982
    Date of Patent: August 20, 1985
    Assignee: Giga-Tronics, Inc.
    Inventors: Lawrence A. Kaye, Robert Mayer
  • Patent number: 4528521
    Abstract: The subject invention is a precision controlled frequency synthesizer which is capable of precisely adjusting the frequency of an output signal to maintain a desired frequency difference between an input and output signal regardless of the stability of the frequency of an input signal. The synthesizer comprises the basic elements of a phase locked loop (PLL) type circuit. The PLL circuit portion detects the actual frequency difference, a value A, between the input and output signals. A reference source provides a desired frequency difference, a value D, which represents the frequency difference between a stable input frequency and a desired output frequency. The difference between the frequency difference values A and D serves as the amount of adjustment to the frequency of the output signal. This adjustment represents the amount of compensation necessary to maintain a specified frequency relationship between the input and output signals.
    Type: Grant
    Filed: February 9, 1984
    Date of Patent: July 9, 1985
    Assignee: AT&T Information Systems Inc.
    Inventor: Gary J. Grimes
  • Patent number: 4528523
    Abstract: An improved circuit for rapidly locking the phase of a reference signal e.sub.r of frequency f.sub.r with the phase of a signal e.sub.VCO in a phase locked loop which comprises a voltage controlled oscillator (VCO) for generating the signal e.sub.VCO of frequency f.sub.VCO, a divide-by-N circuit, for dividing f.sub.VCO by a variable N, a frequency/phase detector responsive to the phases of e.sub.VCO and e.sub.r to supply a control signal e.sub.c to the VCO, a loop filter circuit comprising a resistor and a capacitor for filtering e.sub.c, and logic for changing N to a new value N' in a time interval not less than T. Also provided is a circuit responsive to each change of N for coarse tuning the control signal supplied to the VCO and comprising a voltage generator responsive to each new value N' of N for generating a coarse tuned voltage having a magnitude which, when applied across the capacitor, will change the frequency f.sub.VCO /N to f.sub.VCO /N' to approximate f.sub.r.
    Type: Grant
    Filed: December 20, 1982
    Date of Patent: July 9, 1985
    Assignee: RCA Corporation
    Inventor: Albert T. Crowley
  • Patent number: 4523157
    Abstract: An improved PLL frequency synthesizer for producing a signal of frequency f.sub.T -f.sub.IF or f.sub.T +f.sub.IF is provided with a detection-control circuit which detects from the voltage applied to a voltage controlled oscillator (VCO) in the PLL that the VCO frequency reaches an upper or lower limit frequency and upon the detection forces the VCO to fall into the capture range. The improved PLL frequency synthesizer can acquire lock even if it has been thrown out of the capture range.
    Type: Grant
    Filed: September 24, 1982
    Date of Patent: June 11, 1985
    Assignee: Nippon Kogaku K. K.
    Inventor: Yu Sato
  • Patent number: 4523150
    Abstract: One of two capacitors in a phase comparator is discharged for a logic zero data input and is alternately charged with opposite polarities, depending on the state of a regenerated clock signal, for a logic one data input. The resultant charge of the capacitor when the data input again becomes zero is used to control a variable frequency oscillator which produces the clock signal, while the other of the two capacitors is discharged and then charged in the same manner. A phase locked loop including the phase comparator can accommodate arbitrary data sequences of a return-to-zero data signal and does not require a low pass filter.
    Type: Grant
    Filed: September 27, 1982
    Date of Patent: June 11, 1985
    Assignee: Northern Telecom Limited
    Inventor: John G. Hogeboom
  • Patent number: 4521918
    Abstract: An arrangement for reducing the amount of battery supplied power to a high frequency synthesizer. The phase-locked loop section of the synthesizer is periodically disconnected from the battery supplied power. In order to prevent substantial drift of the phase-locked loop during such power interruption, a control signal is provided for maintaining the VCO frequency. By minimizing the frequency drift, the loop can be re-locked in a short period of time following each power interruption.
    Type: Grant
    Filed: November 10, 1980
    Date of Patent: June 4, 1985
    Assignee: General Electric Company
    Inventor: Richard F. Challen
  • Patent number: 4517531
    Abstract: A modulated signal level detecting circuit comprising a synchronized detector 1 of the modulated input signal, a phase-locked loop 5, 14, 16 connected to the input signal for providing a reproduced carrier wave of the input signal, a switch 21 included in the phase-locked loop, and a signal level detecting circuit 22, 23 for detecting the level of the unmodulated signal and opening the switch and thereby breaking the loop when this level exceeds a fixed limit.
    Type: Grant
    Filed: January 5, 1982
    Date of Patent: May 14, 1985
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Yoichi Tan, Fumio Miyao
  • Patent number: 4511859
    Abstract: A circuit for generating a common signal as a function of either of two reference signals comprises a pair of phase-locked loops which share an oscillator. Each phase-locked loop generates a control signal as a function of one of the reference signals. One or the other of the control signals is coupled to the oscillator which generates the common signal. A comparator compares the two control signals and generates a signal indicative of their difference. While the control signal generated by the first phase-locked loop is coupled to the oscillator, the difference signal is applied to the second phase-locked loop where it controls the generation of the second control signal to minimize the difference between the two control signals. While the control signal generated by the second phase-locked loop is coupled to the oscillator, the second phase-locked loop is nonresponsive to the difference signal.
    Type: Grant
    Filed: August 30, 1982
    Date of Patent: April 16, 1985
    Assignee: AT&T Bell Laboratories
    Inventor: Leonard C. Dombrowski
  • Patent number: 4510462
    Abstract: A frequency disturbance minimization circuit for use in a phase locked loop circuit. A pulse generator eliminates random phase shift, which occurs after a reference clock outage, by synchronizing counted down derivatives of the local and reference clock circuits. A window circuit provides a signal representative of the difference in phase between these local and reference clock circuits. A counter accumulates these phase difference window signals for periodic interrogation by a microprocessor which causes a voltage controlled oscillator to adjust its frequency in the direction necessary to eliminate this phase difference.
    Type: Grant
    Filed: June 23, 1983
    Date of Patent: April 9, 1985
    Assignee: GTE Automatic Electric Inc.
    Inventors: Ivan L. Edwards, Robert C. McLaughlin, Max S. Macrander
  • Patent number: 4503400
    Abstract: A frequency disturbance minimization circuit for use in a phase locked loop circuit. A pulse generator eliminates random phase shift, which occurs after a reference clock outage, by synchronizing counted down derivatives of the local and reference clock circuits. A window circuit provides a signal representative of the difference in phase between these local and reference clock circuits. A counter accumulates these phase difference window signals for periodic interrogation by a microprocessor which causes a voltage controlled oscillator to adjust its frequency in the direction necessary to eliminate this phase difference.
    Type: Grant
    Filed: June 23, 1983
    Date of Patent: March 5, 1985
    Assignee: GTE Automatic Electric Inc.
    Inventors: Ivan L. Edwards, Robert C. McLaughlin, Max S. Macrander
  • Patent number: 4498059
    Abstract: A frequency disturbance minimization circuit for use in a phase locked loop circuit. A pulse generator eliminates random phase shift, which occurs after a reference clock outage, by synchronizing counted down derivatives of the local and reference clock circuits. A window circuit provides a signal representative of the difference in phase between these local and reference clock circuits. A counter accumulates these phase difference window signals for periodic interrogation by a microprocessor which causes a voltage controlled oscillator to adjust its frequency in the direction necessary to eliminate this phase difference.
    Type: Grant
    Filed: June 23, 1983
    Date of Patent: February 5, 1985
    Assignee: GTE Automatic Electric Incorporated
    Inventors: Ivan L. Edwards, Robert C. McLaughlin, Max S. Macrander
  • Patent number: 4496912
    Abstract: Rapid lock or synchronization between a reference oscillator and a voltage controlled oscillator in a phase locked loop circuit is achieved by a synchronizing circuit. The synchronizing circuit senses the magnitude of the ramp signal produced by the phase locked loop circuit, and produces a blocking signal when the ramp signal exceeds a predetermined level. This blocking signal is applied to one of the oscillators to block that one oscillator pulse during the blocking signal, thus moving the two oscillator signals closer together more quickly, and thus providing lock or synchronization more rapidly.
    Type: Grant
    Filed: June 10, 1982
    Date of Patent: January 29, 1985
    Assignee: General Electric Company
    Inventor: Stephen R. Wynn
  • Patent number: 4494079
    Abstract: A digital counter is phased locked to a reference frequency by a voltage trolled oscillator which causes the counter to increase its count rate or decrease its count rate in accordance to the presence of a one or a zero on the most significant bit of the counter at the halfway point of one cycle of the reference frequency. The counter is reset at the end of the cycle of the reference frequency. A single microprocessor which can assess this most significant bit (MSB) and vary the oscillator output, can in this manner control any number of independent phase lock loop circuits.
    Type: Grant
    Filed: December 9, 1981
    Date of Patent: January 15, 1985
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: David O. Light, Jr., Frank Hayes, III, Joseph R. McGinty
  • Patent number: 4484152
    Abstract: A phase-locked loop having improved off-frequency detection. A variable frequency output signal is to be precisely locked to the frequency and phase of an alternating input signal. This is accomplished by alternately utilizing two feedback loops. A reference signal, having a frequency approximately equal to the frequency of the input signal is input to an initialization feedback loop in which it is mixed with the output signal. The initialization loop produces a feedback signal for controlling a voltage controlled oscillator which generates the output signal. An off-frequency detector detects the frequency difference between the output signal and the reference signal. When this frequency difference decreases below a predetermined level, the off-frequency detector disables the initialization feedback loop and enables a primary feedback loop.
    Type: Grant
    Filed: May 19, 1982
    Date of Patent: November 20, 1984
    Assignee: Westinghouse Electric Corp.
    Inventor: Ronald L. Lee
  • Patent number: 4470025
    Abstract: The starting frequency and sweep rate of a chirped frequency-shift-keyed oscillator are automatically controlled for correction of long-term drift. The substantially linear swept frequency output of the oscillator, during each of a successive multiplicity of swept frequency chirps, is counted and the count converted to an error signal utilized to control an appropriate potential in the oscillator circuit. The initial frequency is monitored, where the swept frequency range is small compared to the initial frequency, by counting the number of cyles during a chirp period in obtaining a first error signal from the total cycle count. The frequency-chirp ramp rate is monitored by counting the number of cycles during an initial portion, e.g.
    Type: Grant
    Filed: December 17, 1981
    Date of Patent: September 4, 1984
    Assignee: General Electric Company
    Inventor: Lewin T. Baker
  • Patent number: 4468632
    Abstract: An improvement in a frequency synthesizer comprising a voltage-controlled oscillator (VCO) for generating an output signal S.sub.VCO of frequency F.sub.VCO, a divider for dividing F.sub.VCO in division cycles with each division cycle consisting of the division of F.sub.VCO by N, Y times, and by (N+M), Z times, in an iterative manner to produce a divided output signal S.sub.N of frequency F.sub.N, where the division ratio is ##EQU1## and where N, Y, M and Z are integers, a reference signal generator for generating a reference signal S.sub.R of frequency F.sub.R, and a phase detector responsive to S.sub.N and S.sub.R to produce an output signal whose amplitude is representative of the phase therebetween. The improvement is a control circuit comprising logic for detecting and averaging the output signal from the phase detector during each division of F.sub.VCO in each division cycle to produce a d.c.
    Type: Grant
    Filed: November 30, 1981
    Date of Patent: August 28, 1984
    Assignee: RCA Corporation
    Inventor: Albert T. Crowley
  • Patent number: 4465982
    Abstract: A phase-locked loop provides an output frequency, locked to a multiple N of a reference frequency, responsive to a frequency-control voltage supplied to the output-frequency-generating voltage-controlled oscillator from the output of a differential amplifier. The differential amplifier inputs are provided with voltages sampled from the output of a pair of integrators respectively enabled for integration during complementary, and substantially identical, portions of the phase detector output waveform. Output-frequency-control voltage ripple is substantially reduced, with concomitant reduction of frequency modulation of the output freqeuncy, over the reference frequency period.
    Type: Grant
    Filed: February 18, 1982
    Date of Patent: August 14, 1984
    Assignee: General Electric Company
    Inventor: George Jernakoff
  • Patent number: 4464638
    Abstract: An improvement in a digital frequency synthesizer comprising a voltage-controlled oscillator (VCO) for producing a signal S.sub.VCO having a frequency f.sub.VCO, a first signal generator for generating a plurality of signals S.sub.AS having a spectrum of frequencies f.sub.AS, all exceeding a given minimum frequency f.sub.M, a mixer responsive to S.sub.VCO and to S.sub.AS to produce an output signal having a frequency (f.sub.VCO .+-.f.sub.AS), a divide-by-N divider responsive to (f.sub.VCO .+-.f.sub.AS) to produce a signal S.sub.N having a frequency f.sub.N, a second signal generator for generating a first reference signal S.sub.R1 having a frequency f.sub.R1, a phase detector responsive to S.sub.N and S.sub.R1 to produce a d.c. control signal E.sub.c whose amplitude varies with the phase relation of S.sub.N and S.sub.R1, and a filter for supplying E.sub.c back to said VCO, the VCO being responsive to E.sub.c to produce an output signal S.sub.VCO of frequency f.sub.VCO where (f.sub.VCO .+-.f.sub.AS )=Nf.sub.
    Type: Grant
    Filed: November 30, 1981
    Date of Patent: August 7, 1984
    Assignee: RCA Corporation
    Inventors: Albert T. Crowley, Robert M. Lisowski
  • Patent number: 4459560
    Abstract: First and second frequency signals are frequency converted by a frequency converter and the frequency-converted output and the output from a variable frequency oscillating means are phase compared by a digital phase comparator. The phase-compared output controls the variable frequency oscillating means, constituting a first phase lock loop of a wide capture range. The output from the variable frequency oscillating means is frequency converted by the first frequency signal and the converted output and the second frequency signal are phase compared by an analog phase comparator. By the phase-compared output is controlled the variable frequency oscillating means, constituting a second phase lock loop of a narrow capture range but a large loop gain. The output frequency of the variable frequency oscillating means is varied by changing the setting of the frequencies of the first and second frequency signals.
    Type: Grant
    Filed: January 15, 1982
    Date of Patent: July 10, 1984
    Assignee: Takeda Riken Kogyo Kabushikikaisha
    Inventor: Takenori Kurihara
  • Patent number: 4453136
    Abstract: An automatic frequency control system includes a frequency measuring unit (IFM), which produces a frequency quantity representing the frequency of its input signal, and a controllable-frequency signal generator (VCO), which produces an output signal whose frequency depends on a control signal supplied to its control input. In a normal mode of operation, IFM derives its input signal from an external source connected to an input terminal (T), and the system derives from the frequency quantity produced by IFM, a control signal for VCO, using a predetermined transfer characteristic, so that the output frequency of VCO is dependent on the frequency of the input signal to IFM, being, for example, equal to the frequency of the signal at T.
    Type: Grant
    Filed: October 13, 1981
    Date of Patent: June 5, 1984
    Assignee: U.S. Philips Corporation
    Inventor: Martin J. Kelland
  • Patent number: 4443769
    Abstract: A sampling PLL circuit features a frequency sweep caused by an offset voltage applied to an integrator to avoid false lock ups. At one end of the frequency range the polarity of the offset signal can be reversed. The error voltage can be sampled during a television vertical or horizontal blanking period. Once proper lock up is achieved, the offset signal can be removed.
    Type: Grant
    Filed: September 21, 1981
    Date of Patent: April 17, 1984
    Assignee: RCA Corporation
    Inventors: Felix Aschwanden, Willem H. Groeneweg
  • Patent number: 4437071
    Abstract: The device for controlling a local clock signal H both in frequency and in phase by means of a binary signal S comprises logical means for delivering two signals S.sub.1 and S.sub.3 representing respectively the sign of the phase difference and the sign of the frequency difference between the signals H and S. The signal H is generated by a voltage-controlled oscillator circuit, the control voltage of which is generated by a tuning control circuit as a function of the signal S.sub.1 when the frequency of the signal H is close in value to the desired frequency and as a function of the signal S.sub.3 when this is not the case.
    Type: Grant
    Filed: December 7, 1981
    Date of Patent: March 13, 1984
    Assignee: Thomson-CSF
    Inventor: Daniel Rougeolle