Abstract: A frequency synthesizer is composed of a reference oscillator, the first and the second integrators, a binary adder, a low pass filter and VCO forming a Phase Locked Loop (PLL). The first integrator, driven by the timing of a reference oscillator, integrates an externally supplied value K and generates the input signal. The second integrator, driven by the output signal of the VCO of the PLL, integrates an externally supplied value L. The binary adder detects the difference between the outputs of the first and the second integrators functioning as a phase comparator. The output of the phase comparator is converted into an analog voltage which is filtered to control the VCO to achieve frequency synthesis by the phase lock function of the loop.

Abstract: A phase locked loop (20) includes a standby control circuit (30) and recovers from standby with minimum lock time. A reference counter (21), a loop counter portion (22, 23) and a phase detector (24) are disabled in response to an activation of a standby signal. Both the reference counter (21) and the loop counter portion (22, 23) are enabled in response to a deactivation of the standby signal. A voltage controlled oscillator (VCO) (26) output signal is decoupled from an input of the loop counter portion (22, 23) in response to an activation of a loop counter output signal. The VCO output signal is next recoupled to the input of the loop counter portion (22, 23) in response to an activation of a reference counter output signal. Finally, the phase detector (24) is enabled. In one embodiment, the loop counter portion (22, 23) includes a prescaler (22) which does not have a separate reset input, and a separate loop counter (23).

Abstract: A frequency synthesizer circuit, having first and second modes of operation, comprises a voltage-controlled oscillator (VCO) (64), a low-pass filter (74), a phase-locked loop (PLL) (67), an analog-to-digital converter (50), a digital-to-analog converter (56), a controller (48), and a VCO input switch. During the first mode, the VCO input switch couples the control input of the VCO to a control signal produced by the PLL, and the analog-to-digital converter measures the control signal and provides it to the controller which stores the control voltage measured by the analog-to-digital converter. During the second mode, the VCO input switch couples the control input of the VCO to the digital-to-analog converter which applies the stored control to the control input of the VCO.

Abstract: A phase control circuit for controlling the relative phase of periodic components of two logic signals having the same frequency, and one of which periodic components has a pulse-duty factor different from 50:50, said circuit includes a signal source which provides a control signal for regulating the relative phase of the periodic components of said logic signals. The control signal has a first value for phase relationships in a predetermined range of values and a second value for phase relationships outside said range of values. A phase lock detector detects the lock status of the periodic components of the logic signals. Another signal source provides a third logic signal having a periodic component having the same frequency as the periodic component of each of the two logic signals and a pulse width substantially wider than that of the two logic signals.

Abstract: A phase locked loop including a switch between a phase detector output and a VCO input to open the PLL during a frequency change is provided. While the PLL is open, an analog error correction signal is generated by sampling any residual error coming from the phase detector, and generating the analog error correction signal to counter the residual error. Once analog error correction signal is available, the switch is closed and the error correction signal is added to the phase detector output and the PLL is allowed to settle to an optimized frequency.

Abstract: A multi-channel frequency synthesizer comprises first, second, and third phase-locked loop circuits. The loop gains of the second and third phase-locked loop circuits are set higher than that of the first phase-locked loop circuit. Furthermore, a phase adjustment circuit is provided in the first phase-locked loop circuit. The second phase-locked loop circuit is activated before changing the channel. During the channel switching operation, the third phase-locked loop circuit transforms the frequency quickly on the basis of an output of the second phase-locked loop circuit. After being switched to the first phase-locked loop circuit, the phase adjustment operation is carried out. Thus, this frequency synthesizer makes it possible to realize the speedy inter-channel frequency switching operation without causing deterioration in other characteristics such as S/N or C/N in the normal condition.

Abstract: An autoranging phase-lock-loop circuit compares an oscillator signal output from a range programmable voltage controlled oscillator, which generates the oscillator frequency within one of a plurality of operating ranges, to a reference signal and commands the voltage controlled oscillator to step to a next operating range if the voltage controlled oscillator cannot lock onto the reference signal within a prescribed time.

Abstract: A clamp circuit for use in a phase-locked loop clock circuit, the phase-locked loop including a phase detector with inputs for reference clock signal and oscillator signal, a loop filter with an input connected to the phase detector, and a voltage-controlled oscillator with an output connected to the phase detector, the clamping circuit connected between an output of the loop filter and an input of the voltage-controlled oscillator, the clamping circuit connected between the loop filter and the voltage-controlled oscillator. The clamping circuit selectively provides, under the control of a clamping signal either a path for the loop through the clamping circuit or clamping the input of the voltage-controlled oscillator to varying potential. The varying potential is provided by a resistor capacitor network. When the loop is closed the capacitor is charged to an average of the loop control voltage for the oscillator.

Abstract: A digital PLL circuit capable of stabilizing a phase comparison operation to largely reduce a jitter of an output signal, including a peak detection circuit for detecting a peak of an input signal level, a two-points sampling circuit for sampling two data points determined at a predetermined time interval in the peak to output two sample values, an inclination calculation circuit for calculating an inclination value from the two sample values, and a discrimination circuit for discriminating whether the inclination value is zero or either a positive or negative value to output a control signal for a VCO depending on the discrimination result.

Abstract: The frequency control and phase control of a voltage-controlled oscillator (50) of a phase-locked loop (100) comprise two current paths. The frequency control system comprises a filter (75) that converts pulse output current (i.sub.1) of a charge pump (70) generated by phase error signals (X.sub.1, X.sub.2) to a DC voltage, and a resistor (R.sub.1 or R.sub.2) that converts that voltage to DC current (i.sub.3), and the phase control system comprises a charge pump (80) that generates a pulse output current (i.sub.2) using the phase error signals (X.sub.1, X.sub.2). The frequency and phase of the oscillator output (V.sub.OUT) of the voltage-controlled oscillator (50) is controlled by a composite current i.sub.4, which is the sum of the DC current (i.sub.3) and the output current i.sub.2. Since it is possible to make the natural angular frequency proportional to the data transfer rate while the damping factor remains unchanged, by changing the value of the currents (i.sub.3, i.sub.

Abstract: This invention aims at providing a PLL synthesizer circuit that can shorten lock-up time while sufficiently securing a time constant of a low-pass filter, and has a structure wherein a phase comparator 3 outputs output signals .phi.R and .phi.P on the basis of a reference signal fr output from a reference frequency divider 2, and a comparison signal fp output from a comparison frequency divider 4; the output signals .phi.R and .phi.P are negatively fed back to the comparison frequency divider 4 through a charge pump 5, a low-pass filter 6 and a voltage controlled oscillator 7, and a lock detection circuit 8 outputs a lock signal LD when in a locked state.

Abstract: Disclosed is an apparatus and method for high speed tuning to a commanded frequency using a low noise high speed frequency synthesizer employing a learning sequence. A phase-locked loop (PLL) generates the commanded frequency. High speed tuning circuitry high speed tunes the PLL to the commanded frequency. Thereafter, the high speed tuning circuitry is substantially isolated from the PLL, while learning circuitry is employed to learn a correction signal which will enable subsequent more accurate high speed tuning to the commanded frequency.

Abstract: A divider synchronization circuit (11) that provides faster settling to a new frequency in a phase-locked loop frequency synthesizer (10) that uses a programmable divider (16) and a phase detector (17). The circuit (11) is adapted to stop the divider (16) while its program is being changed, and then restart the divider (16) on command. The startup time of the divider (16) is automatically adjusted such that the divider output is in phase with a reference input to a phase detector (17). The outputs of the phase detector (17) are also blanked during the time period that the divider (16) is stopped. The circuit (11) reduces the time required for the phase locked-loop frequency synthesizer (10) to settle to its new frequency and phase when the frequency is changed. The timing of the divider startup eliminates the large phase transient that may occur when the divider startup timing is random, thus shortening the time that must be allowed for the synthesizer output to settle to its final phase.

Abstract: The voltage-controlled oscillator in a phase-locked loop comprises a voltage-current converter (62) and a current frequency converter (34). The voltage-current converter (62) comprises a voltage differential-current converter (64), a current-current converter (66) and a current adder-subtracter (68). In the voltage differential-current converter (64), only the voltage fluctuation or difference .DELTA.V.sub.CN with respect to one-half a power supply voltage V.sub.DD /2, and not the absolute value of a control voltage V.sub.CN, undergoes current conversion as a control current I.sub.CN. Therefore, the center frequency of the oscillation frequency is not a factor of control voltage V.sub.CN and is controlled only by an offset voltage V.sub.B2. Accordingly, the center frequency can be independently set by changing offset voltage V.sub.B2. This is particularly significant in zone bit recording, which requires a wide frequency band.

Abstract: An apparatus is provided for synchronously selecting different oscillators as the system clock source. The apparatus is comprised of two oscillator selectors. Each of the oscillator selectors has as its inputs the output of each of the oscillators and a three-bit command code which indicates which of the oscillators is to be selected by the oscillator selector and a single clock output. A different oscillator may be selected by each of the oscillator selectors at the same time. The output of the oscillator selectors are inputs to the clock controller. The clock controller also receives command signals for controlling the switching of the clock controller between the outputs of the two oscillator selectors. The output of the clock controller is the clock source for the system and a status signal indicating which oscillator selector is presently being used.

Abstract: A receiver array in accordance with the reception principle of synchronous demodulation, in which a controllable oscillator array is pre-synchronized to a set value for the oscillator frequency by a digital first control circuit having a reference frequency source during a pre-synchronization phase, and a heterodyne signal derived from the oscillator frequency is then synchronized with phase locking to the received useful signal by switching the oscillator control input to an analog second control circuit.

Abstract: An oscillator control system includes a phase-locked loop having a programmable frequency divider operative within the loop. A switch is further included within the phase-locked loop to permit the loop to be open or closed in response to an input signal. A counter accumulates oscillator clock signal counts between each successive rising edge portion of the applied sync signal. A pair of shift registers sequentially store successive clock signal counts for the current and previous sync signal intervals. The output counts are compared for consistency by producing a difference signal therebetween which is utilized to control the phase-locked loop switch and close it once the consistency of sync signal has been established. The output counts of the shift registers are combined and used to provide a scaling factor which sets the frequency division of the programmable frequency divider within the phase-locked loop and properly scales the oscillator frequency to the sync signal frequency.

Abstract: In a frequency synthesizer, a first, variable frequency divider and a second frequency divider are activated in response to a periodic power activation pulse. The first frequency divider is driven by a voltage-controlled oscillator and the second frequency divider is driven by a reference frequency oscillator. A timing difference between the outputs of the first and second frequency dividers is detected and converted to a frequency-domain control signal for coupling to the voltage-controlled oscillator. Since the timing difference is converted to a frequency domain signal, the VCO is stabilized once there is a substantial frequency match between the first and second frequency dividers. Since the VCO can be stabilized thereafter, the frequency dividers can be deactivated when the detected timing difference is reduced to an acceptable value and are allowed to remain inactive until the synthesizer is activated again by the next activation pulse.

Abstract: A phase-locked-loop circuit for a radio transceiver operative to transmit and to receive modulated signals during nonconcurrent time periods. During time periods in which the radio transceiver is to generate and to transmit a modulated signal, the phase-locked-loop circuit is connected to the transmitter portion of the transceiver. During time periods in which the radio transceiver is to receive a modulated signal, the phase-locked-loop circuit is connected to the receiver portion of the transceiver. A switch, preferably comprised of a multiplexer, alternately connects the phase-locked-loop with the transmitter portion and the receiver portion of the transceiver.

Abstract: A voltage controlled oscillator (VCO), a frequency divider, a phase detector, and a loop filter are connected to form a phase-locked loop. The input line of the loop filter is branched into two. One branch is connected to the ground through a first resistor, a second resistor and a capacitor which are connected in series. The other branch is connected between the second resistor and the capacitor through a switch and a bypass resistor which are connected in series. The connection point of the first resistor and second resistor are connected to the VCO as the output terminal of the loop filter. When the switch is off, the bandwidth of the loop filter is narrow, and when the switch is on, the bandwidth of the loop filter is broad.

Abstract: A clock changeover apparatus including a reference frequency divider for dividing a reference clock by a first frequency division number; a comparative frequency divider for dividing by a second frequency division number an output clock obtained by the clock changeover apparatus; a phase comparator for comparing phase of a signal of the reference frequency divider with that of the comparative frequency divider; a clock controller for changing the output clock so as to make the phase of the signal of the reference frequency divider coincident with that of the comparative frequency divider; a clock determining member which gives an initial value of the output clock to the clock controller and is capable of selecting the initial value of the output clock arbitrarily; a changeover member for effecting changeover between the first and second frequency division numbers; and a phase lock detector for monitoring whether or not the phase of the signal of the reference frequency divider coincides with that of the compa

Abstract: A digital-to-analog converter--preamplifier apparatus serving as an interface between a source of digital audio signal data and an amplifier is disclosed. A digital stage receives multiple digital audio signal inputs, a selected one of which is analyzed by a digital audio interface receiver, processed by a digital signal processing device and a delta-sigma modulator prior to passing to the analog stage for conversion from the digital domain into left and right channel analog audio output signals. Volume control is performed on the audio signal in both the digital domain and the analog domain in order to optimize performance and minimize noise. The present invention automatically adjust for input word lengths of greater than 18-bits.

Abstract: The invention relates to a circuit arrangement for frequency synthesis with a phase control circuit (1) which comprises a first phase discriminator (3) for receiving a reference signal and an output signal supplied by a first frequency divider (6) with a division ratio k, a low-pass filter (4) coupled to the output of the first phase discriminator (3), and an oscillator (5) coupled to the output of the low-pass filter (4) for generating an output signal which can be supplied to the first frequency divider (6). At least one further branch (2) with a further phase discriminator (8) and a further frequency divider (9) which is to be released and which has a division ratio k is present. The further phase discriminator (8) coupled to the input of the low-pass filter (4) is designed for receiving the reference signal delayed by a delay element (10) and the output signal of the further frequency divider (9) provided for receiving the output signal of the oscillator (5).

Abstract: A device for the control of a phase-locked loop with frequency changing comprises an oscillator (10), a mixer (20) of signals, and a phase/frequency detector (40). The control device comprises a frequency comparator (60) to compare the frequency Fv of the signal given by the oscillator and the transposition frequency Fx, and an inhibiting circuit (70) sensitive to the frequency comparator and interposed between the mixer and the phase/frequency detector to block the beat frequency Fv-Fx at input of the phase/frequency detector. The disclosed device can be used to release the loop automatically during major changes in the loop control frequency F.

Abstract: A phase lock loop for a sector servo system. A servo phase lock loop oscillator provides the control timing function of the servo. Initially, the PLO is locked in frequency to a frequency reference obtained from a counter/timer in a digital signal processor (DSP) used to control the servo system. Subsequent to acquisition of the nominal operation frequency, the PLO is caused to lock in turn to gap and frame character markers derived from the digital information encoded into the servo burst. Transition between PLO reference sources is commanded by the microprogram running in the DSP, based upon microprogram assessment of servo PLO status. The PLO outputs timing control tags to the servo control logic and PES demodulator, a reference clock to the file read/write channel, and interrupt pulses to the DSP to synchronize DSP operation with the servo hardware, and initiate periodic DSP computation of the control algorithm.

Abstract: A frequency division scheme which offsets for a phase lag produced on initial power-on is described. A division ratio of a programmable counter is initially set at a first division ratio at the time of releasing the programmable counter from its reset state. When the first division cycle is complete, the division ratio is reset to its steady state value. Thus, a delay equivalent to the phase lag is produced. A frequency synthesizer is also proposed where the division ratio is set, and a phase difference is detected. Reset signals are continually set while the phase difference is changed. This cycle is continued until the phase difference is reduced to one cycle of the input signals or less.

Abstract: A frequency source (1) in, for example, a remote unit in a mobile communications system, is controlled to maintain a stable frequency signal. In normal operation, the frequency source (1) is frequency locked to an external reference frequency (10). A temperature detecting device (2) monitors the temperature of the frequency source, and information relating to temperature is stored in a storage device (7) together with information relating to control signals (6) applied to the frequency source (1). In the absence of the reference frequency (10), the temperature of the frequency source (1) is detected and the stored information is used to generate a control signal (6) to control the output frequency of the frequency source (1) in accordance with the detected temperature.

Abstract: A phase/frequency-locked loop (P/FLL) circuit for generating output signals synchronized with input signals in frequency and phase. The circuit includes a phase comparator which responds to the input signals and to the output signals to develop therefrom phase comparison signals in the form of positive or negative voltages corresponding to the phase differences between the input and output signals. A filtering circuit produces from the phase comparison signals a control signal for a voltage controlled oscillator (VCO) which produces in turn an oscillation signal having a frequency corresponding to the control signal. A phase controller responds to the control signal for the VCO as well as to the output oscillation signal thereof and produces the output signals in a form and wave shape which cause the control signal for the VCO to have a single voltage polarity. The P/FLL circuit of the invention reduces the time required to pull-in the frequency of the VCO and also expands the pull-in range.

Abstract: A monolithic phaselock loop circuit (PLL) for controlling the phase and frequency of a VCO to compensate for process induced variations in the VCO natural frequency and to extend the pull-in range by .+-.50% of the frequency of a reference clock. The PLL is comprised of a VCO, a digital phase comparator, a digital frequency divider and a digital sequential phase error detector (SPED). The SPED circuit comprises two up-down counters, one to control the phase; the other, the frequency; a first one-shot circuit that drives the phase up-down counter to detect every level transition of the reference clock and a second one-shot circuit that drives the frequency up-down counter to provide a pulse for every falling edge of the reference clock; and a shift register responsive to the phase comparator to store the value of the phase comparator thereby providing indication of a frequency lock between the reference clock and the VCO.

Abstract: A phase-locked loop having automatic internal phase offset calibration includes a voltage-controlled oscillator circuit for generating a recovered data signal in response to an error signal. A phase detector determines the phase difference between the recovered data signal and a reference data signal. The phase-locked loop further includes a charge pump circuit, coupled to the phase detector, for generating an error signal in response to the detected phase difference. The charge pump circuit includes first and second pump generators for respectively providing first and second sets of pump signals, with the pump generators being interconnected to facilitate generation of the error signal. The phase-locked loop is designed to alternate between operation in phase correction and phase calibration cycles. In each phase correction cycle an error signal is synthesized as described above on the basis of the most recent phase comparison.

Abstract: A phase-locked oscillation circuit system for dividing a clock whose frequency is an integral multiple of a signal produced by dividing the frequency of an input clock. While the input clock to the circuit is shut off, a phase comparator included in the circuit is supplied with a reference signal which is the signal being applied to the compare input of the comparator and the timing of which is modified by a small amount. The system protects the output of a voltage controlled oscillator and, therefore, the output clock of a phase-locked oscillation circuit thereof against disturbances ascribable to the shut-off and recovery of an input clock.

Abstract: A method to speed up the training of the output frequency signal (Out) of a frequency synthesizer circuit. The circuit comprises a voltage controlled oscillator (7) controlled by a filtered (6) feedback signal (Fb) output by a phase detector circuit (5) having a first input signal (Rs), which is produced by a reference counter (3) dividing an external reference signal produced by a reference oscillator (2), and a second input signal (Cs) produced by a programmable counter (4) dividing an output signal (Vs) from the voltage controlled oscillator (7). When the training process is started, the internal reference frequency of the first and second input signals (Rs, Cs) is simultaneously increased by a predetermined amount for a predetermined time.

Abstract: A PLL system having a variable oscillator and apparatus for generating both phase and frequency error signals for controlling the variable oscillator, includes apparatus, responsive to the polarity of the frequency error signal, to selectively disconnect the frequency error signal from the variable oscillator when the PLL system approaches phase lock.

Abstract: A phase-locked loop device for producing an output clock synchronized in phase with an input clock, wherein in addition to a loop responsive to the phase difference between an output clock of a controlled oscillator and the input clock for controlling the controlled oscillator, there is provided another loop for controlling the controlled oscillator in accordance with the frequency difference between the output clock of the controlled oscillator and a reference clock.

Abstract: A clock generator (30) dynamically generates a system clock in response to a high or a low frequency oscillator. An amplified oscillator input is provided to a first input of a multiplexor (62), a divider (56), and a comparator circuit (58, 60). Divider (56) divides an oscillator input frequency to provide a divided input to a second input of multiplexor (62). Comparator circuit (58,60) compares the input frequency with a reference frequency to determine whether the input frequency is high or low. If the input frequency is low, multiplexor (62) is enabled to provide the oscillator input as the system clock. If the input frequency is high, multiplexor (62) provides the divided input as the system clock. Additionally, comparator circuit (58,60) provides a control signal to enable an amplifier (50) to amplify the oscillator input using a high or low gain factor in accordance with the input frequency.

Abstract: A phase lock loop for a sector servo system. A servo phase lock loop oscillator provides the control timing function of the servo. Initially, the PLO is locked in frequency to a frequency reference obtained from a counter/timer in a digital signal processor (DSP) used to control the servo system. Subsequent to acquisition of the nominal operation frequency, the PLO is caused to lock in turn to gap and frame character markers derived from the digital information encoded into the servo burst. Transition between PLO reference sources is commanded by the microprogram running in the DSP, based upon microprogram assessment of servo PLO status. The PLO outputs timing control tags to the servo control logic and PES demodulator, a reference clock to the file read/write channel, and interrupt pulses to the DSP to synchronize DSP operation with the servo hardware, and initiate periodic DSP computation of the control algorithm.

Abstract: A phase-locked loop (PLL) clock generator circuit which is capable of changing the frequency of its outpt clock signal in a stable fashion. Selection of the frequency of the output clock signal is made by way of a selectable frequency divider coupled between the reference clock signal and an input of the PLL, with another frequency divider in the feedback loop of the PLL; each of these frequency dividers are selectable according to a signal on a select bus, translated by way of a ROM look-up table. The circuit also includes a multiplexer having a first input coupled to the PLL output, and a second input coupled to a stable clock signal, for example to the referenc clock signal or to the output of a fixed frequency PLL. The conrol input of the multiplexer is controlled by a state machine which monitors the select bus.

Abstract: An oscillation frequency control circuit which, while activating normal operation mode, initially computes a frequency control data corresponding to horizontal synchronizing signal by applying an interpolation on the basis of the frequency control data read from a memory and the frequency of horizontal synchronizing signal supplied to a display unit, and then, based on the computed result, automatically and internally controls the oscillation frequency of a horizontal oscillation circuit in accordance with the frequency of input horizontal synchronizing signal.

Abstract: A phase-lock loop for a swept synthesized source in which hysteresis, tuning nonlinearity, and drift over time and temperature of an oscillator incorporated into the swept synthesized source are compensated. The tuning current to the oscillator is initialized to zero to eliminate hysteresis effects. Then, the pretune current is set to produce the minimum operating frequency of the oscillator. Next, the main phase-lock loop is closed, and a low-frequency synthesizer is swept to in turn sweep the oscillator over a selected frequency span. If the selected frequency span extends over other frequency bands, the oscillator is swept to the maximum frequency of the present band and held at this frequency by a track and hold circuit. The main phase-lock loop is opened, the low-frequency synthesizer is re-initialized, the main phase-lock loop is again closed, and the low-frequency synthesizer is swept again. Each frequency band is crossed in a similar manner until the selected frequency span is swept.

Abstract: A phase lock loop (PLL) reduces output phase jitter by averaging an input clock signal and a delayed input clock signal. A control signal selects between the input clock signal and the delayed input clock signal for providing a reference clock signal for the phase lock loop. The output oscillator signal of the PLL is divided by a predetermined integer value for providing the control signal to select between the input clock signal and the delayed input clock signal. The PLL establishes phase lock to the input clock signal during a first state of the control signal. The PLL next establishes phase lock to the delayed input clock signal during a second state of the control signal such that the average value of the output clock signal of the PLL is substantially constant.

Abstract: The invention provides an arrangement for reducing waveform errors such as errors in phase or amplitude in output pulses produced by pulsed power output devices such as klystrons by generating an error voltage representing the extent of error still present in the trailing edge of the previous output pulse, using the error voltage to provide a stored control voltage, and applying the stored control voltage to the pulsed power output device to limit the extent of error in the leading edge of the next output pulse.

Abstract: An auto-tuning circuit for automatically adjusting the transfer function of an active filter for processing video signals. A voltage-controlled filter is used as active filter, for imparting a predetermined transfer characteristic to a signal having a component related to a television signal. The transfer characteristic can be adjusted in accordance with a voltage. The auto-tuning circuit comprises PLL section connected to the voltage-controlled filter, and switching circuit. The PLL section applies to the voltage-controlled filter a control voltage corresponding to the phase difference between a reference signal and an output signal obtained by passing the reference signal through the voltage-controlled filter. The switching section allows transfer of signals between the voltage-controlled filter and the PLL section for at least one of the horizontal blanking period and vertical blanking period of the television signal.

Abstract: A digital phase-locked loop comprises a phase comparator, a controllable oscillator whose output signal is compared with an input signal in the phase comparator, and a loop filter preceding the oscillator. The filter comprises a clocked input register for storing the last phase-measuring value of the phase comparator, and an integrator which comprises a clocked register whose output signal is fed back to the register input. When the input signal of the phase comparator is absent or disturbed, a switching signal is generated which immediately erases the input register in the loop filter and after whose appearance the register in the integrator of the loop filter is reset to zero within a limited number of clock cycles.

Abstract: A phase-lock circuit for controlling an oscillator includes a sampling gate that operates during a gate interval to pass transitions in a comparison signal derived from the oscillator to produce therefrom an oscillator-controlling error signal that is representative of the phase-error direction and magnitude of the substantially symmetrical relationship between occurrence of transitions in the comparison signal within the interval of the gate pulse.

Abstract: A frequency synthesizer phase locked loop includes a voltage controlled oscillator (VCO) providing a variable frequency signal, a reference frequency oscillator providing a reference frequency signal, a phase comparison circuit for comparing the phases of the variable frequency and reference frequency signals and providing an output signal to a loop filter, the output of the loop filter providing a frequency control signal to the VCO. The phase comparison circuit includes a digital phase detector providing an output signal on an output line coupled to a charge pump for providing a first output signal to the loop filter; and an analog phase detector including a sample and hold circuit, and a control circuit responsive to the variable and reference frequency signals for providing a signal for sampling to the sample and hold circuit, the sample and hold circuit providing a second output signal to the loop filter.

Abstract: A digital phase locked loop for correcting the phase of an output signal with respect to an input signal has a phase comparator for comparing the phases of the input signal and a feedback signal from a variable frequency oscillator. The output signal of the phase comparator representing the phase difference is integrated in a low pass filter. The output of the low pass filter is supplied to a switch which alternately selects between the output of the low pass filter and a zero level signal from a zero generator. The output of the switch is supplied to the variable frequency oscillator. The output signal of the variable frequency oscillator is returned to the phase comparator, so that the phase of the output signal from the variable frequency oscillator is synchronized with the phase of the input signal.

Abstract: In a high prrecision PLL circuit arrangement, a phase detecting circuit produces a detecting signal which is directly proportional to a phase difference between a horizontal synchronizing signal and a voltage-controlled oscillating signal. A loop filter circuit produces a delay signal for delaying a frequency control at a predetermined time constant in response to the detecting signal derived from the phase detecting circuit. A voltage-controlled oscillating circuit produces an oscillating signal having a frequency directly proportional to a voltage of the delay signal from the loop filter circuit. A non-linear circuit includes a non-linear element for changing at least one of an AC gain and a DC gain of the loop filter circuit, and prevents an erroneous capture phenomenon of the PLL circuit arrangement in response to the detecting signal from the phase detecting circuit.

Abstract: A phase-locked loop includes an oscillator controlled by means of a switching network and a microprocessor which generates, in response to the output of a phase detector, two groups of output signals. A first group (Q1 . . . QN) is for adjusting the frequency of the oscillator in steps by selectively switching in frequency determining elements, and a second group (P1 . . . PM) for feeding a pulse duration modulator. The pulse duration modulator produces a control signal for a frequency determining minimum element of the switching network. The control signal has a duty cycle indicative of the frequency determination contribution by the minimum element.

Abstract: A PLL synthesizer includes a voltage-controlled oscillator generating an output signal having a frequency based on a first signal supplied thereto, a PLL control circuit which generates a second signal based on the output signal and a set frequency, a lowpass filter having an input terminal and an output terminal, for filtering the second signal supplied through the input terminal to thereby generate the first signal supplied to the voltage-controlled oscillator through the output terminal, and a switch circuit which is coupled between the input and output terminals of the lowpass filter and which supplies the second signal directly to the voltage-controlled oscillator during a predetermined time when the set frequency is changed.

Abstract: A synchronizing circuit including an oscillator, a phase discriminator having a first input coupled to an input terminal of the circuit for receiving an incoming synchronizing signal, a second input for receiving a signal derived from the oscillator and an output for applying a control signal to a control input of the oscillator for controlling the frequency and/or the phase of the oscillator signal. To ensure that the action of the circuit is not disturbed when no signal is present at the input terminal of the circuit, the circuit includes an auxiliary circuit for reducing the difference between the signal at the output of the phase discriminator and a reference, the auxiliary circuit being active in response to a synchronizing signal detector at the output of the phase discriminator in the absence of the incoming synchronizing signal and inactive in the opposite case.