Abstract: A phase-locked-loop circuit configuration is described which eliminates the statistical nature of the acquisition process, thereby improving or decreasing the acquisition or lock-up-time of the loop. The circuit configuration is such that given an input signal, that occurs at time T.sub.0, the loop error signal is reduced to a level where the lock-up-time is substantially reduced and predictable to a degree of certainty heretofore unattainable. In addition, by eliminating the statistical nature of the acquisition process, lock-up-time becomes a function of controllable system parameters, such as bandwidth, gain and circuit time constants.

Abstract: A synchronized carrier recovery circuit for a PSK modulated signal includes a plurality of phase detectors supplied with the PSK input signal and phase shifted outputs from a voltage controlled oscillator. The detector outputs are rectified and alternately coupled to a pair of adders whose outputs feed a complimentary subtractor. The detector outputs are also converted to digital form and fed to an Exclusive OR circuit, whose output couples the appropriate subtractor outputs to the VCO to achieve phase locked synchronization.

Abstract: Phase detection in a phase lock loop circuit is performed by periodically sampling the A. C. carrier communication signal applied thereto in response to a sample timing signal having a periodic frequency twice that of the carrier and a polarity check signal which is indicative of the polarity of the communication signal at a predetermined interval prior to each sample timing signal, one polarity enabling a sample to be taken and the opposite polarity inhibiting it.

Abstract: In a phase locked oscillator (PLO), the frequency of a voltage controlled oscillator (VCO) is changed in response to error signals indicating the phase error between the individual pulses of a stream of input pulses and the output pulses of the PLO. The running of the PLO is temporarily interrupted whenever the phase error exceeds a predetermined amount, and is restarted in phase with the next input pulse from the stream of pulses. A residual part of the error signal causing the interruption is accumulated so that after each interruption the frequency of the oscillator is closer to the frequency of the input stream of pulses. The process is repeated as required until phase lock is achieved.