Abstract: The invention provides a demodulation PLL wherein: the first position of a switch, which is controlled by a control circuit, respectively connects the outputs of a mixer and a LP filter to high gain and low gain inputs of an oscillator when frequency signals at the inputs of the mixer have not converged sufficiently, i.e. during the PLLs tuning mode; the second position of the switch respectively connects the outputs of the mixer and the LP filter to the low gain and high gain inputs of the oscillator when the frequency signals at the inputs of the mixer and the signal levels on the input and output of the filter have converged sufficiently, i.e. during the PLLs demodulation mode.

Abstract: A charge pump in a phase locked loop is enabled only when a loop filter needs to be updated, thereby reducing the power consumption of the charge pump. The charge pump is enabled or disabled in response to an enable signal which is generated by a latch. The enable signal is activated by look-ahead signals which are activated in advance of either a pulse from a reference signal or a pulse from a variable signal so as to allow the charge pump to stabilize before providing the charge current to update the loop filter. Logic signals from a programmable divider and reference signal generator are used to generate the look-ahead signals. The charge pump is disabled by a reset signal from a phase-frequency detector after the loop filter is updated. The charge pump includes a current switch for generating source and sink charge currents in response to pump-up and pump-down control signals. A bias cell provides two reference signals to the current switch.

Abstract: A frequency locked loop (FLL) having an oscillator whose output frequency controls the amount of charge provided by a switched feedback capacitor to a charge integrator whose output voltage controls the frequency of the oscillator. A switched reference capacitor provides a charge to the charge integrator which is a function of a reference frequency, so that the oscillator output frequency is a function of a product of the reference frequency times a ratio of the capacitance of the reference capacitor to the capacitance of the feedback capacitor. Plural reference capacitors, each responsive to a respective reference frequency may be provided so that the oscillator output frequency can be related to the sums or differences of the reference frequencies, the ratios of capacitors, the ratio of the reference voltages or a fixed multiplication factor.

Abstract: An A/D converter performs sampling of a reproduced signal from a reading device in synchronism with a clock signal from a PLL circuit and outputs the sampled value to a binary circuit and a phase comparator. The phase comparator detects a change from a positive sampled value to a negative one or from the negative sampled value to a positive one (zero-cross) and outputs a phase error signal corresponding to the zero-cross to a frequency comparator. The frequency comparator outputs a frequency error sensed in reference to a variation of the phase error signal to a switch through a low pass filter. The switch outputs the frequency error to an adder only when the PLL is not in a lock state. The adder outputs a sum of the frequency error and the phase error to a VCO through a loop filter. The VCO generates the clock signal with a frequency corresponding to the sum and supplies it to the A/D converter.

Abstract: An error suppressing circuit (301) and method therefor for a phase locked loop (PLL) (300). According to one embodiment of the present invention, a transient condition, for example, a bandwidth switch, in the PLL (300) is detected. The PLL (300) is opened for a period of time (509) responsive to detecting the transient condition. The phase of a reference frequency signal (115) and the phase of a output frequency signal (116 or 117) are synchronized after a lapse of the period of time (509). The PLL (300) is closed responsive to the phase of the reference frequency signal (115) and the phase of the output frequency signal (116 or 117) being synchronized. The present envention advantageously reduces the length of time it takes for the PLL (300) to correct for the phase and frequency error generated by the transient condition, and is capable of operating with various types of PLLs.

Abstract: The capture range and stability of a phase locked loop are improved by adjusting the free running frequency of a voltage controlled oscillator in response to the output signal of the phase locked loop. The output signal is filtered and amplified, and then compared to a reference signal from the voltage controlled oscillator which is indicative of the free running frequency. A direct current level capture circuit compares the filtered and amplified output signal with the reference signal and generates a control signal which adjusts the free running frequency so as to equalize the output signal and the reference signal. The control signal is generated by sequentially and consecutively enabling a series of filter reset circuits. A switch control circuit controls two feedback paths between the phase detector and the voltage controlled oscillator. The first feedback path includes a low pass filter and is selected by the switch circuit for normal operation.

Abstract: A clock signal reproduction circuit including an A/D conversion circuit for converting an input RF analog signal with a restricted upper limit of a frequency band into a digital signal, a digital phase error calculation unit for digitally calculating a phase error of a digital signal converted in the A/D conversion circuit, a control voltage generating unit including a loop filter, a D/A conversion unit for outputting an analog control voltage signal based on the digital phase error calculated, and an analog voltage-controlled type oscillating circuit for outputting a reproduction clock signal having a frequency of at least 2 times the frequency of the input analog signal. The A/D conversion circuit uses the clock signal output from the analog voltage-controlled type oscillating circuit to convert the input analog signal into a digital format and output a reproduction clock signal from the analog voltage-controlled oscillating circuit.

Abstract: A biphase stable FPLL includes a lock switch, operated in response to a frequency lock condition, that forces a predetermined voltage on the input of the third multiplier to guarantee that the loop locks up in a phase that produces a desired polarity of demodulated signal. A frequency lock indicator operates the lock switch to force the predetermined voltage on the third multiplier irrespective of the actual lock up phase of the loop. If the lock up phase is wrong, the voltage reversal causes the VCO to slip 180.degree. in phase and the loop locks up in its other bistable state.

Abstract: In a phase synchronous circuit, a phase of a reference signal and a phase of a compared signal that corresponds to an oscillation signal output by an oscillator are compared with each other a phase comparison output signal which corresponds to a phase difference is fed to the oscillator via a filter so that the oscillator is controlled. A control circuit provided in the phase synchronous circuit causes an output value of the phase comparison output signal to vary nonlinearly in accordance with the phase difference.

Abstract: A phase lock loop of a synthesizer (143) is controlled by applying (506) modern optimal control techniques for a predetermined period in a computing engine (222), in response to an error being introduced into a signal of the phase lock loop, and by utilizing (510) classical control techniques for controlling the phase lock loop after the predetermined period.

Abstract: Disclosed is a digital PLL circuit which can permit voltage level conversion using pulse width modulation by a PWM circuit to thereby ensure lower consumed power and a lower implementation density even when the transitional change of the phase error signal is not constant. A phase error signal is obtained based on sample values acquired by sampling a read signal read from a recording medium, and an average phase error signal corresponding to the average value of this phase error signal is obtained. Then, this average phase error signal is sampled and held at a predetermined clock timing to acquire a sampled average phase error signal which is in turn subjected to pulse width modulation for each mentioned predetermined clock timing. A clock signal whose oscillation frequency corresponds to the average voltage level of the resultant pulse width modulation signal is produced as the aforementioned reproduction clock signal.

Abstract: A clock recovery phase locked loop system is described. One embodiment has a voltage controlled oscillator divider (the signal of which is compared with a REFCLK divider signal), a voltage stimulus input where a test voltage is applied, a time stimulus input where a digital input with appropriate pulse width is applied and a monitor (output) where the results of the measurement can be observed. A test system is included which applies a series of analog voltages to the voltage stimulus input. For each analog voltage, the test system apply a series of pulses to the time stimulus input. By monitoring (a) the level on the monitor output and (b) the time at which it switches, the VCO gain can be calculated. This allows a direct measurement of VCO gain (K.sub.v) using conventional automatic test equipment used to test digital logic or memory devices.

Abstract: An oscillator supplies a signal of adjustable frequency to drive power ultrasonic actuators. The oscillator frequency is varied and the phase between the voltage and current of the signal is continuously measured. A computer determines the sign of the variation in the absolute value of the phase in the course of successive sampling cycles of predetermined duration and produces therefrom frequency correction signals for the oscillator. A frequency correction is applied to the oscillator in the same direction as the frequency correction applied previously if the variation in absolute value of the phase is negative, and in the opposite direction if the variation in absolute value of the phase is positive. If the variation in absolute value of the phase is zero, a frequency correction of random sign is applied to the oscillator.

Abstract: A sampled phase locked loop is phase-locked with support from a conventional phase locked loop (PLL). The support value from the PLL is locked with the aid of a sample and hold circuit. The locked support value is summed together with the control signal from the sampled loop in order to control a controlled oscillator which can suitably be a voltage-controlled oscillator. Accuracy of the support values depend on the PLL's resolution. The sampled loop is coupled in without any signal being built up in the sampled loop's loop filter.

Abstract: A PLL circuit (401), including a VCO (420) having a trimming port (418) and a tuning port (416), a PLL controller (404), a variable voltage source (408), a voltage measuring circuit (426) and a multiplexer (412, 414, 428), performs automatic trimming of the VCO (420). The PLL circuit (401) accomplishes this by initiating a trimming mode that controls the multiplexer so that it couples the output of the PLL controller (404) to the trimming port (418), and the output of the variable voltage source (408) to the tuning port (416), thereby to phase lock the VCO (420) to the reference frequency signal (421). The PLL circuit (401) then measures, by way of the voltage measuring circuit (426), a voltage at the trimming port (418), switches the PLL circuit (401) to an operational mode, and then adjusts the variable voltage source (408) to be substantially equal to the voltage measured.

Abstract: An apparatus for acquiring tuning for a tuning frequency at a high speed. In a receiver, a tuning control unit holds inputted tuning frequency information at a designated address in accordance with a storage designation signal supplied from a control unit and controls the frequency of a VCO based on the tuning frequency information held at a designated address in accordance with a read designation signal supplied from the control unit. Further, in a frequency comparison loop including a frequency comparator for acquiring a frequency difference between a target tuning frequency and the VCO frequency, a count time setting circuit sets the count time for measuring the VCO frequency, and the count time is increased whenever measurement of the VCO frequency is repeated.

Abstract: A digitally controlled phase locked loop generates a derived clock signal that is frequency locked to a reference clock signal. The apparatus is comprised of a microcontroller, counter, digital to analog converter (DAC) and a voltage controlled crystal oscillator (VCXO) connected in a feedback loop arrangement. A frequency output derived from the VCXO periodically samples an incoming reference signal. The sampled count value is compared to an ideal count value associated with the same sampling time period. A microcontroller and software-based algorithm perform the phase comparison and loop filter operations of the phase locked loop (PLL).

Abstract: According to the preferred embodiment, an improved feedforward path is provided that improves the frequency response and reduces the output jitter of a phase-locked loop. Specifically, the frequency response is improved by providing a zero in the frequency response of the phase-locked loop by means of a feedforward path. The feedforward path delivers a feedforward charge to the oscillator of the phase-locked loop. According to the preferred embodiment, the feedforward path reorders the feedforward charge, such that the feedforward charge is stored and distributed equally across all the phase-locked loop output signal sub-cycles.

Abstract: Phase-locked loop (for signals having rectangular waveforms, comprising, in series, a phase detector, a control signal generator circuit having a loop filter, a controlled oscillator and an auxiliary circuit. The detector recieves a reference signal having a reference frequency from a reference source as first input signal. The detector recieves second and third input signals from the auxiliary circuit. The reference signal and the second input signal are compared by a first logic combination function to deliver a second combination signal. The second and third input signals are compared by a second logic combination function to deliver a second combination signal.

Abstract: A frequency-locked loop (100) employs a controllable oscillator (102) for generating an output signal having a frequency, optional sampler (104), coupled to oscillator (102), for sampling the frequency of the output signal, a divider (106), coupled to optional sampling circuit (104), for dividing the output signal frequency to generate a prescaled signal and a microprocessor (108), coupled between the divider 106 and oscillator (102), for comparing the prescaled signal to a reference signal and generating a control signal for correcting frequency shifts based upon the comparison. The control signal generated by microprocessor (108) is non-continuous. During that time when microprocessor (108) generates no control signals, power is removed from various frequency-locked loop circuitry.

Abstract: A loop circuit such as a delay lock loop or a phase lock loop includes circuitry for changing the strength of the lock after lock has been achieved. Before lock is achieved, the strength of the charge pump circuitry that controls the charge in the low-pass filter in the loop may be relatively weak. After lock has been achieved, the strength of the charge pump circuit may be increased so that the circuit can maintain its locked condition in a noisy environment.

Abstract: The clock multiplying phase locked loop includes components for selectively setting a center frequency of a voltage controlled oscillator (VCO) to bias the VCO for operation within a selected range of input frequencies. To this end, the VCO is configured to output a signal at a selected center frequency based upon a tuning current provided to the VCO. Initially, a voltage input of the VCO is set to a reference voltage and a feedback signal is generated. The feedback signal, perhaps divided by N, is input to a phase-frequency detector. The phase-frequency detector also receives a reference frequency signal having a frequency at the selected center frequency. The detector outputs an UP or DOWN signal indicating whether the feedback signal is greater or less than the reference frequency signal.

Abstract: A protective circuit for a phase lock loop ensures that the VCO does not initiate a runaway condition when outputting a signal having a frequency higher than the feedback divider can respond to. During normal phase lock operation, a counter keeps track of the PLL input signal and is reset by the feedback divider. In the runaway condition the counter is not reset and triggers a control signal to the VCO. A second counter can be used to keep track of the feedback divider output and to reset the first counter. When the first counter far outruns the second counter the control signal is triggered.

Abstract: A phase locked loop includes a voltage controlled oscillator (VCO) for generating output VCO pulses. A frequency divider divides the VCO pulses by a variable number to produce frequency divided pulses whose phase is compared with that of input reference pulses by a phase detector. An update pulse is produced by the phase comparator having a pulsewidth corresponding to the detected phase difference. A pulse generator generates a train of update pulses having a combined pulsewidth equal to the pulsewidth of the update pulse, with the update pulses being substantially equally distributed within each period of the reference pulses to produce low output ripple. The update pulses are integrated by a loop filter to produce a D.C. control voltage that controls the VCO to vary the frequency of the VCO pulses such that the phase difference is adjusted toward zero. The frequency divider comprises a binary counter and a controller that enable the frequency divider to divide by a number N that is not a power of 2.

Abstract: A novel phase synchronous circuit includes a phase comparator, a first loop filter being electrically connected to the multiplying phase comparator, a second loop filter being electrically connected to the first loop filter, a voltage control oscillator being electrically connected to the second loop filter, an inventor circuit having an input side being electrically connected to the voltage control oscillator and a switching circuit having two input terminals and a single output terminal. The input terminal is electrically connected to the voltage control oscillator. The input terminal is electrically connected to an output terminal of the invertor circuit. The output terminal is electrically connected to an output terminal and also to an input side of the multiplying phase comparator. An input terminal is also electrically connected to another input of the multiplying phase comparator.

Abstract: An improved phase locked loop utilizing control logic generated by a phase detector to eliminate sensitivity to uncorrelated noise when the loop is in lock.

Abstract: A control signal generation circuit is particularly suited for use in a phase lock loop circuit. The control signal generation circuit provides a control signal to a voltage controlled oscillator. The control signal is provided in response to a phase difference signal provided by phase comparator circuitry. Charge pump circuitry includes a primary current source that provides a primary current signal in response to the phase/frequency difference signal. A secondary current source provides a secondary current signal, also in response to the phase/frequency difference signal. The control signal generation circuit also includes filter circuitry. The filter circuitry includes a resistance element connected between a first input, which is connected to receive the primary current signal, and a second input, which is connected to receive the secondary current signal. A capacitance element, connected in series to the resistive element, is connected between the second input and ground.

Abstract: A PLL that enables smooth switching of loop bandwidth over a wide range. By switchably inserting a resistance between the output of a current-mode charge pump and a loop filter of the PLL, current sources of the charge pump are made to appear as voltage sources, and a suitably small trickle current may be obtained for wideband acquisition. During tracking, the resistance is bypassed, such that the current sources again function as current sources for narrowband tracking. More particularly, in accordance with one embodiment of the invention, a phase locked loop having a current-mode charge-pump loop filter including a current source is operated by, during narrowband operation, switching a resistive element into a current path of the current-mode charge-pump loop filter. The resistive element has a sufficient resistance to change an operating point of the current source on a V-I curve characterizing the current source.

Abstract: The present invention discloses a control algorithm of digital processing-phase locked loop(DP-PLL) for network synchronization to prevent phase-hit generated at the time of transition of the operation mode.

Abstract: A frequency synthesizer having two atomic frequency standard inputs that is adapted to provide seamless switching or transition between the atomic frequency standard inputs with no change in the synthesizer output phase and frequency. The synthesizer includes a multichannel phase comparison system, each channel adapted for handling an atomic frequency standard input, a digital phase lock loop, a digital to analog converter, and a voltage controlled crystal oscillator which provides the synthesizer output. The phase comparison system is adapted to continually monitor the integrity of the atomic frequency standard inputs and to continually estimate the phase differences between the two atomic frequency standard inputs. The phase difference is used to estimate the proper phase and frequency offset between the primary and secondary inputs.

Abstract: Based on a phase locked loop (PC1, CP1, VCXO) which receives an incoming data signal (DS) and generates a recovered clock signal (RC), in the event that this incoming data signal (DS) includes low frequency cycling, false phase locking can occur, consequently leading to impaired operation; in order to avoid this, according to the invention, there is also included a false locking detector (FLD) to which is applied the incoming data signal (DS) and the recovered clock signal (RC) and the output of, which is added in an adder circuit (ADD) to that coming from the first loop, for producing voltage pulses when both signals are not at the same frequency, provoking a non-locked state. Only when the frequency is correct, does the false locking detector (FLD) not alter loop operation.

Abstract: The invention provides an LSI with a built-in clock generator-controller which minimizes power dissipation of an entire system and reduces production of a skew between an external system clock signal and an internal clock signal.

Abstract: The present invention relates to a method of enhancing the noise Immunity of a phase-locked loop. The phase-locked loop includes a comparator and apparatus for inhibiting the action of the comparator on the phase-locked loop. According to the method, the inhibition is lifted during a main time window resulting from the intersection of a first time window derived from the input signal of the phase-locked loop, and of a second time window derived from the loop-return signal.

Abstract: A loop filter for a phase locked loop (PLL) circuit may include two operational amplifiers and switched-capacitors connecting the inverted input and output of the operational amplifiers, the switched-capacitors replacing resistors found in conventional loop filters for PLL circuits. The loop filter may be in a monolithic integrated circuit, and the PLL circuit may operate with a response time heretofore available only with individual (non-IC) components. Phase error due to amplifier offset may be reduced with offset nulling techniques.

Abstract: A PLL circuit is provided which has excellent quick response and noise resistance. A bias data memory circuit 7 previously stores frequency assignment data Da, for assigning the frequency of output signals S1 of VCO 1, as an address and the value, of a control voltage Vc corresponding to the assigned frequency, as bias data Db. A bias voltage production circuit 6 produces a bias voltage Vb of a voltage value provided by the bias data Db output from the bias data memory circuit 7. A switch control circuit 5 compares a phase difference voltage Vd, output from a phase comparison circuit 2, with the bias voltage Vb output from the bias voltage production circuit 6.

Abstract: A system and method for establishing the frequency of a voltage controlled oscillator ("VCO") within narrowly defined frequency bands. The resonant circuit of the VCO uses selectable elements, such as varactor diodes, to establish the operating frequency band. The control voltage of the VCO is varied within a voltage range to adjust the VCO output frequency. A phase detector compares the VCO output to a reference signal. If the phase detector determines that there is an imbalance between the VCO output and the reference signal, then it produces a signal which indicates whether the VCO frequency should be increased or decreased to match the reference signal frequency. If the control voltage is outside of the voltage range, then the system allows the operating frequency band to be changed by varying the number of selectable elements in response to the phase detector signal.

Abstract: A loop circuit such as a delay lock loop or a phase lock loop includes circuitry for detecting when the output signal of the low-pass filter in the loop has either risen to a voltage which is relatively close to the power voltage of the circuit or has fallen to a voltage which is relatively close to the ground voltage of the circuit. In either case the circuitry reverses the significance of the phase frequency detector output signals that control whether the output voltage of the low-pass filter rises or falls. Alternatively or in addition, the phase frequency detector may be reset. Coarser adjustments may be made to the loop circuit downstream from the low-pass filter in response to a recurrence of the low-pass filter output voltage reaching either of the detected voltages mentioned above.

Abstract: The invention provides a demodulation PLL wherein: the first position of a switch, which is controlled by a control circuit, respectively connects the outputs of a mixer and a LP filter to high gain and low gain inputs of an oscillator when frequency signals at the inputs of the mixer have not converged sufficiently, i.e. during the PLLs tuning mode; the second position of the switch respectively connects the outputs of the mixer and the LP filter to the low gain and high gain inputs of the oscillator when the frequency signals at the inputs of the mixer and the signal levels on the input and output of the filter have converged sufficiently, i.e. during the PLLs demodulation mode.

Abstract: A phase lock loop has a lock detection circuit, a phase comparator, a charge pump circuit, a low-pass filter, a variable delay circuit and a frequency divider. The lock detection circuit generates a lock detection signal when a phase difference between an input reference clock and an output of the variable delay circuit is smaller than a predetermined value in a first stage of the synchronization operation. The input and output of the variable delay circuit are connected in a loop responding to the lock detection signal to form a voltage controlled oscillator (VCO) and shift the phase lock loop into a second stage of the synchronization operation. An initial control signal for controlling the VCO in the second stage is obtained as a value of the variable delay circuit in the first stage before generation of the lock detection signal, thereby obtaining a higher-speed synchronization operation and low jitters in the output clock.

Abstract: A frequency detector of a phase-lock-loop circuit is used for measuring a frequency error between a frequency of an output signal of an oscillator and a frequency of a synchronizing signal. When the frequency error in each of 32 periods of the synchronizing signal exceeds a predetermined magnitude, the phase-lock-loop circuits begins operating in a coarse frequency correction mode. As long as the 32 periods have not lapsed, the phase-lock-loop circuit operates in an idle mode of operation and the oscillator is not corrected. As a result, during vertical retrace, when equalizing pulses occur, the phase-lock-loop circuit is not disturbed by a large frequency error.

Abstract: A method and system for operating a radiotelephone at reduced power provides for a deenergization of a receiver of the radiotelephone wherein the receiver, during periods of activation, receives a sequence of messages of a control channel, each message having a synchronization portion and a data portion which follows the synchronization portion. Included within the radiotelephone is signal processing circuitry synchronized by a synchronization portion of an individual one of the messages to permit a reading of data of the data portion of an individual one of the messages. A digital phase locked lop (DPLL) with phase adjustment capability enables operation of synchronization circuitry and the data reading circuitry. Electronic circuitry within the DPLL provides for inhibiting the phase adjustment function in response to the command of a controller of the radiotelephone subsequent to a reading of data and concurrently with a termination of power to the receiver.

Abstract: A phase-locked-loop circuit includes an oscillator having switched capacitors that are selectively coupled to a positive feedback path of the oscillator in a coarse frequency error correction mode of operation. When the frequency error is small, the circuit operates in a fine error correction mode without varying the selection of the switched reactive elements.

Abstract: A processor (PR) is connected to the output of a phase comparator (PK) in a phase-locked loop. The processor (PR) calculates the phase shift of an input signal (f.sub.E) within an observation time span (for example, .DELTA.t=0-T) from the phase difference (.DELTA..phi.) at the output of the phase comparator (PK) and the parameters of the phase-locked loop (FT1, PK, FI, VCO, FT2).

Abstract: A phase comparator circuit in which an output synchronized with the input signal may be accurately produced without producing a malfunction even in the absence of the synchronization signal, in which a detection unit 11 detects the phase information of an input signal, an error detection unit 12 detects the phase error with respect to the phase of the input signal, a switch 13 switches between the phase error from the error detecting unit and plural fixed values of the phase error +.DELTA..alpha. and -.DELTA..alpha.

Abstract: A clock signal generation circuit performs a stable operation with respect to both a high frequency input clock signal and a sufficient low frequency testing clock signal.

Abstract: A method and a device for changing the phase of a generated signal by a predetermined value in a device for frequency generation. In the device for frequency generation, the generated signal is phase-locked to a reference signal where non-integer multiples of the frequency of the generated signal may be phase-locked to the reference signal by changing the phase of each of the periods of the reference signal by a value which determines the frequency of the generated signal. The phase is changed by a phase-shifter. The change of the phase of the generated signal is made by controlling the phase-shifter so that no change of the phase of the reference signal is made during at least one period of the reference signal.

Abstract: A phase detector of a phase-lock-loop circuit measures a phase error between an output signal of an oscillator and a synchronizing signal. When a difference between the phase error that is measured in a pair of horizontal line periods exceeds a first magnitude, that is indicative of phase error inconsistency, the phase of the oscillator output signal is not corrected and the phase-lock-loop circuit operates in an idle mode of operation.

Abstract: A clock generating circuit generates 2n clocks (where n is a positive integer number) each having 1/2n frequency of a maximum baud rate of data bit-stream input and a phase difference of .pi./n between successive phases thereof, and simultaneously shifts the phases on the clocks ahead or behind until the phases between the clocks and corresponding data bits of the data bit-stream input are locked in quadrature, by comparing the phase of the clock with those of data bit-stream input and adjusting the phases of the clocks.

Abstract: In a phase-lock-loop circuit a frequency detector measures a frequency error between an oscillatory signal and a synchronizing signal in alternate horizontal line periods for generating a frequency error indicative signal. The frequency error indicative signal is applied to an oscillator for correcting the frequency error in other alternate horizontal line periods in a manner to prevent frequency error measurement and correction from occurring in the same horizontal line period.

Abstract: A phase-looked loop circuit with holdover mode is formed utilizing a primary and secondary phase-locked loop circuits. Each loop circuit comprises a phase detector, loop filter, VCXO and frequency divider. The secondary loop is configured such that its output is very stable. The primary loop is phase-locked on a received reference clock signal and the second loop is phase locked on the output of the primary loop. The scaled output of the secondary loop being parallel to the reference clock signal. If the incoming reference signal is interrupted or lost the circuit is switched to a holdover mode where the input of the primary loop is switched to the stable scaled output of the secondary loop. In holdover mode, the output of the primary loop is phase-looked to the stable output of the secondary loop. When the reference clock signal is reestablished, the input of the primary loop is switched back to the reference clock signal.