Tuning Compensation Patents (Class 331/16)
  • Patent number: 10419008
    Abstract: Methods and systems are provided for calibrating voltage-controlled oscillators (VCOs). frequency control information, relating to output frequency of a VCO, which varies based on changes in operational conditions, may be determined. The frequency control information enables indicating the output frequency within a range of allowable values for control inputs and a range of expected values based on the operational conditions. For each control input setting, calibration control information for a calibration voltage associated with a control input, may be determined, based on the frequency control information, with respect to the operational conditions, to generate a constant output frequency. The operational conditions may be assessed, and a calibration voltage corresponding to the assessed operational conditions may be determined.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: September 17, 2019
    Assignee: MAXLINEAR ASIA SINGAPORE PTE. LTD.
    Inventors: Hormoz Djahanshahi, Masoud Ghoreishi Madiseh
  • Patent number: 10374511
    Abstract: A scalable controller circuit that provides faster and simpler regulation of a DC-to-DC converter is provided. Unlike such prior techniques, preferred embodiments do not require any threshold-level generation circuitry or analog compensation circuitry. Preferred embodiments implement a simple control law that requires only a few digital gates. Preferred embodiments can therefore significantly reduce the overhead power consumption and area of the controller in DC-to-DC converters to new levels.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: August 6, 2019
    Assignee: The Regents of the University of California
    Inventors: Loai Galal Bahgat Salem, Patrick Mercier
  • Patent number: 10371800
    Abstract: Exemplary embodiments disclosed herein relate to a radar device. The radar device may transmit an RF oscillator signal to a radar channel and receive a respective first RF radar signal from the radar channel. The radar device may further generate a second RF radar signal. Frequency conversion circuits are also disclosed to down-convert the first RF radar signal and the second RF radar signal. An analog-to digital conversion unit may digitize the down-converted first RF radar signal and the down-converted second RF radar signal to generate a first digital signal and a second digital signal, respectively. A digital signal processing unit is disclosed to estimate a phase noise signal included in the second digital signal and to generate a cancellation signal based on the estimated phase noise signal. The cancellation signal is subtracted from the first digital radar signal to obtain a noise compensated digital radar signal.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: August 6, 2019
    Assignee: Infineon Technologies AG
    Inventors: Mario Huemer, Alexander Melzer, Alexander Onic, Florian Starzer, Rainer Stuhlberger
  • Patent number: 10313105
    Abstract: An illustrative digital communications receiver and a fractional-N phase lock loop based clock recovery method provide substantially reduced sensitivity to nonlinearities in any included phase interpolators. One receiver embodiment includes: a fractional-N phase lock loop, a phase interpolator, a sampling element, a phase detector, a phase control filter, and a frequency control filter. The phase interpolator applies a controllable phase shift to the clock signal from the frac-N PLL to provide a sampling signal to the sampling element. The phase detector estimates timing error of the sampling signal relative to the analog receive signal. The phase control filter derives a phase control signal for the phase interpolator which operates to minimize a phase component of the estimated timing error. The frequency control filter derives the frequency control signal in a fashion that separately minimizes a frequency offset component of the estimated timing error, reducing the interpolator's phase rotation rate.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: June 4, 2019
    Assignee: Credo Technology Group Limited
    Inventors: Xiang Gao, Haoli Qian
  • Patent number: 10298243
    Abstract: A system for determining a correction for an output value of a time-to-digital converter within a phase-locked loop is provided. The output value relates to a time difference between an input signal and a reference signal supplied to the time-to-digital converter. The system includes a digitally-controlled oscillator configured to generate a first signal independently from the output signal. The first signal has a first frequency different from an integer multiple of a reference frequency of the reference signal. The system further includes a frequency divider configured to generate the input signal for the time-to-digital converter based on the first signal. The input signal has a second frequency being a fraction of the first frequency. Further, the system includes a processing unit configured to calculate the correction using a distribution of output values of multiple time differences.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel IP Corporation
    Inventor: Thomas Mayer
  • Patent number: 10297134
    Abstract: An energy supply device comprises an analysis unit for determining a signaling information which indicates a state of operation of the energy supply device, and a communication interface for outputting said signaling information. The analysis unit is designed to detect an operating variable of the energy supply device; to set a characterization parameter; and to characterize the detected operating variable of the energy supply device as a function of the characterization parameter in order to obtain the signaling information.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: May 21, 2019
    Assignee: PHOENIX CONTACT GMBH & CO KG
    Inventors: Jochen Zeuch, Hartmut Henkel, Patrick Schweer
  • Patent number: 10284243
    Abstract: A frequency tuning apparatus includes: a frequency tuner configured to tune an oscillation frequency of an oscillator based on target information extracted from a mapping table in correspondence to a target frequency, and oscillation information collected from the oscillator; and a frequency compensator configured to compensate for a compensation error between the tuned oscillation frequency and the target frequency based on an offset table.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: May 7, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: SeongJoong Kim, Joonseong Kang, Seok Ju Yun, Young Jun Hong
  • Patent number: 10243572
    Abstract: A digital phased lock loop includes a digital controlled oscillator configured to produce an output signal at an output signal frequency, and a phase comparator configured to compare the output signal or a signal derived from the output signal, with a reference signal at a reference signal frequency or a signal derived from the reference signal to produce a phase error signal. A first loop filter produces a first control signal for the digital controlled oscillator. A frequency error measuring circuit produces a frequency error signal that directly represents a frequency difference between the output signal frequency and the reference signal frequency. A second loop filter produces a second control signal for the digital controlled oscillator from an output of the frequency error measuring circuit. A circuit combines the first and second control signals and providing the combined control signals to the digital controlled oscillator.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: March 26, 2019
    Assignee: Microsemi SoC Corporation
    Inventor: Prakash Reddy
  • Patent number: 10193686
    Abstract: Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: January 29, 2019
    Assignee: SUNRISE MICRO DEVICES, INC.
    Inventors: Mario Lafuente, Paul Edward Gorday
  • Patent number: 10164572
    Abstract: An oscillator module used with a plurality of power sources includes an oscillator unit, a clock monitor unit (CMU), a software module and a digital calibration circuit. The oscillator unit generates a clock signal. The CMU is coupled to the oscillator unit, determines whether an amplitude of the clock signal exceeds a predetermined threshold, and outputs an alarm signal if the amplitude of the clock signal is lower than the predetermined threshold. The software module is coupled to the CMU, and receives the alarm signal to output a calibration signal. The digital calibration circuit is coupled to the oscillator and the software module, and outputs a control signal in response to the clock signal and the calibration signal, adjusting the plurality of power sources to modify the clock signal.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: December 25, 2018
    Assignee: M2Communication Inc.
    Inventors: Yang-Wen Chen, Chun-Yi Lee, Derrick Wei
  • Patent number: 10164760
    Abstract: Systems and methods are disclosed for detecting and compensating for timing excursions in a data channel. If a signal contains discontinuities in phase, a detector of the channel may lose lock on the signal, resulting in the channel incorrectly adjusting a sampling phase toward a following symbol or previous symbol. This is referred to as a cycle slip, where the integer alignment of the sampling of a signal contains a discontinuity over the duration of a sector, preventing decoding of the signal. A circuit may be configured to detect a cycle slip during processing of a signal at a data channel based on timing error values, and when the signal fails to decode, shift an expected sampling phase of a detector for a subsequent signal processing attempt. Shifting the expected sampling phase can cause the channel to adjust the sampling phase in the correct direction, thereby preventing a cycle slip.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: December 25, 2018
    Assignee: Seagate Technology LLC
    Inventors: Jason Vincent Bellorado, Marcus Marrow, Zheng Wu
  • Patent number: 10148312
    Abstract: A method of generating a spread spectrum signal is disclosed. The method includes selecting a first pseudorandom slope for a modulation curve. A current frequency on the modulation curve is selected. An oscillating signal is produced at the current frequency for a respective time. The current frequency is set to a next frequency on the modulation curve. The steps of producing an oscillating frequency and setting the current frequency to a next frequency are repeated until the current frequency is a final frequency on the modulation curve.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: December 4, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Theodore Ernest Yu, Yogesh Kumar Ramadass
  • Patent number: 10084465
    Abstract: An analog-to-digital converter ADC may be provided. The ADC may include a current driving circuit. The current driving circuit may include an additive current driving circuit and a subtractive current driving circuit configured for adjusting a voltage level of a node. The ADC may include a comparison circuit including a plurality of comparators. Each of the plurality of comparators may be configured to compare a voltage level of the node with a reference voltage.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: September 25, 2018
    Assignee: SK hynix Inc.
    Inventors: Keunjin Chang, Joo Won Oh, Donghoon Sung
  • Patent number: 10075285
    Abstract: A bandwidth adjusting method for a phase-locked loop (PLL) unit of a phase recovery module includes: adjusting an operating bandwidth of the PLL unit to a first bandwidth; measuring multiple first phase errors between a compensated input signal, which is generated according to an input signal and a phase compensating signal that the PLL unit generates, and a reference clock signal, and obtaining a first statistical value of the first phase errors; adjusting the operating bandwidth of the PLL unit to a second bandwidth; measuring multiple second phase differences between the compensated input signal and the reference clock signal, and obtaining a second statistical value of the second phase differences; and adjusting the operating bandwidth according to the first statistical value and the second statistical value. The first bandwidth and the second bandwidth are obtained by interpolating an upper bandwidth limit and a lower bandwidth limit.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: September 11, 2018
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Ting-Nan Cho, Kai-Wen Cheng, Tai-Lai Tung
  • Patent number: 10031167
    Abstract: Circuits and methods for identifying or verifying frequencies are disclosed herein. A frequency verification circuit comprises: an input port for receiving an input signal; a phase frequency difference detector for determining a difference in phase and frequency between the input signal and a feedback signal and for providing a control signal based on the detected difference; a voltage controlled crystal oscillator for producing an output signal based on the control signal; and a feedback loop including a feedback divider for frequency dividing the output signal by a factor R to produce the feedback signal, the feedback divider being programmable to a plurality of values of the factor R to correspond to a plurality of different test frequencies.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: July 24, 2018
    Assignee: NANOWAVE TECHNOLOGIES INC.
    Inventors: Charles William Tremlett Nicholls, Walid Hamdane
  • Patent number: 10020777
    Abstract: A voltage-controlled oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors, coupled between a supply voltage and the two output terminals, two N-type transistors coupled between a ground voltage and the two output terminals, and a control circuit. The control circuit is coupled to the inductor, and is arranged to control a current flowing through the two P-type transistors and the inductor by controlling a voltage of the inductor.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: July 10, 2018
    Assignee: MEDIATEK INC.
    Inventors: Chao-Ching Hung, Po-Chun Huang, Yu-Li Hsueh
  • Patent number: 10008981
    Abstract: An integrated clock generator includes a tunable LC oscillator, a tunable frequency synthesizer, and a processor. The tunable LC oscillator has an input for receiving an oscillator control signal, and an output for providing an oscillator clock signal. The tunable frequency synthesizer has a clock input coupled to the output of the tunable LC oscillator, a control input for receiving a synthesizer control signal, and an output for providing a clock output signal. The processor has an input for receiving a data input signal, a first output for providing the oscillator control signal, and a second output for providing the synthesizer control signal. The processor provides the oscillator control signal and the synthesizer control signal such that the tunable frequency synthesizer generates the output clock signal at a frequency indicated by the data input signal, and provides the synthesizer control signal further in response to a dynamic condition.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: June 26, 2018
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Brian G. Drost, Hendricus de Ruijter
  • Patent number: 10008954
    Abstract: In accordance with an embodiment, a method includes driving at least one electronic switch coupled to at least one inductor in a converter stage of a switched mode power supply based on a clock signal, and modulating a clock frequency of the clock signal over a predefined first frequency range around a center frequency such that a frequency spectrum of the clock signal is asymmetric. The switched mode power supply includes a filter coupled between the converter stage and an input of the switched mode power supply.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: June 26, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Johann Kolar, Matthias Kasper, Cheng-Wei Chen
  • Patent number: 10003414
    Abstract: The method for calibrating the frequency synthesizer using two-point FSK modulation consists, in a first phase, in supplying an excitation signal generated by a calibration unit to a sigma-delta modulator by deactivating a digital-to-analog converter and transmitting the output signal from a loop filter of the synthesizer to the calibration unit, which digitally converts the incoming signal and offsets the phase shift between the excitation signal and the loop filter output signal in the calibration unit. In a second phase, the excitation signal is supplied to the sigma-delta modulator and to the activated digital-to-analog converter, and the digital-to-analog converter gain is calibrated by checking, in the calibration unit, the polarity of the loop filter output signal with respect to the excitation signal, and using a dichotomy algorithm.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: June 19, 2018
    Assignee: The Swatch Group Research and Development Ltd
    Inventor: Arnaud Casagrande
  • Patent number: 9948449
    Abstract: Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: April 17, 2018
    Assignee: SUNRISE MICRO DEVICES, INC.
    Inventors: Mario Lafuente, Paul Edward Gorday
  • Patent number: 9948234
    Abstract: A voltage controlled oscillator (VCO) is disclosed. The VCO includes an amplifier that receives a control signal and a feedback signal and generates an amplified output signal based on the difference between the control signal and the feedback signal. The VCO also includes circuitry to generate an oscillating output signal based on the amplifier output signal. Additionally, the VCO includes a feedback amplifier that generates the feedback signal based on the output of the amplifier. The feedback amplifier includes a first resistor connected in parallel with a second resistor, the second resistor having an adjustable resistance.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: April 17, 2018
    Assignee: Lattice Semiconductor Corporation
    Inventors: Qiming Wu, Yibin Fu, Yu Shen, Zhi Wu, Kai Lei, Kai Zhou, Kexin Luo, Xiaofeng Wang
  • Patent number: 9893876
    Abstract: A phase locked loop, comprising: a phase detector configured to determine a phase difference (??) between a reference signal and a feedback signal; a loop filter configured to perform a filtering operation on a signal derived from the phase difference, and to provide a control signal; a frequency controlled oscillator configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal; wherein a low-pass filter is provided between the phase detector and the loop filter and/or between the loop filter and the frequency controlled oscillator to reduce quantization noise from the phase detector.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: February 13, 2018
    Assignee: NXP B.V.
    Inventor: Ulrich Moehlmann
  • Patent number: 9893913
    Abstract: A technique for cancelling or reducing crosstalk signals between controlled oscillators in an integrated circuit is provided. The technique involves an arrangement adapted to reduce a crosstalk signal generated by a first controlled oscillator to a second oscillator both comprised in the integrated circuit, wherein both controlled oscillators are configured to output a respective clock signal. The arrangement comprises a detector adapted to detect the crosstalk signal generated by the first controlled oscillator to the second controlled oscillator, a crosstalk cancellation circuit adapted to generate a cancellation signal having an amplitude substantially the same as that of the crosstalk signal and a phase substantially opposite to that of the crosstalk signal, and a cancellation signal injector adapted to introduce the cancellation signal into the second controlled oscillator.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: February 13, 2018
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (publ)
    Inventors: Fenghao Mu, Lars Sundström
  • Patent number: 9825639
    Abstract: The present disclosure is directed towards systems and method for actively tuning a phase locked loop based on vibration excitation levels experienced by the phase locked loop. A bandwidth of the phase locked loop can be actively increased or decreased based upon a detected vibration level. In an embodiment, the phase locked loop includes a controllable oscillator, an output module, a filter module and a detector. The filter module can be configured to receive a bandwidth control signal to modify a bandwidth of the phase locked loop based on a vibration signal. In an embodiment, the vibration signal corresponds to a vibration level experienced by the phased locked loop. The detector can be configured to receive a PLL output signal from the output module and to receive a PLL input signal.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: November 21, 2017
    Assignee: Raytheon Company
    Inventors: Michael R. Patrizi, Nathan R. Francis, Matthew J. Koeth
  • Patent number: 9825588
    Abstract: An oscillator comprising a support substrate, at least one transducer mounted on a first surface of the support substrate, and an integrated circuit element mounted on a second surface of the support substrate. The integrated circuit element includes first and second frequency generating components integrated therein. The first frequency generating component generates a first output frequency, and the second frequency generating component generates a second output frequency that is higher than the first output frequency. The oscillator also includes a ground terminal to which the second frequency generating component is closer than the first frequency generating component.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: November 21, 2017
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Yoshiaki Matsumoto
  • Patent number: 9793906
    Abstract: A locked loop circuit includes a controlled oscillator generate an output signal having a frequency set by an analog control signal. The analog control signal is generated by a first digital-to-analog converter (DAC) in response to a digital control signal and a bias compensation current signal. The bias compensation current signal is generated by a second DAC in response to a compensation control signal and a bias reference current. A compensation circuit adjusts the compensation control signal during compensation mode in response to a comparison of a frequency of the output signal to a frequency of a reference signal so as to drive the frequency of the output signal toward matching a desired frequency. The bias compensation current signal associated with the frequency match condition during compensation mode is then used during locked loop mode.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: October 17, 2017
    Assignee: STMicroelectronics International N.V.
    Inventor: Gagan Midha
  • Patent number: 9774363
    Abstract: An apparatus of a mobile device may calibrate RF circuitry for mobile communications. The apparatus may include phase locked loop (PLL) comprising a digital controlled oscillator (DCO) and one or more processors coupled to the PLL. The one or more processors may determine a coarse tuning setting for the DCO based on a target frequency of a wireless channel; and calculate, a DCO gain value for the coarse tuning setting based on a calibration DCO gain value for a calibration coarse tuning setting.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 26, 2017
    Assignee: Intel Corporation
    Inventor: Stefan Tertinek
  • Patent number: 9748930
    Abstract: A method includes generating a calibration signal by a clock generator, feeding the calibration signal to a first filter through a first switch unit, comparing an output of the first filter with the calibration signal through a frequency detector and a phase comparator and generating a first updated bandwidth code to adjust a bandwidth frequency of the first filter.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Feng Wei Kuo
  • Patent number: 9712177
    Abstract: A phase-locked loop. The phase-locked loop includes a voltage-controlled oscillator having: a control input, and a clock output; and a phase frequency detector having: a reference clock input, a feedback clock input, an up output configured to be either in a set state or a reset state, and a down output configured to be either in a set state or a reset state. The up output and the down output are connected to the control input. The clock output is connected to the feedback clock input. The phase frequency detector includes an adjustable delay block configured to delay, by an adjustable delay time: a transition of the up output from the set state to the reset state, and a transition of the down output from the set state to the reset state.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: July 18, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Mohammad Hekmat, Jalil Kamali
  • Patent number: 9706497
    Abstract: A method for a near field communication circuit includes entering a low power mode and subsequently determining to exit the low power mode. The method further includes generating an open loop clock signal and providing the open loop clock signal to circuits of the near field communication circuit during a low power mode exit duration. Subsequently a reference clock signal is received from a host and used to clock the near field communication circuit.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: July 11, 2017
    Assignee: NXP USA, INC.
    Inventors: Yushi Tian, Wayne (Siwei) Tang, Handiono Santosa
  • Patent number: 9634877
    Abstract: Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: April 25, 2017
    Assignee: SUNRISE MICRO DEVICES, INC.
    Inventors: Mario Lafuente, Paul Edward Gorday
  • Patent number: 9628316
    Abstract: A multi-waveband OFDM receiver and a frequency offset compensation method and system are disclosed. The method includes: performing single waveband frequency offset estimation on an optical comb line of each order; classifying the optical comb lines into a low mutation optical comb line and a high mutation optical comb line; performing joint frequency offset estimation on the low mutation optical comb line; and performing compensation for a frequency offset of a radio frequency drive signal by using an estimated joint frequency offset. The present invention improves accuracy and reliability of the frequency offset estimation of the radio frequency drive signal, so that the degree of the compensation for the frequency offset of the radio frequency drive signal is more comprehensive and accurate.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: April 18, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xingwen Yi, Cheng Hong, Huaping Qing
  • Patent number: 9608647
    Abstract: A system and method for calibrating a Voltage-Controlled Oscillator (VCO) having both fine-tuning control and coarse-tuning control. The VCO frequency can vary monotonically with changes in each of one or more operational conditions. The calibration method determines the coarse-tuning control setting for the VCO at system start-up. The method comprises generating frequency characterization data, generating a polynomial function from the characterization data, calculating the fine-tuning control voltage based on the polynomial function and a measurement of the operational conditions, and sweeping through all the coarse-tuning control settings to determine the coarse-tuning control setting that generates the closest VCO frequency to a target frequency when using the calculated fine-tuning control voltage.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: March 28, 2017
    Assignee: MAXLINEAR ASIA SINGAPORE PTE LTD.
    Inventors: Hormoz Djahanshahi, Masoud Ghoreishi Madiseh
  • Patent number: 9608599
    Abstract: An RF circuit and method for detecting the amount of phase shift applied to an RF signal. An RF heating apparatus including the RF circuit. The RF circuit includes a phase shifter operable to apply a phase shift to a reference signal to produce a phase shifted reference signal. The RF circuit also includes a phase detector operable to detect a phase difference between the phase shifted RF signal and the phase shifted reference signal. The phase detector has a reduced input range at a frequency of the phase shifted RF signal. The RF circuit further includes a controller operable to control the phase shifter to set the phase of the phase shifted reference signal so that the phase difference between the phase shifted RF signal and the phase shifted reference signal falls within the reduced input range of the phase detector.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: March 28, 2017
    Assignee: NXP B.V.
    Inventor: Jean-Robert Tourret
  • Patent number: 9602082
    Abstract: Techniques for correcting clock distortion. The techniques include use of circuitry for detecting and correcting duty cycle distortion and quadrature clock phase distortion. For phase detection, detection circuitry is made simpler and more accurate through the use of a sampling operation in which device mismatch within detection circuitry is accounted for by sampling charge associated with an ideal clock signal across sampling capacitors. When phase detection is performed with the detection circuitry, the stored charge compensates for the device mismatch, improving the accuracy of the detection circuit. The sampling operation is used for duty cycle distortion detection as well. Specifically, a common mode voltage is applied to sampling capacitors, which effectively zeroes the voltage differential between the sampling capacitors, compensating for offset that might exist due to operation of other components of the detection circuit.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: March 21, 2017
    Assignee: XILINX, INC.
    Inventors: Hiva Hedayati, Yohan Frans
  • Patent number: 9601101
    Abstract: Techniques and systems for facilitating the calibration of oscillation frequencies for an analog audio synthesizer are disclosed. Included are embodiments for performing the initial calibration of an audio synthesizer and for continuously compensating for the frequency irregularities which originate from insufficient calibration and/or frequency drift of the oscillator circuits. Embodiments can utilize the microcontroller already present in most synthesizers and require no further hardware.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: March 21, 2017
    Assignee: THE FLORIDA INTERNATIONAL UNIVERSITY BOARD OF TRUSTEES
    Inventors: Oliver Ullrich, Naphtali Rishe
  • Patent number: 9571114
    Abstract: An analog-to-digital converter (ADC) circuit comprises a digital-to-analog (DAC) circuit including at least N+n weighted circuit components, wherein N and n are positive integers greater than zero, and n is a number of repeat bits of the least significant bit (LSB) of the ADC circuit; a sampling circuit configured to sample an input voltage at an input to the ADC circuit and apply a sampled voltage to the weighted circuit components; a comparator circuit configured to compare an output voltage of the DAC to a specified threshold voltage during a bit trial; and logic circuitry configured to perform bit trials for the at least N+n weighted circuit components and adjust one or more parameters for one or more of N bit trials according to values of the n LSB repeat bits.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: February 14, 2017
    Assignee: Analog Devices, Inc.
    Inventors: Junhua Shen, Edward C. Guthrie
  • Patent number: 9560609
    Abstract: Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (PLL). Methods include minimizing the mixing gain between the oscillation signal and a power signal provided to the PLL. The oscillation signal and the power signal may be mixed in a phase frequency detector (PFD) included in the PLL. The minimizing of the mixing gain for the PFD also minimizes the degrading effect that the spurs have on the overall performance of the communications device. The mixing gain may be minimized by minimizing the impedance provided at nodes included in the PFD where the oscillation signal and the power signal mix. The mixing gain may also be minimized by maximizing the power supply rejection ratio for the PFD.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 31, 2017
    Assignee: Broadcom Corporation
    Inventors: Nikolaos Haralabidis, Ioannis Kokolakis, Georgios Konstantopoulos
  • Patent number: 9553714
    Abstract: The problem with duty-cycle correction circuits used by conventional frequency doublers is that they typically analog solutions, such as variable delay lines with long chains of inverters or buffers, that directly adjust the reference signal used by a phase-locked loop (PLL). These solutions can considerably increase the noise (e.g., thermal noise and supply noise) of the reference signal, as well as the overall power consumption and cost of the PLL. Rather than directly correct the duty-cycle of the reference signal, the present disclosure is directed to an apparatus and method for measuring the period error between adjacent cycles of a frequency doubled reference signal in terms of cycles of the output signal generated by the PLL (or some other higher frequency signal) and adjusting the division factor of the PLL frequency divider to compensate for the measured period error.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 24, 2017
    Assignee: Broadcom Corporation
    Inventors: Fazil Ahmad, Pin-En Su, William Huff, Greg Unruh
  • Patent number: 9537494
    Abstract: A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. A sampled loop filter (SLPF) in the phase locked loop may capture charge from a charge pump (CHP) in the phase locked loop and the charge is captured at a frequency corresponding to the frequency of the reference clock signal. A switch of the sampled loop filter is utilized and controlled to manage holding and releasing of the captured charge, where the switch is controlled utilizing a control signal. By utilizing the sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of the charge pump, disturbance which is associated with duty cycle errors of the crystal clock signal.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: January 3, 2017
    Assignee: MaxLinear, Inc.
    Inventor: Sheng Ye
  • Patent number: 9531393
    Abstract: Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: December 27, 2016
    Assignee: Intel Corporation
    Inventors: Wenyan Vivian Jia, Shenggao Li, Fulvio Spagna
  • Patent number: 9531395
    Abstract: This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a digital phase locked loop (DPLL) based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client). An example of this DPLL in conjunction with a recursive least squares mechanism for clock offset and skew estimation is also provided.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: December 27, 2016
    Assignees: Khalifa University of Science, Technology and Research, Emirates Telecommunications Corporation, British Telecommunications Corporation
    Inventor: James Aweya
  • Patent number: 9509371
    Abstract: A method and apparatus for harmonic distortion compensation in power line communications. In one embodiment, the method comprises analyzing a waveform generated by a transmitter of a power line communications transceiver (PLCT), wherein the waveform is analyzed to determine harmonic information for one or more harmonics of a carrier waveform of the PLCT; computing, based on the harmonic information, one or more harmonic compensation coefficients; and pre-distorting, based on the one or more harmonic compensation coefficients, the carrier waveform such that the one or more harmonics are reduced below a threshold.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: November 29, 2016
    Assignee: Enphase Energy, Inc.
    Inventors: Martin Fornage, Kennan Laudel
  • Patent number: 9503017
    Abstract: The described devices, systems and methods include a voltage controlled oscillator. The voltage controlled oscillator includes a fine-tuning varactor network, a switch capacitor array having a first plurality of binary capacitor array elements and a second plurality of thermometer code capacitor array elements, and a tank inductor network including a first inductor in parallel with a second inductor.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: November 22, 2016
    Assignee: Qorvo US, Inc.
    Inventors: Jacob K. Easter, William Thales Roberts, Shayan Farahvash, David Conrad Stegmeir, Li Jin
  • Patent number: 9496856
    Abstract: Provided is a ramp signal generating apparatus. The ramp signal generating apparatus includes N (N is a natural number) ramp signal generating cells that are connected in series to each other. Each of the ramp signal generating cells includes a power voltage unit for supplying current source, a latch unit for latching an output voltage of the power voltage unit, and a switch unit for outputting the voltage latched by the latch unit as an output voltage in response to an input signal.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: November 15, 2016
    Assignee: Korea University Research and Business Foundation
    Inventors: Chul Woo Kim, Min Seob Shim, Jun Won Jung, Jung Moon Kim, Jun Young Maeng
  • Patent number: 9473022
    Abstract: An apparatus including: a current source configured to generate current; a switching current source circuit coupled to the current source and a first bias node to allow the current to flow through the switching current source circuit into the first bias node; a first bias circuit configured to receive a first control signal from a phase detector, the first bias circuit configured to mirror the current flowing through the switching current source circuit in response to the first control signal; a second bias circuit coupled to the first bias circuit at an output node and a second bias node, the second bias circuit configured to receive a second control signal from the phase detector; and a transconductance amplifier configured to receive a feedback signal from the output node and generate an output current to control the second biasing node.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: October 18, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Dongmin Park, Lai Kan Leung, Jong Min Park
  • Patent number: 9473157
    Abstract: A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: October 18, 2016
    Assignee: MEDIATEK INC.
    Inventors: Chun-Ming Kuo, Chii-Horng Chen, Shih-Chi Shen, Ai-Hsuan Liu
  • Patent number: 9467090
    Abstract: A semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to detected ambient temperature and operating voltage.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: October 11, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Tsukasa Oishi, Katsuyoshi Mitsui, Naoki Otani
  • Patent number: 9465373
    Abstract: A mechanism is provided for implementing an operational parameter change within the data processing system based on an identified degradation. One or more degradations existing in the data processing system are identified based on a set of degradation values obtained from a set of degradation sensors. A determination is made as to whether one or more operational parameters need to be modified based on the one or more identified degradations. Responsive to determining that the one or more operational parameters need to be modified based on the one or more identified degradations, an input change is implemented to a one or more control devices in order that the one or more operational parameters are modified.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: October 11, 2016
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Alan J. Drake, Michael S. Floyd, Tilman Gloekler, Charles R. Lefurgy, Karthick Rajamani
  • Patent number: 9467153
    Abstract: In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: October 11, 2016
    Assignee: FINISAR CORPORATION
    Inventors: The'Linh Nguyen, Steven Gregory Troyer, Daniel K. Case