Tuning Compensation Patents (Class 331/16)
  • Patent number: 9748930
    Abstract: A method includes generating a calibration signal by a clock generator, feeding the calibration signal to a first filter through a first switch unit, comparing an output of the first filter with the calibration signal through a frequency detector and a phase comparator and generating a first updated bandwidth code to adjust a bandwidth frequency of the first filter.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Feng Wei Kuo
  • Patent number: 9712177
    Abstract: A phase-locked loop. The phase-locked loop includes a voltage-controlled oscillator having: a control input, and a clock output; and a phase frequency detector having: a reference clock input, a feedback clock input, an up output configured to be either in a set state or a reset state, and a down output configured to be either in a set state or a reset state. The up output and the down output are connected to the control input. The clock output is connected to the feedback clock input. The phase frequency detector includes an adjustable delay block configured to delay, by an adjustable delay time: a transition of the up output from the set state to the reset state, and a transition of the down output from the set state to the reset state.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: July 18, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Mohammad Hekmat, Jalil Kamali
  • Patent number: 9706497
    Abstract: A method for a near field communication circuit includes entering a low power mode and subsequently determining to exit the low power mode. The method further includes generating an open loop clock signal and providing the open loop clock signal to circuits of the near field communication circuit during a low power mode exit duration. Subsequently a reference clock signal is received from a host and used to clock the near field communication circuit.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: July 11, 2017
    Assignee: NXP USA, INC.
    Inventors: Yushi Tian, Wayne (Siwei) Tang, Handiono Santosa
  • Patent number: 9634877
    Abstract: Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: April 25, 2017
    Assignee: SUNRISE MICRO DEVICES, INC.
    Inventors: Mario Lafuente, Paul Edward Gorday
  • Patent number: 9628316
    Abstract: A multi-waveband OFDM receiver and a frequency offset compensation method and system are disclosed. The method includes: performing single waveband frequency offset estimation on an optical comb line of each order; classifying the optical comb lines into a low mutation optical comb line and a high mutation optical comb line; performing joint frequency offset estimation on the low mutation optical comb line; and performing compensation for a frequency offset of a radio frequency drive signal by using an estimated joint frequency offset. The present invention improves accuracy and reliability of the frequency offset estimation of the radio frequency drive signal, so that the degree of the compensation for the frequency offset of the radio frequency drive signal is more comprehensive and accurate.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: April 18, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xingwen Yi, Cheng Hong, Huaping Qing
  • Patent number: 9608647
    Abstract: A system and method for calibrating a Voltage-Controlled Oscillator (VCO) having both fine-tuning control and coarse-tuning control. The VCO frequency can vary monotonically with changes in each of one or more operational conditions. The calibration method determines the coarse-tuning control setting for the VCO at system start-up. The method comprises generating frequency characterization data, generating a polynomial function from the characterization data, calculating the fine-tuning control voltage based on the polynomial function and a measurement of the operational conditions, and sweeping through all the coarse-tuning control settings to determine the coarse-tuning control setting that generates the closest VCO frequency to a target frequency when using the calculated fine-tuning control voltage.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: March 28, 2017
    Assignee: MAXLINEAR ASIA SINGAPORE PTE LTD.
    Inventors: Hormoz Djahanshahi, Masoud Ghoreishi Madiseh
  • Patent number: 9608599
    Abstract: An RF circuit and method for detecting the amount of phase shift applied to an RF signal. An RF heating apparatus including the RF circuit. The RF circuit includes a phase shifter operable to apply a phase shift to a reference signal to produce a phase shifted reference signal. The RF circuit also includes a phase detector operable to detect a phase difference between the phase shifted RF signal and the phase shifted reference signal. The phase detector has a reduced input range at a frequency of the phase shifted RF signal. The RF circuit further includes a controller operable to control the phase shifter to set the phase of the phase shifted reference signal so that the phase difference between the phase shifted RF signal and the phase shifted reference signal falls within the reduced input range of the phase detector.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: March 28, 2017
    Assignee: NXP B.V.
    Inventor: Jean-Robert Tourret
  • Patent number: 9601101
    Abstract: Techniques and systems for facilitating the calibration of oscillation frequencies for an analog audio synthesizer are disclosed. Included are embodiments for performing the initial calibration of an audio synthesizer and for continuously compensating for the frequency irregularities which originate from insufficient calibration and/or frequency drift of the oscillator circuits. Embodiments can utilize the microcontroller already present in most synthesizers and require no further hardware.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: March 21, 2017
    Assignee: THE FLORIDA INTERNATIONAL UNIVERSITY BOARD OF TRUSTEES
    Inventors: Oliver Ullrich, Naphtali Rishe
  • Patent number: 9602082
    Abstract: Techniques for correcting clock distortion. The techniques include use of circuitry for detecting and correcting duty cycle distortion and quadrature clock phase distortion. For phase detection, detection circuitry is made simpler and more accurate through the use of a sampling operation in which device mismatch within detection circuitry is accounted for by sampling charge associated with an ideal clock signal across sampling capacitors. When phase detection is performed with the detection circuitry, the stored charge compensates for the device mismatch, improving the accuracy of the detection circuit. The sampling operation is used for duty cycle distortion detection as well. Specifically, a common mode voltage is applied to sampling capacitors, which effectively zeroes the voltage differential between the sampling capacitors, compensating for offset that might exist due to operation of other components of the detection circuit.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: March 21, 2017
    Assignee: XILINX, INC.
    Inventors: Hiva Hedayati, Yohan Frans
  • Patent number: 9571114
    Abstract: An analog-to-digital converter (ADC) circuit comprises a digital-to-analog (DAC) circuit including at least N+n weighted circuit components, wherein N and n are positive integers greater than zero, and n is a number of repeat bits of the least significant bit (LSB) of the ADC circuit; a sampling circuit configured to sample an input voltage at an input to the ADC circuit and apply a sampled voltage to the weighted circuit components; a comparator circuit configured to compare an output voltage of the DAC to a specified threshold voltage during a bit trial; and logic circuitry configured to perform bit trials for the at least N+n weighted circuit components and adjust one or more parameters for one or more of N bit trials according to values of the n LSB repeat bits.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: February 14, 2017
    Assignee: Analog Devices, Inc.
    Inventors: Junhua Shen, Edward C. Guthrie
  • Patent number: 9560609
    Abstract: Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (PLL). Methods include minimizing the mixing gain between the oscillation signal and a power signal provided to the PLL. The oscillation signal and the power signal may be mixed in a phase frequency detector (PFD) included in the PLL. The minimizing of the mixing gain for the PFD also minimizes the degrading effect that the spurs have on the overall performance of the communications device. The mixing gain may be minimized by minimizing the impedance provided at nodes included in the PFD where the oscillation signal and the power signal mix. The mixing gain may also be minimized by maximizing the power supply rejection ratio for the PFD.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 31, 2017
    Assignee: Broadcom Corporation
    Inventors: Nikolaos Haralabidis, Ioannis Kokolakis, Georgios Konstantopoulos
  • Patent number: 9553714
    Abstract: The problem with duty-cycle correction circuits used by conventional frequency doublers is that they typically analog solutions, such as variable delay lines with long chains of inverters or buffers, that directly adjust the reference signal used by a phase-locked loop (PLL). These solutions can considerably increase the noise (e.g., thermal noise and supply noise) of the reference signal, as well as the overall power consumption and cost of the PLL. Rather than directly correct the duty-cycle of the reference signal, the present disclosure is directed to an apparatus and method for measuring the period error between adjacent cycles of a frequency doubled reference signal in terms of cycles of the output signal generated by the PLL (or some other higher frequency signal) and adjusting the division factor of the PLL frequency divider to compensate for the measured period error.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 24, 2017
    Assignee: Broadcom Corporation
    Inventors: Fazil Ahmad, Pin-En Su, William Huff, Greg Unruh
  • Patent number: 9537494
    Abstract: A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. A sampled loop filter (SLPF) in the phase locked loop may capture charge from a charge pump (CHP) in the phase locked loop and the charge is captured at a frequency corresponding to the frequency of the reference clock signal. A switch of the sampled loop filter is utilized and controlled to manage holding and releasing of the captured charge, where the switch is controlled utilizing a control signal. By utilizing the sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of the charge pump, disturbance which is associated with duty cycle errors of the crystal clock signal.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: January 3, 2017
    Assignee: MaxLinear, Inc.
    Inventor: Sheng Ye
  • Patent number: 9531393
    Abstract: Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: December 27, 2016
    Assignee: Intel Corporation
    Inventors: Wenyan Vivian Jia, Shenggao Li, Fulvio Spagna
  • Patent number: 9531395
    Abstract: This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a digital phase locked loop (DPLL) based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client). An example of this DPLL in conjunction with a recursive least squares mechanism for clock offset and skew estimation is also provided.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: December 27, 2016
    Assignees: Khalifa University of Science, Technology and Research, Emirates Telecommunications Corporation, British Telecommunications Corporation
    Inventor: James Aweya
  • Patent number: 9509371
    Abstract: A method and apparatus for harmonic distortion compensation in power line communications. In one embodiment, the method comprises analyzing a waveform generated by a transmitter of a power line communications transceiver (PLCT), wherein the waveform is analyzed to determine harmonic information for one or more harmonics of a carrier waveform of the PLCT; computing, based on the harmonic information, one or more harmonic compensation coefficients; and pre-distorting, based on the one or more harmonic compensation coefficients, the carrier waveform such that the one or more harmonics are reduced below a threshold.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: November 29, 2016
    Assignee: Enphase Energy, Inc.
    Inventors: Martin Fornage, Kennan Laudel
  • Patent number: 9503017
    Abstract: The described devices, systems and methods include a voltage controlled oscillator. The voltage controlled oscillator includes a fine-tuning varactor network, a switch capacitor array having a first plurality of binary capacitor array elements and a second plurality of thermometer code capacitor array elements, and a tank inductor network including a first inductor in parallel with a second inductor.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: November 22, 2016
    Assignee: Qorvo US, Inc.
    Inventors: Jacob K. Easter, William Thales Roberts, Shayan Farahvash, David Conrad Stegmeir, Li Jin
  • Patent number: 9496856
    Abstract: Provided is a ramp signal generating apparatus. The ramp signal generating apparatus includes N (N is a natural number) ramp signal generating cells that are connected in series to each other. Each of the ramp signal generating cells includes a power voltage unit for supplying current source, a latch unit for latching an output voltage of the power voltage unit, and a switch unit for outputting the voltage latched by the latch unit as an output voltage in response to an input signal.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: November 15, 2016
    Assignee: Korea University Research and Business Foundation
    Inventors: Chul Woo Kim, Min Seob Shim, Jun Won Jung, Jung Moon Kim, Jun Young Maeng
  • Patent number: 9473022
    Abstract: An apparatus including: a current source configured to generate current; a switching current source circuit coupled to the current source and a first bias node to allow the current to flow through the switching current source circuit into the first bias node; a first bias circuit configured to receive a first control signal from a phase detector, the first bias circuit configured to mirror the current flowing through the switching current source circuit in response to the first control signal; a second bias circuit coupled to the first bias circuit at an output node and a second bias node, the second bias circuit configured to receive a second control signal from the phase detector; and a transconductance amplifier configured to receive a feedback signal from the output node and generate an output current to control the second biasing node.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: October 18, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Dongmin Park, Lai Kan Leung, Jong Min Park
  • Patent number: 9473157
    Abstract: A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: October 18, 2016
    Assignee: MEDIATEK INC.
    Inventors: Chun-Ming Kuo, Chii-Horng Chen, Shih-Chi Shen, Ai-Hsuan Liu
  • Patent number: 9465373
    Abstract: A mechanism is provided for implementing an operational parameter change within the data processing system based on an identified degradation. One or more degradations existing in the data processing system are identified based on a set of degradation values obtained from a set of degradation sensors. A determination is made as to whether one or more operational parameters need to be modified based on the one or more identified degradations. Responsive to determining that the one or more operational parameters need to be modified based on the one or more identified degradations, an input change is implemented to a one or more control devices in order that the one or more operational parameters are modified.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: October 11, 2016
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Alan J. Drake, Michael S. Floyd, Tilman Gloekler, Charles R. Lefurgy, Karthick Rajamani
  • Patent number: 9467090
    Abstract: A semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to detected ambient temperature and operating voltage.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: October 11, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Tsukasa Oishi, Katsuyoshi Mitsui, Naoki Otani
  • Patent number: 9467153
    Abstract: In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: October 11, 2016
    Assignee: FINISAR CORPORATION
    Inventors: The'Linh Nguyen, Steven Gregory Troyer, Daniel K. Case
  • Patent number: 9455625
    Abstract: A switching converter with slope compensation circuit, the slope compensation circuit has a first voltage source, a first operation circuit, a first switch, a first capacitor, a second switch and a first controlled current source.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: September 27, 2016
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventor: Bo Zhang
  • Patent number: 9425736
    Abstract: Variable capacitor structures and methods of use are disclosed. The variable capacitor structures include a variable controlled oscillator which includes a variable capacitor structure having at least one capacitor set driven by a control gate voltage of a voltage control circuit which comprises a logic cell that senses a selected frequency band and sets the control gate voltage based on the selected frequency band.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: August 23, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Ram Kelkar
  • Patent number: 9397558
    Abstract: An apparatus including: a current source configured to generate current; a switching current source circuit coupled to the current source and a first bias node to allow the current to flow through the switching current source circuit into the first bias node; a first bias circuit configured to receive a first control signal from a phase detector, the first bias circuit configured to mirror the current flowing through the switching current source circuit in response to the first control signal; a second bias circuit coupled to the first bias circuit at an output node and a second bias node, the second bias circuit configured to receive a second control signal from the phase detector; and a transconductance amplifier configured to receive a feedback signal from the output node and generate an output current to control the second biasing node.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: July 19, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Dongmin Park, Lai Kan Leung, Jong Min Park
  • Patent number: 9385732
    Abstract: A variable frequency signal synthesizer includes a phase locked loop including a time-to-digital converter configured to detect differences in phase and frequency between a reference signal and a feedback clock signal and output error signals corresponding to the detected differences, a digital loop filter, a digitally controlled oscillator, and a first frequency divider configured to divide output signals of the digitally controlled oscillator at a predetermined frequency division ratio, a feedback clock generation unit configured to generate sign signals and a phase-modulated feedback clock signal, and a frequency slope tracker configured to generate a frequency control signal by accumulating differences in the error signals according to signs corresponding to the sign signals. The digitally controlled oscillator receives the frequency control signal to supply an output variable frequency signal.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: July 5, 2016
    Assignee: SNU R&DB FOUNDATION
    Inventors: Jae Ha Kim, Hwan Seok Yeo, Si Gang Ryu
  • Patent number: 9356612
    Abstract: Aspects of the disclosure provide a circuit that includes a detector, a loop filter and a controller. The detector is configured to generate a first signal indicative a timing difference between a reference clock signal and a feedback clock signal. The feedback clock signal is generated based on an oscillating signal from an oscillator. The oscillator includes a first tuning circuit and a second tuning circuit to tune a frequency of the oscillating signal. The loop filter is configured to filter out a portion of frequency components from the first signal to generate a second signal for tuning the first tuning circuit of the oscillator. The controller is configured to tune the second tuning circuit based on the first signal and the second signal.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: May 31, 2016
    Assignee: Marvell World Trade Ltd.
    Inventors: Xiang Gao, Li Lin
  • Patent number: 9350296
    Abstract: The present disclosure provides for a phase-locked loop (PLL) that includes a high-port calibration control module configured to calibrate an input modulation value of a voltage-controlled oscillator (VCO) to a first modulation value that results in an output signal of the VCO having a positive frequency change from an initial output frequency, and capture a positive frequency value of the output signal after a first accumulation time period. The high-port calibration control module is also configured to calibrate the input modulation value of the VCO to a second modulation value that results in the output signal having a negative frequency change from the initial output frequency, capture a negative frequency value of the output signal after a second accumulation time period, and calculate a calibration scale factor based on a difference between the positive and negative frequency values.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: May 24, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Khurram Waheed, Chris N. Stoll
  • Patent number: 9335261
    Abstract: The time-domain spectroscopy analysis system includes a splitter for splitting pulsed light entered, a variable delayer for delaying timing of a first part of the pulsed light split by the splitter, an electromagnetic wave generator for converting a second part of the pulsed light split by the splitter into an electromagnetic wave, a detector for detecting measurement data from a pulse having passed through a measurement object subjected to the electromagnetic wave emitted from the electromagnetic wave generator, and the pulse outputted from the variable delayer, and a comparator for detecting a phase difference between the pulsed light before being entered into the electromagnetic wave generator and the pulsed light outputted from the variable delayer, wherein a result obtained by the comparator is fed back to the variable delayer.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: May 10, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Takahiro Nakamura, Nobuhiro Shiramizu
  • Patent number: 9287853
    Abstract: A signal conversion circuit, a PLL circuit, a delay control circuit and a phase control circuit for promoting miniaturization and for reducing quantization noise. TSTC does not require a low-pass filter of capacitor Cm with large layout area conventionally required for converting pulse width to voltage, which promotes miniaturization and cost reduction. TSTC 8 generates analog voltage adequate for transition state at boundary where pulse signal transits, which reduces quantization noise, compared with conventional digital PLL circuits.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: March 15, 2016
    Assignee: AIKA DESIGN INC.
    Inventors: Toru Nakura, Kunihiro Asada
  • Patent number: 9257999
    Abstract: Systems and methods for compensating for a known interferer to a Controlled Oscillator (CO) of a Phase-Locked Loop (PLL) are disclosed. In one embodiment, a system includes a PLL and a compensation system. The compensation system is configured to generate a compensation signal based on a complex correlation of an output signal of a phase detector of the PLL and a signal derived from a replica of a known interferer to the CO. The compensation system is further configured to apply the compensation signal to the control signal provided by the low-pass filter of the phase-locked loop to thereby provide the compensated control signal for the CO of the phase-locked loop. In this manner, the compensation system mitigates the known interferer at the CO of the PLL.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: February 9, 2016
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventor: Sami Vilhonen
  • Patent number: 9240796
    Abstract: A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a digital control circuit configured to generate a curve select signal using a closed loop curve search operation to select one of the operating curves in the multi-curve VCO, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit implements a binary jump method and an operating curve is selected when the operating curve has an output frequency meeting the target frequency with the control voltage being within a first voltage range being a narrowed and centered voltage range within the control voltage range.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: January 19, 2016
    Assignee: Micrel, Inc.
    Inventors: Juinn-Yan Chen, Wei-Kang Cheng
  • Patent number: 9219485
    Abstract: Systems and methods for compensating for a known interferer to a Controlled Oscillator (CO) of a Phase-Locked Loop (PLL) are disclosed. In one embodiment, a system includes a PLL and a compensation system. The compensation system is configured to generate a compensation signal based on a complex correlation of an output signal of a phase detector of the PLL and a signal derived from a replica of a known interferer to the CO. The compensation system is further configured to apply the compensation signal to the control signal provided by the low-pass filter of the phase-locked loop to thereby provide the compensated control signal for the CO of the phase-locked loop. In this manner, the compensation system mitigates the known interferer at the CO of the PLL.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: December 22, 2015
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventor: Sami Vilhonen
  • Patent number: 9219599
    Abstract: A clock and data recovery (CDR) circuit employing zero-crossing linearizing (ZCL) technique. The circuit including a voltage controlled oscillator (VCO), an inject-locked divider (ILD), a variable delay unit, a linearized loop, a bang-bang loop, and a loop filter (LP). The differential clock generated by VCO passes through ILD for frequency dividing and variable delay unit to generate 8-phase clocks. Then using these clocks, the PDs over-sample the input data, followed by synchronization and logic operation to control the CPs output current pulses. These currents filtered by LP control the VCO to finish the loop. The circuit recovers 4 channel data and corresponding clocks of the input with low power broken-down and preferable jitter performance and locking property.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: December 22, 2015
    Assignee: FUDAN UNIVERSITY
    Inventors: Zhongkai Wang, Rui Bai, Patrick Yin Chiang
  • Patent number: 9203308
    Abstract: A power converter includes a ramp generating unit, a first comparator, a second comparator, and a pulse width modulation (PWM) signal generating unit. The ramp generating unit provides a ramp signal. The first comparator receives the ramp signal and a control signal to provide a normal operation control signal. The second comparator receives the ramp signal and the control signal to provide a dynamic response control signal. The PWM signal generating unit generates a PWM signal according to the normal operation control signal or dynamic response control signal. When the control signal is higher than a threshold of ramp signal, the second comparator provides the dynamic response control signal to the PWM signal generating unit to control it to adjust a duty cycle of the PWM signal.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 1, 2015
    Assignee: UPI SEMICONDUCTOR CORPORATION
    Inventor: Han Pang Wang
  • Patent number: 9203544
    Abstract: A transmitting device, a receiving device, an optical communication system, and associated methods are provided. The transmitting device transmits an optical signal containing data, and comprises: an optical tone generator for generating at least one optical tone; at least one encoder for performing advanced coding on at least one data signal respectively, each of the at least one data signal carrying a part of the data; at least one mapper for performing high order modulation on the at least one coded data signal; and an up-converter for up-converting the at least one high-order-modulated data signal into the optical signal to be outputted through the at least optical tone. Thereby, high speed (e.g., over 1-Tb/s) transmission per single channel over a long-haul distance (e.g. over 1000-km) with error-free recovery may be achieved.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: December 1, 2015
    Assignee: WUHAN RESEARCH INSTITUTE OF POSTS AND TELECOMMUNICATIONS
    Inventors: Qi Yang, Wu Liu, Zhixue He, William Shieh, Ivan B. Djordjevic, Zhu Yang, Shaohua Yu
  • Patent number: 9189724
    Abstract: The present invention provides a noncontact interface technique capable of performing communication operation without stopping an internal operation even when a clock signal cannot be extracted from a carrier wave. In a semiconductor device that receives a modulated carrier wave from an antenna, generates an internal clock signal on the basis of a clock signal extracted from the received carrier wave, and performs operation synchronously with the internal clock signal, a PLL circuit that receives the extracted clock signal and generates the internal clock signal is provided with a voltage control oscillation function. In the case where the clock signal extracted from the carrier wave is discretely interrupted, the function makes the internal clock signal maintained at a frequency immediately before the interruption. With the configuration, even when the clock signal extracted from the carrier wave is interrupted, internal data processes such as decoding and bus interfacing can be continued.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: November 17, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shin Morita, Norihisa Yamamoto
  • Patent number: 9166606
    Abstract: A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. The phase locked loop may enable usage of both rising and falling edges of the crystal clock signal, based on the generated reference clock signal. The phase locked loop may perform an operation of the phase locked loop based on the enabling. The phase locked loop may perform a phase comparison function, based on both rising and falling edges of the crystal clock signal. By utilizing a sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of a charge pump in the phase locked loop, disturbance which is associated with duty cycle errors of the crystal clock signal.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: October 20, 2015
    Assignee: MaxLinear, Inc.
    Inventor: Sheng Ye
  • Patent number: 9160274
    Abstract: The present disclosure relates to a FinFET varactor circuit having one or more control elements that control a relationship between capacitance and voltage of a FinFET MOS varactor without introducing changes to process parameters used in fabrication of the FinFET MOS varactor. In some embodiments, the FinFET varactor circuit has a FinFET MOS varactor with a first terminal connected to a gate terminal of the FinFET MOS varactor and a second terminal connected to connected source and drain terminals of the FinFET MOS varactor. One or more control elements are connected to the first or second terminals of the FinFET MOS varactor and vary one or more operating characteristics of the FinFET MOS varactor. Using the control elements to vary the operating characteristics of the FinFET MOS varactor, allows for the characteristics to be adjusted without making changes to process parameters used in the fabrication of the FinFET MOS varactor.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsieh-Hung Hsieh, Yi-Hsuan Liu, Chewn-Pu Jou
  • Patent number: 9143140
    Abstract: A delay circuit provides a quadrature-delayed strobe, a tightly controlled quadrature DLL and write/read leveling delay lines by using the same physical delay line pair. By multiplexing different usage models, the need for multiple delay lines is significantly reduced to only two delay lines per byte. As a result, the delay circuit provides substantial saving in terms of layout area and power.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: September 22, 2015
    Assignee: Cavium, Inc.
    Inventors: David Lin, Suresh Balasubramanian
  • Patent number: 9110777
    Abstract: A system has at least a first circuit portion and a second circuit portion. The first circuit portion is operated at normal AC frequency. The second circuit portion is operated in a back-up mode at low AC frequency, such that the second circuit portion can rapidly come-online but has limited temperature bias instability degradation. The second circuit portion can then be brought on-line and operated at the normal AC frequency. A system including first and second circuit portions and a control unit, as well as a computer program product, are also provided.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: August 18, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aditya Bansal, Manjul Bhushan, Keith A. Jenkins, Jae-Joon Kim, Barry P. Linder, Kai Zhao
  • Patent number: 9065601
    Abstract: A receiver in an integrated circuit device is described. The circuit comprises a receiver having a clock and data recovery circuit coupled to receive data signals modulated with a transmitter clock signal; and a clock generator coupled to receive an output of the clock and data recovery circuit, the clock generator providing a modulated reference clock to the receiver, based upon a reference clock signal which is independent of the transmitter clock signal; wherein the modulated reference clock provided to the receiver is synchronized with the transmitter clock signal. A method of receiving data in an integrated circuit is also described.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 23, 2015
    Assignee: XILINX, INC.
    Inventors: Michael O. Jenkins, Cheng-Hsiang Hsieh, Christopher J. Borrelli
  • Patent number: 9048849
    Abstract: The inventive concept relates to a supply regulated voltage controlled oscillator having a function of an active loop filter by sharing one operational amplifier without additional use of active elements in a supply regulated voltage controlled oscillator using an operational amplifier as a supply regulator, and a phase locked loop using the same.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: June 2, 2015
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Woo-Young Choi, Kwang-Chun Choi
  • Publication number: 20150130543
    Abstract: A circuit includes a first oscillator and a second oscillator. The first oscillator includes an inductive device, a capacitive device, and an active feedback device configured to output a first output signal having a predetermined frequency according to electrical characteristics of the inductive device of the first oscillator and electrical characteristics of the capacitive device of the first oscillator. The second oscillator includes an inductive device, a capacitive device, and an active feedback device configured to output a second output signal having the predetermined frequency according to electrical characteristics of the inductive device of the second oscillator and electrical characteristics of the capacitive device of the second oscillator. The inductive device of the first oscillator and the inductive device of the second oscillator are magnetically coupled.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chewn-Pu JOU, Huan-Neng CHEN
  • Patent number: 9024692
    Abstract: A method, an apparatus, and a computer program product are provided. The apparatus tunes a frequency provided by a VCO. The apparatus determines a relative capacitance change associated with a first frequency and a desired frequency from a look-up table. The apparatus adjusts a capacitor circuit in the VCO based on the determined relative capacitance change determined from the look-up table in order to tune from the first frequency to the desired frequency. The apparatus determines that the frequency provided by the VCO is a second frequency different than the desired frequency after adjusting the capacitor circuit. The apparatus performs an iterative search to further adjust the capacitor circuit when a difference between the second frequency and the desired frequency is greater than a threshold.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: May 5, 2015
    Assignee: Qualcomm Incorporated
    Inventors: Ngar Loong Alan Chan, Jeongsik Yang, Sang-Oh Lee
  • Patent number: 9025965
    Abstract: Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: May 5, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seung Woo Lee, Kwang Chun Choi, Woo Young Choi, Bhum Cheol Lee
  • Patent number: 9024694
    Abstract: A system is disclosed for a voltage controlled oscillator (“VCO”) having a large frequency range and a low gain. Passive or active circuitry is introduced between at least one VCO cell in the voltage controlled oscillator and the voltage source for the VCO cell which reduces a gain value for the VCO to maintain stability of the system.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chih-Min Liu
  • Patent number: 9019016
    Abstract: There are provided an accumulator-type fractional N-PLL synthesizer for suppressing the fractional spurious caused by periodically switching a frequency division number of a fractional frequency divider, and a control method thereof. In an accumulator-type fractional N-PLL synthesizer (100), a pulse signal proportional to a fractional phase error occurring between a reference signal and an output signal of a fractional divider (112) for feeding back an output of a VCO (115) of an output stage to a preceding stage is generated using an error signal from an accumulator (120). Through the use of the pulse signal, pulse widths of a UP signal and a DN signal output from a phase detector (140) are controlled so as to reduce a fractional phase error occurring between the UP signal and the DN signal. Thus, the fractional spurious caused by periodically switching the frequency division number of the fractional divider (112) is suppressed.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: April 28, 2015
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Eizo Ichihara
  • Patent number: 9019017
    Abstract: A digitally controlled oscillator has a high-order ?? modulator configured to be of at least an order higher than a first order and configured to input a digital control signal and output a pseudorandom digital output signal, a first-order ?? modulator configured to input the pseudorandom digital output signal and generate a control pulse signal including a pulse width corresponding to the pseudorandom digital output signal, a low pass filter configured to pass a low frequency component of the control pulse signal, and an oscillator configured to generate a high-frequency output signal whose frequency is controlled based on the control pulse signal outputted by the low pass filter so as to be a frequency corresponding to the digital control signal.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: April 28, 2015
    Assignees: Fujitsu Limited, Fujitsu Semiconductor Limited
    Inventors: Win Chaivipas, Masazumi Marutani, Daisuke Yamazaki