Tuning Compensation Patents (Class 331/16)
  • Patent number: 11902410
    Abstract: A Phase Locked Loop PLL circuit and method therein for generating multiphase output signals are disclosed. The PLL circuit includes a digitally controlled oscillator, a sample circuit, an analog to digital converter and a digital processing unit. The digital processing unit comprises a phase estimator configured to estimate a phase of the multiphase output signals, a differentiator configured to calculate a phase difference between a current phase and a previous phase, and an accumulator configured to accumulate the phase differences generated by the differentiator. The PLL circuit further comprises a loop filter configured to receive an output from the accumulator and generate a control signal to the digitally controlled oscillator to adjust frequency of the digitally controlled oscillator generating the multiphase output signals.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: February 13, 2024
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Henrik Sjöland
  • Patent number: 11881877
    Abstract: A method includes producing a plurality of TX LO signals by a first LO generator comprising a first frequency doubler and a first frequency divider, the first frequency doubler configured to receive a VCO signal having a first frequency and generate a first signal fed into the first frequency divider, the first signal having a second frequency that is twice the first frequency, producing a plurality of MRX LO signals by a second LO generator comprising a second frequency doubler and a second frequency divider, the second frequency doubler configured to receive the VCO signal and generate a second signal fed into the second frequency divider, the second signal having the second frequency, configuring the TX to operate at a first LO frequency equal to the second frequency, and configuring the MRX to operate at a second LO frequency equal to the first frequency through disabling the second frequency doubler.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: January 23, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Hong Jiang, Wael Al-Qaq, Zhihang Zhang
  • Patent number: 11847966
    Abstract: A shift register (SR) includes a voltage control circuit (110) and a bias compensation circuit (120). The voltage control circuit (110) is configured to control a voltage at a first node (Output) to be a first voltage or a second voltage. The bias compensation circuit (120) is configured to: when the voltage at the first node (Output) is the first voltage, transmit a first signal received by a first signal terminal (VDD-A) to a first signal output terminal (EM1), and transmit a second signal received by a second signal terminal (VDD-B) to a second signal output terminal (EM2); and in response to the voltage at the first node (Output) being the second voltage, transmit a signal received by a first voltage terminal (LVGL1) to the first signal output terminal (EM1) and the second signal output terminal (EM2).
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: December 19, 2023
    Assignee: Boe Technology Group Co., LTD.
    Inventors: Haoliang Zheng, Minghua Xuan, Dongni Liu, Zhenyu Zhang, Li Xiao, Liang Chen, Hao Chen, Jiao Zhao, Lijun Yuan, Yi Ouyang, Qi Qi
  • Patent number: 11817872
    Abstract: An IQ mixer is used in a Pound-stabilized microwave source to detect amplitude modulation of the signal reflected from the reference resonator. By properly configuring the IQ mixer so that the LO and RF inputs are maintained in quadrature at the Q mixer, hence in-phase at the I mixer, lower levels of amplitude modulation may be detected at lower modulation frequencies compatible with optimal choices of resonator coupling and maximal phase to amplitude conversion. With the Q mixer held in quadrature it acts as a broadband phase noise detector. A portion of the Q mixer output is bandpass filtered and summed with the I mixer Pound-server voltage to achieve both center frequency stabilization and broadband phase noise suppression.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: November 14, 2023
    Assignee: Raytheon Company
    Inventors: James Andrew Dervay, Gary Ian Moore
  • Patent number: 11804244
    Abstract: According to one embodiment, a magnetic disk device includes a controlled object, a controller which controls a motion of the controlled object, and loop shaping filters each connected in parallel to the controller. During a determination of coefficients of the loop shaping filters using a transfer function from outputs of the loop shaping filters to before an input of a disturbance affecting the controlled object, the first set of coefficients of each the loop shaping filter is determined by reflecting a frequency response of the other loop shaping filters, and the determined first sets of coefficients of the loop shaping filters are set to the loop shaping filters, respectively.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: October 31, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Takuji Matsuzawa
  • Patent number: 11791771
    Abstract: A method for calibrating a first clock signal output by an oscillation module to obtain a calibrated second clock signal includes obtaining a first count value by counting a third clock signal of an external device. A second count value is obtained by counting a scan signal of the oscillation module, and a first cycle ratio is obtained based on the first count value and the second count value. It is determined whether the first clock signal has a frequency deviation by comparing the first cycle ratio with a reference cycle ratio. A frequency division coefficient of the oscillation module is adjusted when the first clock signal has the frequency deviation, so that the oscillation module divides a frequency of the first clock signal according to the adjusted frequency division coefficient, thereby obtaining the calibrated second clock signal.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: October 17, 2023
    Assignee: FocalTech Electronics (Shenzhen) Co., Ltd.
    Inventors: Bei Xiao, Xiao-Lin Huang, Zhi-Qiang Luo
  • Patent number: 11777541
    Abstract: Embodiments of the present disclosure provide a circuit and a method for digital fingerprint generation, and an electronic device. The digital fingerprint generation method includes inputting an input signal from outside; generating a frequency relationship indication signal between an input signal and a feedback signal; generating a frequency control signal based on the frequency relationship indication signal; generating an intermediate signal based on a frequency control signal and pulse signals; dividing the intermediate signal in frequency to generate the feedback signal; and generating a digital fingerprint based on the input signal and the feedback signal.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: October 3, 2023
    Assignees: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD., BOE TECHNOLOGY GROUP CO. , LTD.
    Inventors: Xiangye Wei, Liming Xiu
  • Patent number: 11764913
    Abstract: A method for estimating jitter of a clock-signal-under-test includes generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal. The method includes generating N digital time codes for each phase adjustment of P phase adjustments of the phase-adjusted clock signal using a reference clock signal. Each digital time code of the N digital time codes corresponds to a first edge of a clock signal based on the phase-adjusted clock signal. P is a first integer greater than zero and N is a second integer greater than zero. The method includes generating a jitter estimate using an estimated standard deviation of a distribution of edges of the clock signal based on the N digital time codes for each of the P phase adjustments.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: September 19, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: Raghunandan K. Ranganathan, Kannanthodath V. Jayakumar, Srisai R. Seethamraju
  • Patent number: 11757547
    Abstract: An example apparatus as discussed herein includes a first communication circuit and a second communication circuit. A communication link couples the first communication circuit and the second communication circuit. The communication link conveys signals between the first communication circuit and the second communication circuit. The first communication circuit includes a first active inductor set to a first inductance; the first inductance controls a resonant frequency (carrier frequency) of communicating signals from the first communication circuit. The second communication circuit includes a second active inductor set to a second inductance. The second inductance controls a frequency response (such as band-pass resonant frequency) of a band-pass filter in the second communication circuit. The setting of the first inductance and the second inductance aligns the resonant frequency of the transmitted signals with respect to a peak or center frequency passed by the band-pass filter.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: September 12, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Filipe Esteves Tavora, Thomas Ferianz, Gernot Kasebacher
  • Patent number: 11736113
    Abstract: An automatic gain adjustor for a hybrid oscillator can be employed to overcome the frequency limitations of hybrid phase lock loops (PLLs). For example, an automatic gain adjustor for a hybrid oscillator can include a hybrid oscillator that is configured to receive a coarse tuning signal and a gain adjustment signal and generate an output signal with any frequency within the specified frequency range of the hybrid PLL. The automatic gain adjustor for a hybrid PLL may further include a fine tuning array that receives one or more fine tuning selection signals and generates a gain adjustment signal that is received by the hybrid oscillator. The fine tuning array generates a gain adjustment signal to adjust the gain of the hybrid oscillator according to an operating frequency range of the hybrid oscillator.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: August 22, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Hsien Tsai, Ya-Tin Chang, Ruey-Bin Sheen
  • Patent number: 11726545
    Abstract: Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: August 15, 2023
    Assignee: Intel Corporation
    Inventors: Shiva Rao, David Munday
  • Patent number: 11722161
    Abstract: A frequency modulation circuit can include: a modulation circuit configured to generate a digital modulation signal and an analog modulation signal according to an input signal of the frequency modulation circuit; and a phase-locked loop having a voltage-controlled oscillator configured to receive a reference frequency, and to modulate a frequency of an output signal of the voltage-controlled oscillator according to the analog modulation signal and the digital modulation signal.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: August 8, 2023
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Xunyu Zhu, Yan Ye
  • Patent number: 11714127
    Abstract: On-chip spread spectrum characterization including obtaining, from a skitter circuit, skitter data comprising a spread width corresponding to an amplitude of a spread of a spread spectrum clock signal; setting an offset pointer to a center of the spread width corresponding to the amplitude of the spread; retrieving, for each of a number of reference clock cycles, edge data indicating a location, within the spread width, of an edge of the spread spectrum during the reference clock cycle; incrementing, using the edge data, an offset counter for each reference clock cycle during which the edge of the spread spectrum crosses the offset pointer; and calculating a frequency of the spread spectrum using the offset counter and the number of reference clock cycles.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: August 1, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher W. Steffen, John P. Borkenhagen
  • Patent number: 11705874
    Abstract: A power amplifier circuit includes a first transistor having a first terminal to which a voltage corresponding to a variable power supply voltage is to be supplied and a second terminal to which a radio-frequency signal is to be supplied, the first transistor being configured to amplify the radio-frequency signal, a bias circuit configured to supply a bias current or voltage to the second terminal of the first transistor, and an adjustment circuit configured to adjust the bias current or voltage in accordance with the variable power supply voltage supplied from a power supply terminal.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: July 18, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Mitsunori Samata
  • Patent number: 11689206
    Abstract: A method for clock frequency monitoring for a Phase-Locked Loop (PLL) based design includes determining a present operating point of an oscillator of the PLL based design, wherein the oscillator generates a present frequency in response to the present operating point. The present operating point of the oscillator is compared to a comparison range defined by a plurality of reference operating points, wherein the oscillator generates a nominal reference frequency in response to a nominal one of the plurality of reference operating points and the comparison range is further defined by a manufacturing process range, an operating voltage range and an operating temperature range. An action is performed in response to the present operating point being outside of the comparison range.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: June 27, 2023
    Assignee: NXP B.V.
    Inventors: Ulrich Moehlmann, Andreas Lentz
  • Patent number: 11681140
    Abstract: Mirror control circuitry operates to control a movable mirror. The mirror control circuitry includes drive circuitry for providing a drive signal to the movable mirror, and a processor. The processor causes the drive circuitry to generate the drive signal so as to have pulses with leading edges occurring an offset period of time after a maximum opening angle of the movable mirror and trailing edges occurring an offset period of time before a zero crossing of the movable mirror. The processor may sample a mirror sense signal from the movable mirror at times at which a derivative of capacitance of the movable mirror with respect to time is zero, and then perform an action based upon the samples.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: June 20, 2023
    Assignee: STMicroelectronics Ltd
    Inventors: Sivan Kinstlich, Offir Duvdevany
  • Patent number: 11662226
    Abstract: A sensor device has a clock generator, a counter, an exciter device, a sensor element and an evaluation device, and outputs a sensor signal in response to a request signal having alternating leading and trailing edges. The counter reading is incremented differently, depending on whether the request signal has a leading/trailing edge between two successive leading or trailing edges of the clock signal. If the request signal has such a leading/trailing edge the counter corrects the counter reading. The value of the excitation signal outputted by the exciter device depends on the counter reading or a value derived therefrom. The sensor element outputs based on the excitation signal a raw signal, which is supplied to the evaluation device. The evaluation device determines based on this information whether to acquire the raw signal and how to take the raw signal into account when establishing the sensor signal.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: May 30, 2023
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Roland Finkler
  • Patent number: 11644860
    Abstract: A method for execution by one or more processing modules to configure a programmable drive-sense unit (DSU) includes determining one or more load sensing objectives based on sensing a load using the DSU that is configured to drive and simultaneously to sense the load via a single line. The method further includes determining one or more data processing objectives associated with sensing the load. The method further includes determining desired characteristics for the output data associated with sensing the load. The method further includes determining operational parameters for the DSU based on one or more of the load sensing objectives, the data processing objectives, and the desired characteristics for the output data. The method further includes configuring the DSU based on the operational parameters to achieve the one or more load sensing objectives.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: May 9, 2023
    Assignee: SigmaSense, LLC.
    Inventors: Richard Stuart Seger, Jr., Daniel Keith Van Ostrand, Patrick Troy Gray, Michael Shawn Gray, Timothy W. Markison
  • Patent number: 11592534
    Abstract: A system includes a power driver, configured to generate an electric excitation; an oscillating system, configured to perform an oscillation induced by the electric excitation; a feedback detector, configured to detect a feedback measurement signal with to the oscillation; and a controller configured to operate: in a closed loop mode, to control the power driver to generate the electric excitation as a discontinuous electric excitation according to timing information obtained from the detected feedback measurement signal, to synchronize the discontinuous electric excitation with the detected feedback measurement signal; in a learning mode preceding the closed loop mode, to control the power driver to generate the electric excitation as a continuous electric excitation, to obtain timing information from the feedback measurement signal to be used, at least once, in the subsequent closed loop mode, to synchronize the discontinuous electric excitation with the detected feedback measurement signal.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: February 28, 2023
    Assignee: Infineon Technologies AG
    Inventors: David Brunner, Georg Schitter, Han Woong Yoo
  • Patent number: 11527956
    Abstract: A control circuit for controlling switching operation of a switching stage of a converter includes a phase detector circuit that generates a pulse-width modulated (PWM) signal in response to a phase comparison of two clock signals. A first clock signal has a frequency determined as a function of a first feedback signal proportional to converter output voltage. A first transconductance amplifier generates a first current indicative of a difference between a reference voltage and the first feedback signal, and a second transconductance amplifier generates a second current indicative of a difference between the reference voltage and a second feedback signal proportional to a derivative of the converter output voltage. A delay line introduces a delay in the first clock signal that is dependent on the first and second currents as well as a compensation current dependent on a selected operational mode of the converter.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: December 13, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alessandro Bertolini, Alberto Cattani, Alessandro Gasparini
  • Patent number: 11476838
    Abstract: Various embodiments relate to a free running oscillator, including: a voltage controlled oscillator circuit including an input configured to receive an input voltage and an output configured to provide an oscillation signal, wherein the input voltage controls a frequency of the oscillation signal; a frequency to voltage circuit including an input configured to receive the oscillation signal and an output configured to produce a voltage dependent on a frequency of the oscillation signal; a comparison circuit including an input and an output comprising: a first amplifier including a first input, a second input, and an output, wherein the output is based upon a difference in voltage between the first input and the second input, wherein the first input received one of a reference voltage and the output of frequency to voltage circuit; a second amplifier including a first input, a second input, and an output, wherein the output is based upon a difference in voltage between the first input and the second input, fir
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: October 18, 2022
    Assignee: NXP B.V.
    Inventors: Sander Derksen, Jos Verlinden, Ids Christiaan Keekstra, Rene Verlinden
  • Patent number: 11463046
    Abstract: A resistor-capacitor (RC) oscillator with shared circuit architecture includes a current mirror circuit, a comparator circuit, a bias voltage generator, and a clock buffer. The current mirror circuit utilizes a plurality of transistors to perform current control, to adjust a second current on a second current path according to a first current on a first current path. The comparator circuit includes a first transistor, a second transistor, a resistor, and a capacitor, wherein a comparison result signal generated by the comparator circuit corresponds to a voltage of the capacitor. The bias voltage generator generates a bias voltage as a comparator reference voltage between the first transistor and the resistor. The clock buffer buffers the comparison result signal to generate an output signal. The bias voltage generator at least shares the resistor with the comparator circuit, and the RC oscillator may achieve targets of low cost and high performance.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: October 4, 2022
    Assignee: Artery Technology Company
    Inventors: Zhengxiang Wang, Gui Feng Zhou, Wei-Chih Chen
  • Patent number: 11438853
    Abstract: A method of performing device-to-device (D2D) communication by a user equipment (UE) in a wireless communication system includes receiving information on a synchronization type for the D2D communication; based on the information on the synchronization type, selecting a synchronization source for the D2D communication; and transmitting information on the synchronization source used by the UE. Further, based on the synchronization type being a first synchronization type, the UE uses a cell of a network as the synchronization source and based on the synchronization type being a second synchronization type, the UE uses an external synchronization source as the synchronization source.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: September 6, 2022
    Assignee: LG Electronics Inc.
    Inventors: Hanbyul Seo, Manyoung Jung
  • Patent number: 11438018
    Abstract: A frequency modulation circuit can include: a modulation circuit configured to generate a digital modulation signal and an analog modulation signal according to an input signal of the frequency modulation circuit; and a phase-locked loop having a voltage-controlled oscillator configured to receive a reference frequency, and to modulate a frequency of an output signal of the voltage-controlled oscillator according to the analog modulation signal and the digital modulation signal.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: September 6, 2022
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Xunyu Zhu, Yan Ye
  • Patent number: 11428720
    Abstract: A measuring arrangement acquires signals of alternating electrical magnitudes. A sampling apparatus performs a sampling of the signals to form digital sample values. A clock tracking apparatus adapts a sampling clock used by the sampling apparatus in the light of the frequency of the signal to be sampled. In order to be able to acquire reliably signals of alternating electrical magnitudes even when they have different frequencies, the sampling apparatus samples at least two of the signals each with its own sampling clock and the clock tracking apparatus adapts the sampling clock in the light of the frequency of the signal to be sampled simultaneously for each of these at least two signals. There is also described a corresponding method for measuring electrical signals.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: August 30, 2022
    Assignee: Siemens Aktiengesellschaft
    Inventors: Hans-Joachim Herrmann, Frank Mieske, Matthias Loerke
  • Patent number: 11424747
    Abstract: An all-digital phase locked loop (ADPLL) is provided. The ADPLL comprises a pattern generator adapted to generate a frequency control word (FCW) based on a predefined setting and a system clock. In addition, the ADPLL comprises a phase accumulator adapted to translate the FCW into a phase trajectory. The ADPLL further comprises a phase comparator adapted to generate a phase error signal representing a difference between the phase trajectory and the phase of an output oscillation frequency. Moreover, the ADPLL comprises a controller adapted to control a phase of the output oscillation frequency with respect to the phase trajectory.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: August 23, 2022
    Assignee: Stichting Imec Nederland
    Inventors: Johan van den Heuvel, Elbert Bechthum
  • Patent number: 11419580
    Abstract: Therapeutic ultrasound devices and methods are provided. In one embodiment, a therapeutic ultrasound device includes a housing configured for handheld operation by a user, an ultrasound assembly positioned within the housing and configured to generate ultrasound energy, a battery positioned in the housing and coupled to the ultrasound assembly to power the ultrasound assembly to generate the ultrasound energy, a flexible elongate member configured to be positioned within a body lumen of a patient, and an acoustic transmission member. The flexible elongate member includes a proximal portion, a distal portion, and a first lumen extending between the proximal portion and the distal portion. The housing is coupled to the proximal portion.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: August 23, 2022
    Assignee: PHILIPS IMAGE GUIDED THERAPY CORPORATION
    Inventors: Jeremy Stigall, Princeton Saroha
  • Patent number: 11411538
    Abstract: Embodiments provide for a tunable driving circuit by monitoring a frequency of a ring oscillator of an electrical integrated circuit connected to an optical modulator to determine operational characteristics of the electrical integrated circuit; setting, based on the operational characteristics, a driving voltage for a plurality of tunable inverters and a plurality of fixed gain inverters that control the optical modulator, wherein each tunable inverter of the plurality of tunable inverters is connected in parallel with a corresponding fixed gain inverter of the plurality of fixed gain inverters on one of a first arm and a second arm connected to the optical modulator; and setting an amplification strength for the plurality of tunable inverters based on the operational characteristics.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: August 9, 2022
    Assignee: Cisco Technology, Inc.
    Inventors: Craig S. Appel, Peter C. Metz, Joseph V. Pampanin, Sanjay Sunder
  • Patent number: 11405244
    Abstract: A single carrier transmission that minimizes spectral efficiency loss and reduces out of band emission by using adaptive filtering in a block where different filter parameters are used for different symbols within a block.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: August 2, 2022
    Inventors: Hüseyin Arslan, Seda Dogan, Armed Tusha
  • Patent number: 11374535
    Abstract: One or more heating elements are provided to heat a MEMS component (such as a resonator) to a temperature higher than an ambient temperature range in which the MEMS component is intended to operate—in effect, heating the MEMS component and optionally related circuitry to a steady-state “oven” temperature above that which would occur naturally during component operation and thereby avoiding temperature-dependent performance variance/instability (frequency, voltage, propagation delay, etc.). In a number of embodiments, an IC package is implemented with distinct temperature-isolated and temperature-interfaced regions, the former bearing or housing the MEMS component and subject to heating (i.e., to oven temperature) by the one or more heating elements while the latter is provided with (e.g., disposed adjacent) one or more heat dissipation paths to discharge heat generated by transistor circuitry (i.e., expel heat from the integrated circuit package).
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: June 28, 2022
    Assignee: SiTime Corporation
    Inventors: Carl Arft, Aaron Partridge, Markus Lutz, Charles I. Grosjean
  • Patent number: 11356061
    Abstract: The method of calibrating a two-point modulation phase locked loop (PLL) comprises observing, between the loop filter and the second injection point, the loop control signal over at least one period of the first periodic control signal; generating, from the observed loop control signal, a distortion profile; and applying the distortion profile to the second periodic control signal before injecting the second periodic control signal in the PLL. Since, in the case of non-linearity in the controlled oscillator, the PLL output deviates from the ideally expected one, cancellation through the first injection point becomes imperfect disturbing the loop. This error pattern can be observed on the loop filter which allows to generate a distortion profile to distort the second periodic control signal for the next period of the modulation. This will mitigate the effects of the non-linearity of the oscillator.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: June 7, 2022
    Assignee: IMEC VZW
    Inventors: Nereo Markulic, Jan Craninckx, Miguel Glassee
  • Patent number: 11336308
    Abstract: Disclosed is an electronic device. Other various embodiments as understood from the specification are also possible. The electronic device may include an antenna, a communication module including a transceiver, and a control circuit. The control circuit may be configured to radiate a first signal generated from the transceiver through the antenna, to obtain at least part of a second signal obtained by combining a forward signal delivered from the communication module to the antenna and a reverse signal reflected from the antenna, and to determine a reflection coefficient for the antenna based on at least part of the first signal and at least part of the second signal.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: May 17, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wonsub Lim, Seunghyun Oh, Hyoseok Na, Dongil Yang
  • Patent number: 11336289
    Abstract: According to a clock generator, an oscillator outputs source oscillation clocks which are trimmed according to a trimming code. A first frequency divider generates X frequency division clocks by frequency-dividing the source oscillation clocks by a first frequency division ratio X. A trimming controller changes the trimming code within a period of the X frequency division clocks and supplies the changed trimming code to the oscillator.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: May 17, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Hiroaki Kojima
  • Patent number: 11329658
    Abstract: An oscillator calibration circuit is presented. The oscillator calibration includes a first frequency locking circuit (FLC) coupled to a first oscillator, wherein the first FLC calibrates the frequency of the first oscillator using an over-the-air reference signal, wherein the first FLC calibrates the first oscillator prior to a data transmission session and remains free running during the data transmission session; and a second FLC coupled to a second oscillator, wherein the second FLC calibrates the frequency of the second oscillator using the over-the-air reference signal, wherein the second FLC calibrates the second oscillator immediately prior to a data transmission session and remains free running during the data transmission session.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: May 10, 2022
    Assignee: Wiliot, Ltd.
    Inventor: Alon Yehezkely
  • Patent number: 11309900
    Abstract: Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 19, 2022
    Assignee: Intel Corporation
    Inventors: Kuan-Yueh Shen, Nasser A. Kurd, John Fallin
  • Patent number: 11264060
    Abstract: Systems, apparatuses, and methods for dynamically generating a memory bitcell supply voltage rail from a logic supply voltage rail are disclosed. A circuit includes at least one or more comparators, control logic, and power stage circuitry. The circuit receives a logic supply voltage rail and compares the logic supply voltage rail to threshold voltage(s) using the comparator(s). Comparison signal(s) from the comparator(s) are coupled to the control logic. The control logic generates mode control signals based on the comparison signal(s) and based on a programmable dynamic range that is desired for a memory bitcell supply voltage rail. The mode control signals are provided to the power stage circuitry which generates the memory bitcell supply voltage rail from the logic supply voltage rail. A voltage level of the memory bitcell supply voltage rail can be above, below, or the same as the logic supply voltage rail.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: March 1, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Miguel Rodríguez, Stephen Victor Kosonocky, Casey Lee Hardy
  • Patent number: 11258450
    Abstract: Techniques are provided for reducing or mitigating phase noise of a digital phase lock loop or the system depending on the digital phase lock loop. In an example, a multiple-mode digital phase lock loop can include a digital phase lock loop (DPLL), multiple frequency scalers configured to receive a reference clock, and a multiplexer configured to receive a mode command signal and to couple an output of one of the multiple frequency scalers to an input of the DPLL in response to a state of the mode command signal.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: February 22, 2022
    Assignee: Intel Corporation
    Inventors: Niranjan Karandikar, Wayne Ballantyne, Gregory Chance, Simon Hughes, Daniel Schwartz, Nebil Tanzi
  • Patent number: 11258448
    Abstract: Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: February 22, 2022
    Assignee: Mixed-Signal Devices Inc.
    Inventors: Tommy Yu, Avanindra Madisetti
  • Patent number: 11255670
    Abstract: A microelectromechanical system (MEMS) gyroscope sensor has a sensing mass and a quadrature error compensation control loop for applying a force to the sensing mass to cancel quadrature error. To detect fault, the quadrature error compensation control loop is opened and an additional force is applied to produce a physical displacement of the sensing mass. A quadrature error resulting from the physical displacement of the sensing mass in response to the applied additional force is sensed. The sensed quadrature error is compared to an expected value corresponding to the applied additional force and a fault alert is generated if the comparison is not satisfied.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: February 22, 2022
    Assignee: STMicroelectronics, Inc.
    Inventors: Yamu Hu, Deyou Fang, David Mcclure, Huantong Zhang, Naren K. Sahoo
  • Patent number: 11252365
    Abstract: A clock generator and an image sensor including the same are disclosed, which relate to technology for improving an operation speed of a voltage controlled oscillator. The clock generator includes a phase frequency detector (PFD) configured to detect a phase difference between a clock signal and a reference clock signal, a voltage converter configured to adjust a current corresponding to a voltage level in response to an output signal of the phase frequency detector (PFD), a filter circuit configured to generate a control voltage by filtering an output signal of the voltage converter, a voltage pumping circuit configured to pump an output voltage of the voltage converter, and provide the control voltage having a pumped voltage level, and a voltage controlled oscillator configured to generate a clock signal, an oscillation frequency of which is adjusted, in response to the control voltage.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: February 15, 2022
    Assignee: SK hynix Inc.
    Inventor: Tae Gyu Kim
  • Patent number: 11249130
    Abstract: A system comprises a noise generator circuit and a noise envelope detector circuit. The noise generator circuit comprises a first amplifier including a single transistor pair that is operable to generate 1/f noise, an output amplifier coupled to the first amplifier and configured to generate a 1/f noise signal as a function of the 1/f noise. The noise envelope detector circuit comprises a low pass filter operable to pass low frequency signals of the 1/f noise signal as a filtered 1/f noise signal, and a second amplifier or a comparator coupled to the low pass filter and operable to output a direct current (DC) voltage signal according to an envelope of the filtered 1/f noise signal, where the DC voltage signal is a function of an envelope of the filtered 1/f noise signal.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: February 15, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yuguo Wang, Steven Loveless, Tathagata Chatterjee, Jerry Doorenbos
  • Patent number: 11228403
    Abstract: A method for estimating jitter of a clock signal includes generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal. The method generating N digital time codes for each phase adjustment of P phase adjustments of the phase-adjusted clock signal using a reference clock signal. Each digital time code of the N digital time codes corresponds to a first edge of a clock signal based on the frequency-divided clock signal. P is a first integer greater than zero and N is a second integer greater than zero. The method includes generating a jitter indicator based on an expected period of the clock signal and the N digital time codes for each phase adjustment of the P phase adjustments.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: January 18, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventors: Raghunandan K. Ranganathan, Kannanthodath V. Jayakumar, Srisai R. Seethamraju
  • Patent number: 11196410
    Abstract: A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: December 7, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Zhengzheng Wu, Xu Zhang, Xuhao Huang
  • Patent number: 11177738
    Abstract: An apparatus includes a phase frequency detector having a detector output and first and second inputs, the phase frequency detector configured to provide a phase difference signal at the detector output responsive to the first and second inputs. The apparatus also includes a gain controller having a controller input and a controller output, the controller input coupled to the detector output, and the gain controller configured to provide a digital value at the controller output responsive to the phase difference signal and a duty cycle. The apparatus also includes a pulse generator having a generator output and first and second generator inputs, the first generator input coupled to the controller output, the second generator input coupled to the second detector input, the pulse generator configured to provide a generator signal at the generator output responsive to the digital value and the second generator input.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: November 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Janne Matias Pahkala, Juha Olavi Hauru
  • Patent number: 11152890
    Abstract: A voltage controlled oscillator (VCO) circuit employing digital amplitude control of the output oscillating signal and method of operation. The digital control is provided by an analog to digital converter (ADC) element that is shared among many other operating blocks in a system. In a configuration, the oscillator current is obtained by implementing transistors in a linear region and controlling them digitally. The optimum amplitude detection is performed by measuring the DC voltage at the common mode nodes in the oscillator, and is realized using reduced time compared to an extensive frequency measurement over a long time window. The digital control is implemented using an on-chip regulator, and employs digital controls for adjusting the current consumption which leads to low on-chip area overhead, low cost, and a scalable implementation. In an implementation, a one-time code can be obtained for optimum phase noise operation when providing the digital amplitude control.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Bruce B. Doris
  • Patent number: 11139819
    Abstract: A parameter determination method for a spread spectrum circuit, a clock spread spectrum method, a parameter determination device for a spread spectrum circuit, and a clock spread spectrum device are disclosed. The parameter determination method for the spread spectrum circuit includes: obtaining a base time unit and a target frequency; determining a spread spectrum depth coefficient according to the base time unit and the target frequency; determining whether the spread spectrum depth coefficient is greater than or equal to a base spread spectrum depth coefficient; if yes, determining the spread spectrum depth coefficient as a standard spread spectrum depth coefficient and determining a standard frequency control word according to the standard spread spectrum depth coefficient; and if no, adjusting the base time unit until a corresponding spread spectrum depth coefficient corresponding to the base time unit is greater than or equal to the base spread spectrum depth coefficient.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: October 5, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yuhai Ma, Xiangye Wei, Liming Xiu, Yiming Bai
  • Patent number: 11095297
    Abstract: A voltage controlled oscillator (VCO) circuit generates an output signal having a frequency which is dependent on a control voltage. A current is generated which is itself dependent on an amplitude of the VCO circuit. The generated current accordingly tracks, to an extent, the temperature behavior of the oscillator within the VCO circuit. The oscillator is driven by the sum of the generated current and a control current dependent on the control voltage. The control voltage may, for example, be generated by a phase lock loop (PLL).
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: August 17, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Nitin Gupta, Sagnik Mukherjee
  • Patent number: 11088691
    Abstract: An oscillation circuit has a voltage generator configured to generate a linearly changing voltage, a voltage level of which linearly changes as time passes, a first comparator configured to compare the linearly changing voltage with a first reference voltage, a second comparator configured to compare the linearly changing voltage with a second reference voltage having a higher voltage level than the first reference voltage, a time-to-digital converter configured to output a bit sequence signal in accordance with a time difference between a time when the first comparator detects that the linearly changing voltage matches the first reference voltage and a time when the second comparator detects that the linearly changing voltage matches the second reference voltage, and an oscillator configured to generate an oscillation signal that oscillates at a frequency according to the bit sequence signal.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: August 10, 2021
    Assignee: Kioxia Corporation
    Inventor: Hiroo Yabe
  • Patent number: 11012079
    Abstract: A phase locked loop (PLL) control system includes a voltage-controlled oscillator (VCO) circuit including an inductor and a plurality of capacitors arranged in parallel with the inductor. Digitally enabling or disabling the capacitors in a thermometer coded manner via switches creates tuning states that provide additional frequency range, and each has a limited range of VCO frequency tuning. Slowly ramping the switched capacitance, by implementing the capacitor as a varactor, from one thermal code to the next, provides a wider continuous VCO frequency tuning range for use in the PLL. The slow transition between tuning states allows the PLL to remain in lock, useful under changing operating conditions. Specifically, under changing operating conditions, digital logic detects the PLL tuning control voltage approaching the edge of a VCO band and will add/reduce VCO capacitance effectively transitioning into the adjacent VCO band while the PLL maintains lock via its normal feedback loop.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 18, 2021
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Joseph D. Cali, Curtis M. Grens, Richard L. Harwood, Gary M. Madison
  • Patent number: 10998909
    Abstract: A sensing device with a phase locked loop circuit that has an oscillator to provide an oscillator output signal is presented. The sensing device has a power amplifier to provide at an output of the power amplifier an amplified output signal based on the oscillator output signal. The amplified output signal has an interfering signal component at the oscillator frequency. The sensing device has a measurement circuit to measure offset information regarding a frequency offset between the oscillator frequency and a target frequency of the oscillator. The frequency offset is due to a frequency pulling effect at the oscillator caused by the interfering signal component of the amplified output signal. The sensing device has a control circuit to use the offset information for trimming the phase locked loop circuit and/or the power amplifier, and/or for determining information regarding an environmental situation at the output of the power amplifier.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: May 4, 2021
    Assignee: Dialog Semiconductor B.V.
    Inventor: Johannes Gerardus Willms