Tuning Compensation Patents (Class 331/16)
  • Patent number: 11476838
    Abstract: Various embodiments relate to a free running oscillator, including: a voltage controlled oscillator circuit including an input configured to receive an input voltage and an output configured to provide an oscillation signal, wherein the input voltage controls a frequency of the oscillation signal; a frequency to voltage circuit including an input configured to receive the oscillation signal and an output configured to produce a voltage dependent on a frequency of the oscillation signal; a comparison circuit including an input and an output comprising: a first amplifier including a first input, a second input, and an output, wherein the output is based upon a difference in voltage between the first input and the second input, wherein the first input received one of a reference voltage and the output of frequency to voltage circuit; a second amplifier including a first input, a second input, and an output, wherein the output is based upon a difference in voltage between the first input and the second input, fir
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: October 18, 2022
    Assignee: NXP B.V.
    Inventors: Sander Derksen, Jos Verlinden, Ids Christiaan Keekstra, Rene Verlinden
  • Patent number: 11463046
    Abstract: A resistor-capacitor (RC) oscillator with shared circuit architecture includes a current mirror circuit, a comparator circuit, a bias voltage generator, and a clock buffer. The current mirror circuit utilizes a plurality of transistors to perform current control, to adjust a second current on a second current path according to a first current on a first current path. The comparator circuit includes a first transistor, a second transistor, a resistor, and a capacitor, wherein a comparison result signal generated by the comparator circuit corresponds to a voltage of the capacitor. The bias voltage generator generates a bias voltage as a comparator reference voltage between the first transistor and the resistor. The clock buffer buffers the comparison result signal to generate an output signal. The bias voltage generator at least shares the resistor with the comparator circuit, and the RC oscillator may achieve targets of low cost and high performance.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: October 4, 2022
    Assignee: Artery Technology Company
    Inventors: Zhengxiang Wang, Gui Feng Zhou, Wei-Chih Chen
  • Patent number: 11438018
    Abstract: A frequency modulation circuit can include: a modulation circuit configured to generate a digital modulation signal and an analog modulation signal according to an input signal of the frequency modulation circuit; and a phase-locked loop having a voltage-controlled oscillator configured to receive a reference frequency, and to modulate a frequency of an output signal of the voltage-controlled oscillator according to the analog modulation signal and the digital modulation signal.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: September 6, 2022
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Xunyu Zhu, Yan Ye
  • Patent number: 11438853
    Abstract: A method of performing device-to-device (D2D) communication by a user equipment (UE) in a wireless communication system includes receiving information on a synchronization type for the D2D communication; based on the information on the synchronization type, selecting a synchronization source for the D2D communication; and transmitting information on the synchronization source used by the UE. Further, based on the synchronization type being a first synchronization type, the UE uses a cell of a network as the synchronization source and based on the synchronization type being a second synchronization type, the UE uses an external synchronization source as the synchronization source.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: September 6, 2022
    Assignee: LG Electronics Inc.
    Inventors: Hanbyul Seo, Manyoung Jung
  • Patent number: 11428720
    Abstract: A measuring arrangement acquires signals of alternating electrical magnitudes. A sampling apparatus performs a sampling of the signals to form digital sample values. A clock tracking apparatus adapts a sampling clock used by the sampling apparatus in the light of the frequency of the signal to be sampled. In order to be able to acquire reliably signals of alternating electrical magnitudes even when they have different frequencies, the sampling apparatus samples at least two of the signals each with its own sampling clock and the clock tracking apparatus adapts the sampling clock in the light of the frequency of the signal to be sampled simultaneously for each of these at least two signals. There is also described a corresponding method for measuring electrical signals.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: August 30, 2022
    Assignee: Siemens Aktiengesellschaft
    Inventors: Hans-Joachim Herrmann, Frank Mieske, Matthias Loerke
  • Patent number: 11424747
    Abstract: An all-digital phase locked loop (ADPLL) is provided. The ADPLL comprises a pattern generator adapted to generate a frequency control word (FCW) based on a predefined setting and a system clock. In addition, the ADPLL comprises a phase accumulator adapted to translate the FCW into a phase trajectory. The ADPLL further comprises a phase comparator adapted to generate a phase error signal representing a difference between the phase trajectory and the phase of an output oscillation frequency. Moreover, the ADPLL comprises a controller adapted to control a phase of the output oscillation frequency with respect to the phase trajectory.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: August 23, 2022
    Assignee: Stichting Imec Nederland
    Inventors: Johan van den Heuvel, Elbert Bechthum
  • Patent number: 11419580
    Abstract: Therapeutic ultrasound devices and methods are provided. In one embodiment, a therapeutic ultrasound device includes a housing configured for handheld operation by a user, an ultrasound assembly positioned within the housing and configured to generate ultrasound energy, a battery positioned in the housing and coupled to the ultrasound assembly to power the ultrasound assembly to generate the ultrasound energy, a flexible elongate member configured to be positioned within a body lumen of a patient, and an acoustic transmission member. The flexible elongate member includes a proximal portion, a distal portion, and a first lumen extending between the proximal portion and the distal portion. The housing is coupled to the proximal portion.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: August 23, 2022
    Assignee: PHILIPS IMAGE GUIDED THERAPY CORPORATION
    Inventors: Jeremy Stigall, Princeton Saroha
  • Patent number: 11411538
    Abstract: Embodiments provide for a tunable driving circuit by monitoring a frequency of a ring oscillator of an electrical integrated circuit connected to an optical modulator to determine operational characteristics of the electrical integrated circuit; setting, based on the operational characteristics, a driving voltage for a plurality of tunable inverters and a plurality of fixed gain inverters that control the optical modulator, wherein each tunable inverter of the plurality of tunable inverters is connected in parallel with a corresponding fixed gain inverter of the plurality of fixed gain inverters on one of a first arm and a second arm connected to the optical modulator; and setting an amplification strength for the plurality of tunable inverters based on the operational characteristics.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: August 9, 2022
    Assignee: Cisco Technology, Inc.
    Inventors: Craig S. Appel, Peter C. Metz, Joseph V. Pampanin, Sanjay Sunder
  • Patent number: 11405244
    Abstract: A single carrier transmission that minimizes spectral efficiency loss and reduces out of band emission by using adaptive filtering in a block where different filter parameters are used for different symbols within a block.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: August 2, 2022
    Inventors: Hüseyin Arslan, Seda Dogan, Armed Tusha
  • Patent number: 11374535
    Abstract: One or more heating elements are provided to heat a MEMS component (such as a resonator) to a temperature higher than an ambient temperature range in which the MEMS component is intended to operate—in effect, heating the MEMS component and optionally related circuitry to a steady-state “oven” temperature above that which would occur naturally during component operation and thereby avoiding temperature-dependent performance variance/instability (frequency, voltage, propagation delay, etc.). In a number of embodiments, an IC package is implemented with distinct temperature-isolated and temperature-interfaced regions, the former bearing or housing the MEMS component and subject to heating (i.e., to oven temperature) by the one or more heating elements while the latter is provided with (e.g., disposed adjacent) one or more heat dissipation paths to discharge heat generated by transistor circuitry (i.e., expel heat from the integrated circuit package).
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: June 28, 2022
    Assignee: SiTime Corporation
    Inventors: Carl Arft, Aaron Partridge, Markus Lutz, Charles I. Grosjean
  • Patent number: 11356061
    Abstract: The method of calibrating a two-point modulation phase locked loop (PLL) comprises observing, between the loop filter and the second injection point, the loop control signal over at least one period of the first periodic control signal; generating, from the observed loop control signal, a distortion profile; and applying the distortion profile to the second periodic control signal before injecting the second periodic control signal in the PLL. Since, in the case of non-linearity in the controlled oscillator, the PLL output deviates from the ideally expected one, cancellation through the first injection point becomes imperfect disturbing the loop. This error pattern can be observed on the loop filter which allows to generate a distortion profile to distort the second periodic control signal for the next period of the modulation. This will mitigate the effects of the non-linearity of the oscillator.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: June 7, 2022
    Assignee: IMEC VZW
    Inventors: Nereo Markulic, Jan Craninckx, Miguel Glassee
  • Patent number: 11336308
    Abstract: Disclosed is an electronic device. Other various embodiments as understood from the specification are also possible. The electronic device may include an antenna, a communication module including a transceiver, and a control circuit. The control circuit may be configured to radiate a first signal generated from the transceiver through the antenna, to obtain at least part of a second signal obtained by combining a forward signal delivered from the communication module to the antenna and a reverse signal reflected from the antenna, and to determine a reflection coefficient for the antenna based on at least part of the first signal and at least part of the second signal.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: May 17, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wonsub Lim, Seunghyun Oh, Hyoseok Na, Dongil Yang
  • Patent number: 11336289
    Abstract: According to a clock generator, an oscillator outputs source oscillation clocks which are trimmed according to a trimming code. A first frequency divider generates X frequency division clocks by frequency-dividing the source oscillation clocks by a first frequency division ratio X. A trimming controller changes the trimming code within a period of the X frequency division clocks and supplies the changed trimming code to the oscillator.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: May 17, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Hiroaki Kojima
  • Patent number: 11329658
    Abstract: An oscillator calibration circuit is presented. The oscillator calibration includes a first frequency locking circuit (FLC) coupled to a first oscillator, wherein the first FLC calibrates the frequency of the first oscillator using an over-the-air reference signal, wherein the first FLC calibrates the first oscillator prior to a data transmission session and remains free running during the data transmission session; and a second FLC coupled to a second oscillator, wherein the second FLC calibrates the frequency of the second oscillator using the over-the-air reference signal, wherein the second FLC calibrates the second oscillator immediately prior to a data transmission session and remains free running during the data transmission session.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: May 10, 2022
    Assignee: Wiliot, Ltd.
    Inventor: Alon Yehezkely
  • Patent number: 11309900
    Abstract: Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 19, 2022
    Assignee: Intel Corporation
    Inventors: Kuan-Yueh Shen, Nasser A. Kurd, John Fallin
  • Patent number: 11264060
    Abstract: Systems, apparatuses, and methods for dynamically generating a memory bitcell supply voltage rail from a logic supply voltage rail are disclosed. A circuit includes at least one or more comparators, control logic, and power stage circuitry. The circuit receives a logic supply voltage rail and compares the logic supply voltage rail to threshold voltage(s) using the comparator(s). Comparison signal(s) from the comparator(s) are coupled to the control logic. The control logic generates mode control signals based on the comparison signal(s) and based on a programmable dynamic range that is desired for a memory bitcell supply voltage rail. The mode control signals are provided to the power stage circuitry which generates the memory bitcell supply voltage rail from the logic supply voltage rail. A voltage level of the memory bitcell supply voltage rail can be above, below, or the same as the logic supply voltage rail.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: March 1, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Miguel Rodríguez, Stephen Victor Kosonocky, Casey Lee Hardy
  • Patent number: 11255670
    Abstract: A microelectromechanical system (MEMS) gyroscope sensor has a sensing mass and a quadrature error compensation control loop for applying a force to the sensing mass to cancel quadrature error. To detect fault, the quadrature error compensation control loop is opened and an additional force is applied to produce a physical displacement of the sensing mass. A quadrature error resulting from the physical displacement of the sensing mass in response to the applied additional force is sensed. The sensed quadrature error is compared to an expected value corresponding to the applied additional force and a fault alert is generated if the comparison is not satisfied.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: February 22, 2022
    Assignee: STMicroelectronics, Inc.
    Inventors: Yamu Hu, Deyou Fang, David Mcclure, Huantong Zhang, Naren K. Sahoo
  • Patent number: 11258450
    Abstract: Techniques are provided for reducing or mitigating phase noise of a digital phase lock loop or the system depending on the digital phase lock loop. In an example, a multiple-mode digital phase lock loop can include a digital phase lock loop (DPLL), multiple frequency scalers configured to receive a reference clock, and a multiplexer configured to receive a mode command signal and to couple an output of one of the multiple frequency scalers to an input of the DPLL in response to a state of the mode command signal.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: February 22, 2022
    Assignee: Intel Corporation
    Inventors: Niranjan Karandikar, Wayne Ballantyne, Gregory Chance, Simon Hughes, Daniel Schwartz, Nebil Tanzi
  • Patent number: 11258448
    Abstract: Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: February 22, 2022
    Assignee: Mixed-Signal Devices Inc.
    Inventors: Tommy Yu, Avanindra Madisetti
  • Patent number: 11249130
    Abstract: A system comprises a noise generator circuit and a noise envelope detector circuit. The noise generator circuit comprises a first amplifier including a single transistor pair that is operable to generate 1/f noise, an output amplifier coupled to the first amplifier and configured to generate a 1/f noise signal as a function of the 1/f noise. The noise envelope detector circuit comprises a low pass filter operable to pass low frequency signals of the 1/f noise signal as a filtered 1/f noise signal, and a second amplifier or a comparator coupled to the low pass filter and operable to output a direct current (DC) voltage signal according to an envelope of the filtered 1/f noise signal, where the DC voltage signal is a function of an envelope of the filtered 1/f noise signal.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: February 15, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yuguo Wang, Steven Loveless, Tathagata Chatterjee, Jerry Doorenbos
  • Patent number: 11252365
    Abstract: A clock generator and an image sensor including the same are disclosed, which relate to technology for improving an operation speed of a voltage controlled oscillator. The clock generator includes a phase frequency detector (PFD) configured to detect a phase difference between a clock signal and a reference clock signal, a voltage converter configured to adjust a current corresponding to a voltage level in response to an output signal of the phase frequency detector (PFD), a filter circuit configured to generate a control voltage by filtering an output signal of the voltage converter, a voltage pumping circuit configured to pump an output voltage of the voltage converter, and provide the control voltage having a pumped voltage level, and a voltage controlled oscillator configured to generate a clock signal, an oscillation frequency of which is adjusted, in response to the control voltage.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: February 15, 2022
    Assignee: SK hynix Inc.
    Inventor: Tae Gyu Kim
  • Patent number: 11228403
    Abstract: A method for estimating jitter of a clock signal includes generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal. The method generating N digital time codes for each phase adjustment of P phase adjustments of the phase-adjusted clock signal using a reference clock signal. Each digital time code of the N digital time codes corresponds to a first edge of a clock signal based on the frequency-divided clock signal. P is a first integer greater than zero and N is a second integer greater than zero. The method includes generating a jitter indicator based on an expected period of the clock signal and the N digital time codes for each phase adjustment of the P phase adjustments.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: January 18, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventors: Raghunandan K. Ranganathan, Kannanthodath V. Jayakumar, Srisai R. Seethamraju
  • Patent number: 11196410
    Abstract: A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: December 7, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Zhengzheng Wu, Xu Zhang, Xuhao Huang
  • Patent number: 11177738
    Abstract: An apparatus includes a phase frequency detector having a detector output and first and second inputs, the phase frequency detector configured to provide a phase difference signal at the detector output responsive to the first and second inputs. The apparatus also includes a gain controller having a controller input and a controller output, the controller input coupled to the detector output, and the gain controller configured to provide a digital value at the controller output responsive to the phase difference signal and a duty cycle. The apparatus also includes a pulse generator having a generator output and first and second generator inputs, the first generator input coupled to the controller output, the second generator input coupled to the second detector input, the pulse generator configured to provide a generator signal at the generator output responsive to the digital value and the second generator input.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: November 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Janne Matias Pahkala, Juha Olavi Hauru
  • Patent number: 11152890
    Abstract: A voltage controlled oscillator (VCO) circuit employing digital amplitude control of the output oscillating signal and method of operation. The digital control is provided by an analog to digital converter (ADC) element that is shared among many other operating blocks in a system. In a configuration, the oscillator current is obtained by implementing transistors in a linear region and controlling them digitally. The optimum amplitude detection is performed by measuring the DC voltage at the common mode nodes in the oscillator, and is realized using reduced time compared to an extensive frequency measurement over a long time window. The digital control is implemented using an on-chip regulator, and employs digital controls for adjusting the current consumption which leads to low on-chip area overhead, low cost, and a scalable implementation. In an implementation, a one-time code can be obtained for optimum phase noise operation when providing the digital amplitude control.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Bruce B. Doris
  • Patent number: 11139819
    Abstract: A parameter determination method for a spread spectrum circuit, a clock spread spectrum method, a parameter determination device for a spread spectrum circuit, and a clock spread spectrum device are disclosed. The parameter determination method for the spread spectrum circuit includes: obtaining a base time unit and a target frequency; determining a spread spectrum depth coefficient according to the base time unit and the target frequency; determining whether the spread spectrum depth coefficient is greater than or equal to a base spread spectrum depth coefficient; if yes, determining the spread spectrum depth coefficient as a standard spread spectrum depth coefficient and determining a standard frequency control word according to the standard spread spectrum depth coefficient; and if no, adjusting the base time unit until a corresponding spread spectrum depth coefficient corresponding to the base time unit is greater than or equal to the base spread spectrum depth coefficient.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: October 5, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yuhai Ma, Xiangye Wei, Liming Xiu, Yiming Bai
  • Patent number: 11095297
    Abstract: A voltage controlled oscillator (VCO) circuit generates an output signal having a frequency which is dependent on a control voltage. A current is generated which is itself dependent on an amplitude of the VCO circuit. The generated current accordingly tracks, to an extent, the temperature behavior of the oscillator within the VCO circuit. The oscillator is driven by the sum of the generated current and a control current dependent on the control voltage. The control voltage may, for example, be generated by a phase lock loop (PLL).
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: August 17, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Nitin Gupta, Sagnik Mukherjee
  • Patent number: 11088691
    Abstract: An oscillation circuit has a voltage generator configured to generate a linearly changing voltage, a voltage level of which linearly changes as time passes, a first comparator configured to compare the linearly changing voltage with a first reference voltage, a second comparator configured to compare the linearly changing voltage with a second reference voltage having a higher voltage level than the first reference voltage, a time-to-digital converter configured to output a bit sequence signal in accordance with a time difference between a time when the first comparator detects that the linearly changing voltage matches the first reference voltage and a time when the second comparator detects that the linearly changing voltage matches the second reference voltage, and an oscillator configured to generate an oscillation signal that oscillates at a frequency according to the bit sequence signal.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: August 10, 2021
    Assignee: Kioxia Corporation
    Inventor: Hiroo Yabe
  • Patent number: 11012079
    Abstract: A phase locked loop (PLL) control system includes a voltage-controlled oscillator (VCO) circuit including an inductor and a plurality of capacitors arranged in parallel with the inductor. Digitally enabling or disabling the capacitors in a thermometer coded manner via switches creates tuning states that provide additional frequency range, and each has a limited range of VCO frequency tuning. Slowly ramping the switched capacitance, by implementing the capacitor as a varactor, from one thermal code to the next, provides a wider continuous VCO frequency tuning range for use in the PLL. The slow transition between tuning states allows the PLL to remain in lock, useful under changing operating conditions. Specifically, under changing operating conditions, digital logic detects the PLL tuning control voltage approaching the edge of a VCO band and will add/reduce VCO capacitance effectively transitioning into the adjacent VCO band while the PLL maintains lock via its normal feedback loop.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 18, 2021
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Joseph D. Cali, Curtis M. Grens, Richard L. Harwood, Gary M. Madison
  • Patent number: 10998909
    Abstract: A sensing device with a phase locked loop circuit that has an oscillator to provide an oscillator output signal is presented. The sensing device has a power amplifier to provide at an output of the power amplifier an amplified output signal based on the oscillator output signal. The amplified output signal has an interfering signal component at the oscillator frequency. The sensing device has a measurement circuit to measure offset information regarding a frequency offset between the oscillator frequency and a target frequency of the oscillator. The frequency offset is due to a frequency pulling effect at the oscillator caused by the interfering signal component of the amplified output signal. The sensing device has a control circuit to use the offset information for trimming the phase locked loop circuit and/or the power amplifier, and/or for determining information regarding an environmental situation at the output of the power amplifier.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: May 4, 2021
    Assignee: Dialog Semiconductor B.V.
    Inventor: Johannes Gerardus Willms
  • Patent number: 10976862
    Abstract: Exemplary embodiments of the present disclosure relate to a touch driving circuit that operates according to an internal clock signal and a touch controller that calibrates a variation in internal clock signal between touch driving circuits. The touch driving circuit operates using an internal clock signal, thus preventing electromagnetic interference caused by a clock signal line that connects the touch controller and a plurality of touch driving circuits. Further, the touch controller calibrates the output frequencies of internal clock signals of the respective touch driving circuits to be the same on the basis of the counting values of the internal clock signals of the touch driving circuits, which are obtained during a certain period before performing touch sensing, and performs touch sensing, thereby performing touch sensing while controlling the plurality of touch driving circuits operating with the internal clock signals without any operational variation.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: April 13, 2021
    Assignee: LG Display Co., Ltd.
    Inventor: Yongwoo Choi
  • Patent number: 10949915
    Abstract: Embodiments are directed towards employing a non-repudiation process for consumer credit requests based on an affirmative authentication of a one-time-pin (“OTP”) generated from a consumer biometric smartcard. The biometric smartcard may authenticate biometric information (e.g. fingerprint, facial image, iris image, or the like) of the consumer based on biometric templates stored on the biometric smartcard. In at least some of the various embodiments, the OTP may be authenticated by an identity authority, such that an associated credit request to a provider may be authenticated. In some embodiments, the provider may request and utilize a credit report for an authentic credit request to determine whether or not the consumer has an acceptable credit rating. If the consumer has an acceptable credit rating, then the provider may provide credit to the consumer.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: March 16, 2021
    Assignee: CreditRegistry Corporation
    Inventors: Taiwo Ayedun, Jameelah Ayedun
  • Patent number: 10951165
    Abstract: A switched capacitor arrangement for tuning a differential circuit is disclosed. The switched capacitor arrangement comprises a first node, a second node and a third node. The switched capacitor arrangement further comprises a first capacitor coupled between the first node and the second node, a second capacitor coupled between the second node and the third node, and a first switch branch comprising a first switch coupled between the second node and a signal ground node. The first switch has an on state and an off state. The first node and third node are configured to be connected to respective differential nodes of the differential circuit. The switched capacitor arrangement is configured to tune the differential circuit by controlling the state of the first switch.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: March 16, 2021
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Henrik Sjoland, Torbjorn Sandstrom
  • Patent number: 10944541
    Abstract: Systems, methods, and circuitries are provided for resonator-based local oscillator signal generation for receiving self-interference signals. An interference cancellation system for a transceiver includes a resonator configured to generate a high-frequency signal and a local oscillator circuitry. The local oscillator circuitry includes a digital-to time converter configured to receive the high-frequency signal and, in response, generate a clock signal for receiving an interfering signal having an interference frequency. Digital cancellation circuitry is configured to adapt operation of the transceiver based, at least in part, on the received interfering signal.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventor: Zdravko Boos
  • Patent number: 10924123
    Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: February 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Debapriya Sahu, Rittu Sachdev
  • Patent number: 10867165
    Abstract: A gesture recognition system includes a transmission unit, a first reception chain, a second reception chain, a customized gesture collection engine and a machine learning accelerator. The transmission unit is used to transmit a transmission signal to detect a gesture. The first reception chain is used to receive a first signal and generate first feature map data corresponding to the first signal. The second reception chain is used to receive a second signal and generate second feature map data corresponding to the second signal. The first signal and the second signal are generated by the gesture reflecting the transmission signal. The customized gesture collection engine is used to generate gesture data according to at least the first feature map data and the second feature map data. The machine learning accelerator is used to perform machine learning with the gesture data.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: December 15, 2020
    Assignee: KaiKuTek INC.
    Inventor: Mike Chun Hung Wang
  • Patent number: 10868551
    Abstract: A mechanism is provided for detecting errors and parametric deviations in phase-locked loops (PLLs) by measuring the effectiveness of a PLL in recovering from an introduced delay in phase at a phase comparator of the PLL. Embodiments measure a proxy for the area under a phase difference recovery curve of the PLL. If the phase difference recovery is out of predefined thresholds for the PLL, then an error in the PLL is flagged or responded to. In some embodiments, the PLL is automatically re-trimmed to bring the PLL back within the predefined thresholds.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: December 15, 2020
    Assignee: NXP B.V.
    Inventor: Jan-Peter Schat
  • Patent number: 10862427
    Abstract: A two-point modulation Phase-Locked Loop (PLL) has a dual-input Voltage-Controlled Oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to an offset Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. The loop path through the VCO has a higher gain than the DAC path through the VCO, which has better linearity. A calibration unit divides the VCO output and counts pulses. The offset DAC has a data input and a gain input. During calibration, the data input of the DAC is set to minimum and then maximum values and VCO output pulses counted, and repeated for two values of the gain input to the DAC. From the four counts a K(DAC) calculator calculates the calibrated gain to apply to the gain input of the offset DAC.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: December 8, 2020
    Assignee: Hong Kong Applied Science and Technology Research Institute Company, Limited
    Inventor: Tat Fu Chan
  • Patent number: 10848138
    Abstract: A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period; a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 10848163
    Abstract: An example frequency converter includes a drift canceling loop with a balanced delay and a linear signal path (e.g., linear with respect to frequency scaling, amplitude modulation, and/or phase modulation). One side of the drift canceling loop includes a fixed delay, and the opposite side includes an adjustable, complementary delay. The adjustable, complementary delay facilitates precision matching of the signal delays on each side of the loop over a range of frequencies, which results in a significant improvement in noise cancellation, particularly at large offsets to the carrier, while permitting the use of a higher noise, but very fast tuning course scale oscillator. The linear signal path from the signal generator to an RF output facilitates modulation of the signal by the signal generator. A modular format is an advantageous embodiment of the invention that includes the removal of the frequency synthesizer's low phase noise reference into a separate module.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: November 24, 2020
    Assignee: Giga-tronics Incorporated
    Inventors: John R. Regazzi, Charles Lewis, Carlos Fuentes
  • Patent number: 10840923
    Abstract: For example, a digital PLL may include a digitally controlled Ring Oscillator (DCRO) configured to generate a frequency output based on a control signal, the DCRO comprising a plurality of stages in a cyclic order, a first stage of the plurality of stages comprising a plurality of inverter modules controlled by the control signal and comprising a plurality of outputs that drive inputs of a plurality of second stages in the plurality of stages; a decoder to decode a phase of the DCRO based on a plurality of sampled phases of the plurality of stages of the DCRO; and a phase error estimator to estimate a phase error based on the phase of the DCRO and a frequency control word, the control signal is based on the phase error.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 17, 2020
    Assignee: INTEL IP CORPORATION
    Inventors: Ashoke Ravi, Rotem Banin, Ofir Degani, David Ben-Haim, Yigal Kalmanovich
  • Patent number: 10833684
    Abstract: A phase locked loop (PLL) includes: a phase frequency detector configured to: generate one or more comparison signals indicating whether a reference input signal is leading a feedback signal or whether the feedback signal is leading the reference input signal; a charge pump coupled to the phase frequency detector and configured to convert the one or more comparison signals into a driving current; a loop filter coupled to the charge pump and configured to split the driving current to generate a first voltage signal and a second voltage signal; and a voltage controlled oscillator coupled to the loop filter and configured to: receive the first voltage signal and generate a first control current; receive the second voltage signal and generate a second control current; and combine the first and second control currents to jointly drive a charge controlled oscillator such that the output signal of a desired frequency is generated.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: November 10, 2020
    Assignee: Analog Bits Inc.
    Inventors: Raghunand Bhagwan, Alan C. Rogers
  • Patent number: 10797713
    Abstract: A method comprises: using a plurality of gain stages cascaded in a ring topology to form a ring oscillator configured to output an oscillation signal; controlling a supply voltage of said ring oscillator using a low-speed DAC (digital-to-analog converter) in accordance with a coarse control word; providing a capacitive load at an inter-stage node of said ring oscillator using a varactor array controlled by a control voltage array; establishing said control voltage array using a high-speed DAC array in accordance with a fine control word; adjusting the coarse control word upon a start-up to make an oscillation frequency of said oscillation signal approximately equal to target value; and adjusting the fine control word in a closed loop manner in accordance with a detection of a timing error of said oscillation signal.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: October 6, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Sriram Venkatesan, Chia-Liang (Leon) Lin
  • Patent number: 10785086
    Abstract: A method of demodulating a signal that is phase modulated to convey R chips having phase transitions between adjacent ones of the R chips to represent chip states, and an overlay symbol spanning the R chips, wherein R>1, and wherein the phase transitions are rotated in a same direction according to an overlay symbol state, comprises: first processing the signal including: accumulating a respective phase of each chip into a respective first chip magnitude, to produce R first chip magnitudes; and accumulating the R first chip magnitudes to produce a first magnitude; second processing the signal including: accumulating a respective phase of each chip into a respective second chip magnitude, to produce R second chip magnitudes; and accumulating the R second chip magnitudes to produce a second magnitude; and determining the overlay symbol state based on the first magnitude and the second magnitude.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: September 22, 2020
    Assignee: Eagle Technology, LLC
    Inventor: Philip Smith Kossin
  • Patent number: 10771234
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may receive an otw signal that is associated with low-path pass information and transmission data. The apparatus may apply a cost function and an update function to the otw signal prior to sending the otw signal to an oscillator. The apparatus may determine a correction factor for use in estimating a gain of the oscillator based at least in part on an output of the update function.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: September 8, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Emanuele Lopelli, Magnus Olov Wiklund, Charles Chang-I Wang, Salvatore Pennisi, Richard McConnell
  • Patent number: 10771012
    Abstract: An oscillator includes a tunable oscillator, a phase detector circuit communicatively coupled with an output of the tunable oscillator and an input to the oscillator, and an oscillator controller circuit configured to adjust frequency of the tunable oscillator based upon phase detection between output of the tunable oscillator and output of an external resonant element received at the input to the oscillator.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: September 8, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Jason Sachs
  • Patent number: 10756740
    Abstract: Disclosed is a voltage-controlled oscillator (VCO) capable of providing an effective high VCO gain against slow change of an input voltage caused by the variation of manufacturing processes, temperature, voltage, etc. and providing an effective low VCO gain against rapid change of the input voltage for reducing jitter. The VCO includes: an input circuit generating an input current according to an input voltage; a first current supply circuit generating a first output current according to the input current; a second current supply circuit generating a second output current according to the input current; a filter coupled to the input circuit and the second current supply circuit and configured to slow down the influence caused by the variation of the input current on the second current supply circuit; and an oscillating circuit generating an output clock according to the first output current and the second output current.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: August 25, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Sung-Lin Tsai, Kuo-Wei Wu, Jian-Ru Lin
  • Patent number: 10700688
    Abstract: Described is a low power and low jitter phase locked loop (PLL) or delay locked loop (DLL) with digital leakage compensation. The compensation is provided by an apparatus which comprises: a circuitry to generate a pulse with a digitally controlled pulse width, wherein the pulse width is proportional to a static phase error of a PLL or a DLL; and a charge pump coupled to the circuitry, wherein the charge pump is to receive the pulse and to source or sink current to or from a node according to the pulse width.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Yongping Fan, Dan Zhang, Bo Xiang
  • Patent number: 10686451
    Abstract: Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 16, 2020
    Assignee: Apple Inc.
    Inventors: Yair Dgani, Michael Kerner, Elan Banin, Nati Dinur, Gil Horovitz, Rotem Banin
  • Patent number: 10677610
    Abstract: A circuit device includes a driving circuit that generates a clock signal by oscillating a vibrator, a master clock signal generation circuit that generates a master clock signal, and a master clock signal failure detection circuit that detects a failure of the master clock signal. The master clock signal failure detection circuit detects the failure of the master clock signal on the basis of an error detection clock signal, which is the clock signal from the driving circuit, and the master clock signal.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: June 9, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kiminori Nakajima, Katsuhiko Maki