Abstract: A power converter includes a ramp generating unit, a first comparator, a second comparator, and a pulse width modulation (PWM) signal generating unit. The ramp generating unit provides a ramp signal. The first comparator receives the ramp signal and a control signal to provide a normal operation control signal. The second comparator receives the ramp signal and the control signal to provide a dynamic response control signal. The PWM signal generating unit generates a PWM signal according to the normal operation control signal or dynamic response control signal. When the control signal is higher than a threshold of ramp signal, the second comparator provides the dynamic response control signal to the PWM signal generating unit to control it to adjust a duty cycle of the PWM signal.

Abstract: A transmitting device, a receiving device, an optical communication system, and associated methods are provided. The transmitting device transmits an optical signal containing data, and comprises: an optical tone generator for generating at least one optical tone; at least one encoder for performing advanced coding on at least one data signal respectively, each of the at least one data signal carrying a part of the data; at least one mapper for performing high order modulation on the at least one coded data signal; and an up-converter for up-converting the at least one high-order-modulated data signal into the optical signal to be outputted through the at least optical tone. Thereby, high speed (e.g., over 1-Tb/s) transmission per single channel over a long-haul distance (e.g. over 1000-km) with error-free recovery may be achieved.

Abstract: The present invention provides a noncontact interface technique capable of performing communication operation without stopping an internal operation even when a clock signal cannot be extracted from a carrier wave. In a semiconductor device that receives a modulated carrier wave from an antenna, generates an internal clock signal on the basis of a clock signal extracted from the received carrier wave, and performs operation synchronously with the internal clock signal, a PLL circuit that receives the extracted clock signal and generates the internal clock signal is provided with a voltage control oscillation function. In the case where the clock signal extracted from the carrier wave is discretely interrupted, the function makes the internal clock signal maintained at a frequency immediately before the interruption. With the configuration, even when the clock signal extracted from the carrier wave is interrupted, internal data processes such as decoding and bus interfacing can be continued.

Abstract: A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. The phase locked loop may enable usage of both rising and falling edges of the crystal clock signal, based on the generated reference clock signal. The phase locked loop may perform an operation of the phase locked loop based on the enabling. The phase locked loop may perform a phase comparison function, based on both rising and falling edges of the crystal clock signal. By utilizing a sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of a charge pump in the phase locked loop, disturbance which is associated with duty cycle errors of the crystal clock signal.

Abstract: The present disclosure relates to a FinFET varactor circuit having one or more control elements that control a relationship between capacitance and voltage of a FinFET MOS varactor without introducing changes to process parameters used in fabrication of the FinFET MOS varactor. In some embodiments, the FinFET varactor circuit has a FinFET MOS varactor with a first terminal connected to a gate terminal of the FinFET MOS varactor and a second terminal connected to connected source and drain terminals of the FinFET MOS varactor. One or more control elements are connected to the first or second terminals of the FinFET MOS varactor and vary one or more operating characteristics of the FinFET MOS varactor. Using the control elements to vary the operating characteristics of the FinFET MOS varactor, allows for the characteristics to be adjusted without making changes to process parameters used in the fabrication of the FinFET MOS varactor.

Abstract: A delay circuit provides a quadrature-delayed strobe, a tightly controlled quadrature DLL and write/read leveling delay lines by using the same physical delay line pair. By multiplexing different usage models, the need for multiple delay lines is significantly reduced to only two delay lines per byte. As a result, the delay circuit provides substantial saving in terms of layout area and power.

Abstract: A system has at least a first circuit portion and a second circuit portion. The first circuit portion is operated at normal AC frequency. The second circuit portion is operated in a back-up mode at low AC frequency, such that the second circuit portion can rapidly come-online but has limited temperature bias instability degradation. The second circuit portion can then be brought on-line and operated at the normal AC frequency. A system including first and second circuit portions and a control unit, as well as a computer program product, are also provided.

Abstract: A receiver in an integrated circuit device is described. The circuit comprises a receiver having a clock and data recovery circuit coupled to receive data signals modulated with a transmitter clock signal; and a clock generator coupled to receive an output of the clock and data recovery circuit, the clock generator providing a modulated reference clock to the receiver, based upon a reference clock signal which is independent of the transmitter clock signal; wherein the modulated reference clock provided to the receiver is synchronized with the transmitter clock signal. A method of receiving data in an integrated circuit is also described.

Abstract: The inventive concept relates to a supply regulated voltage controlled oscillator having a function of an active loop filter by sharing one operational amplifier without additional use of active elements in a supply regulated voltage controlled oscillator using an operational amplifier as a supply regulator, and a phase locked loop using the same.

Abstract: A circuit includes a first oscillator and a second oscillator. The first oscillator includes an inductive device, a capacitive device, and an active feedback device configured to output a first output signal having a predetermined frequency according to electrical characteristics of the inductive device of the first oscillator and electrical characteristics of the capacitive device of the first oscillator. The second oscillator includes an inductive device, a capacitive device, and an active feedback device configured to output a second output signal having the predetermined frequency according to electrical characteristics of the inductive device of the second oscillator and electrical characteristics of the capacitive device of the second oscillator. The inductive device of the first oscillator and the inductive device of the second oscillator are magnetically coupled.

Abstract: Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof.

Abstract: A system is disclosed for a voltage controlled oscillator (“VCO”) having a large frequency range and a low gain. Passive or active circuitry is introduced between at least one VCO cell in the voltage controlled oscillator and the voltage source for the VCO cell which reduces a gain value for the VCO to maintain stability of the system.

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus tunes a frequency provided by a VCO. The apparatus determines a relative capacitance change associated with a first frequency and a desired frequency from a look-up table. The apparatus adjusts a capacitor circuit in the VCO based on the determined relative capacitance change determined from the look-up table in order to tune from the first frequency to the desired frequency. The apparatus determines that the frequency provided by the VCO is a second frequency different than the desired frequency after adjusting the capacitor circuit. The apparatus performs an iterative search to further adjust the capacitor circuit when a difference between the second frequency and the desired frequency is greater than a threshold.

Abstract: There are provided an accumulator-type fractional N-PLL synthesizer for suppressing the fractional spurious caused by periodically switching a frequency division number of a fractional frequency divider, and a control method thereof. In an accumulator-type fractional N-PLL synthesizer (100), a pulse signal proportional to a fractional phase error occurring between a reference signal and an output signal of a fractional divider (112) for feeding back an output of a VCO (115) of an output stage to a preceding stage is generated using an error signal from an accumulator (120). Through the use of the pulse signal, pulse widths of a UP signal and a DN signal output from a phase detector (140) are controlled so as to reduce a fractional phase error occurring between the UP signal and the DN signal. Thus, the fractional spurious caused by periodically switching the frequency division number of the fractional divider (112) is suppressed.

Abstract: A digitally controlled oscillator has a high-order ?? modulator configured to be of at least an order higher than a first order and configured to input a digital control signal and output a pseudorandom digital output signal, a first-order ?? modulator configured to input the pseudorandom digital output signal and generate a control pulse signal including a pulse width corresponding to the pseudorandom digital output signal, a low pass filter configured to pass a low frequency component of the control pulse signal, and an oscillator configured to generate a high-frequency output signal whose frequency is controlled based on the control pulse signal outputted by the low pass filter so as to be a frequency corresponding to the digital control signal.

Abstract: A process, voltage, and temperature compensated oscillator, formed on an integrate circuit implemented by a semiconductor process, receives a supply voltage and includes: a variation bias unit provided with a variation bias output terminal and generating a process, voltage, and temperature compensated signal; a controlled oscillating unit provided with a control input terminal and an oscillating output and determining a signal oscillating frequency at the oscillating output terminal according to a signal at the control input terminal; and a tuning unit provided with a tuning input terminal, a compensating input terminal, a control output terminal, and a variable-parameter element, wherein the variable-parameter element includes a parameter and is coupled to the control output terminal, and the tuning unit determines the parameter according to a signal at the variation bias output terminal and a voltage signal or a digital signal received at the tuning input terminal.

Abstract: According to one embodiment, a first oscillator has an oscillation frequency that is changed depending on a temperature. A second oscillator has different temperature characteristics from the first oscillator. An on-chip heater heats the first oscillator and the second oscillator. A counter counts a first oscillation signal of the first oscillator. An ADPLL generates a third oscillation signal on the basis of a second oscillation signal of the second oscillator and corrects the frequency of the third oscillation signal on the basis of a count value of the counter.

Abstract: A method and a phase locked loop (PLL) circuit for implementing compact current mode logic inductor capacitor voltage controlled oscillator for high speed communications, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a current mode logic (CML) inductor capacitor (LC) Voltage Controlled Oscillator (VCO). The PLL circuit includes a reference circuit generates a virtual ground node for biasing noise sensitive components, providing level shifted VCO increment and decrement tuning values from a phase detector coupled by a respective resistor to tune a varactor of the LC VCO, and providing a loop filter function. The virtual ground node tracks a logic power supply noise, incurring no jitter penalty, and eliminating the need for a separate power supply for the PLL circuit.

Abstract: A system includes first circuitry including first elements for operating in a low power mode; second circuitry including second elements for operating in a high-temperature mode; and one or more switching elements for selecting between the low power mode and the high temperature mode.

Abstract: In an embodiment of the invention, a frequency divider in a phase-locked loop (PLL) circuit is provided power from the power supply that provides power to a transmission circuit. The PLL is configured to receive a first direct current (DC) reference voltage, a second DC voltage and a reference clock signal. The PLL is configured to generate a transmission clock signal. A transmission circuit is configured to receive the transmission clock signal, the second DC voltage and a data bus where the data bus includes a plurality of data bits in parallel. The transmission circuit transmits data serially.

Abstract: There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (20), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.

Abstract: A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal.

Abstract: A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock.

Abstract: A circuit generates a compensation signal that can remove noise in a VCO introduced by a supply signal (i.e., supply-side noise). The circuit includes two transistors connected in series. A resistor is connected between the gate of the first transistor and the supply signal, and a capacitor is connected between the gate of the second transistor and the supply signal. The circuit is designed so that the transconductance of one transistor is greater than or equal to twice the transconductance of a second transistor. The compensation signal is supplied through a capacitor, which compensates for capacitors in a VCO, to an internal supply node of the VCO. At the internal supply node, the compensation signal removes (or greatly reduces) the noise introduced by the supply signal noise, resulting in a less-noisy output signal from the VCO.

Abstract: A phase locked loop system, comprises: a voltage controlled oscillator circuit, comprising a first plurality of switchable varactors for selecting a frequency band of the VCO, that has a gain that changes with frequency band, and a second plurality of switchable varactors for varying the gain in the selected band. The PLL system has a PLL feedback circuit comprising a switching device for switching the feedback circuit to an open loop state wherein a plurality of predefined tuning voltages can be applied to the VCO; a frequency measurement device for measuring the synthesized VCO frequency; and a control unit operable to determine the gain with respect to the synthesized frequency and the tuning voltages.

Abstract: A digitally-controlled oscillator circuit receives a digital value and generates a driving signal for driving an oscillator at a frequency according to the received digital value. A time-to-digital converter circuit receives a detection signal of oscillation of the oscillator, receives the driving signal, and detects a phase difference between the detection signal and the driving signal. A control circuit receives the detected phase difference and controls the frequency of the driving signal generated by the digitally-controlled oscillator circuit, such that the detected phase difference coincides with a predetermined resonant phase difference to resonate the oscillator.

Abstract: A circuit may include a digitally-controlled oscillator including a coarse frequency-tuning array with a multiple selectable coarse frequency-tuning segments. Each of the coarse frequency-tuning segments may have a coarse segment frequency step size. The digitally-controlled oscillator may also include a fine frequency-tuning array with multiple selectable fine frequency-tuning segments. The fine frequency-tuning array may have a fine array frequency step size that is at least twice the coarse segment frequency step size. The digitally-controlled oscillator may be configured to generate an output signal with a frequency based on the coarse frequency-tuning array and the fine frequency-tuning array.

Abstract: A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur.

Abstract: A digital phase-locked loop (PLL) device includes a digital loop filter which is provided with both a VCO-loop output and a DCO-loop output. The VCO-loop output is connected to an analog input of a multiband voltage-controlled oscillator (VCO) module for allowing usual operation of the PLL with a direct voltage acting as feedback parameter. The DCO-loop output is connected to a digital control input of the multiband VCO module for allowing automatic frequency range selection. A code value which is produced by the digital loop filter acts as feedback parameter during the frequency range selection. Rapid and precise range selection can thus be performed.

Abstract: One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.

Abstract: A signal generator for a transmitter or a receiver for transmitting or receiving RF-signals according to a given communication protocol includes an oscillator and a mismatch compensator. The oscillator is configured to provide a signal generator output signal having a signal generator output frequency and comprises a fine tuning circuit for providing a fine adjustment of the signal generator output frequency based on a fine tuning signal and a coarse tuning circuit for providing a course adjustment of the signal generator output frequency based on a coarse tuning signal.

Abstract: A method for tuning a digital compensation filter within a transmitter includes: obtaining at least one resistance-capacitance (RC) detection result, wherein the digital compensation filter includes an RC compensation module; and tuning the digital compensation filter by inputting the RC detection result into the RC compensation module. For example, the RC detection result may correspond to a detected value representing a product of a resistance value and a capacitance value. In another example, the at least one RC detection result may be obtained by performing RC detection on at least a portion of the transmitter without individually measuring resistance values of resistors therein and capacitance values of capacitors therein. An associated digital compensation filter and an associated calibration circuit are also provided.

Abstract: A frequency synthesizer for a WLAN transceiver is disclosed that may be used to generate 5.4 GHz and 2.4 GHz signals. The frequency synthesizer may be configured to minimize VCO pulling by using VCO operating frequencies that are not integer multiples of the RF bands. Further, the frequency synthesizer may be configured to minimize interference with other frequency bands used by existing wireless systems.

Abstract: A frequency synthesis device with a feedback loop includes: a phase-comparison control circuit; a frequency conversion unit voltage controlled by the control circuit; a feedback loop for supplying at least one signal issuing from the frequency conversion unit to the control circuit; at least one other control circuit for voltage control of the frequency conversion unit; and at least one other feedback loop for supplying at least one other signal issuing from the frequency conversion unit to the other control circuit.

Abstract: A system and method in accordance with the present invention provides a gyroscope incorporating an improved PLL technique. The improved PLL auto-corrects its own reference low-frequency noise, thereby eliminating this source of noise, improving the noise performance of the gyroscope and allowing a compact implementation. The net result is a gyroscope with improved bias stability that can meet noise requirements with a smaller footprint.

Abstract: A phase-locked loop double-point modulator may include a frequency divider having a ratio which can be changed by a first modulation signal, and an oscillator, a frequency of which can be changed by a second modulation signal correlated to the first modulation signal. A calibration circuit may be configured, in a calibration mode, to match the gains of the first and second modulation signals based on frequency measurements of the oscillator for two different calibration values of the second modulation signal. The phase-locked double-point modulator may also include an attenuator having a constant ratio greater than 1 and placed in the path of the second modulation signal, and a selector switch configured to be controlled by the calibration circuit to reduce the ratio of the attenuator in the calibration mode.

Abstract: A phase shift phase locked loop (PSPLL) are described. The phase shift PLL includes a PLL and a phase adjusting circuit coupled to the inputs of the PLL. The phase adjusting circuit has a first input, a first output, a second input, a third input, and a second output. The first output and the second output are coupled to a first input and a second input of the PLL, respectively. The second input of the phase adjusting circuit receives a feedback signal and the third input of the phase adjusting circuit receives a control signal. The phase adjusting circuit receives a reference signal and sends a first output signal and a second output signal based on the reference signal to the PLL to adjust a phase of an output signal of the PLL in an increment less than a time period of the output signal of the PLL.

Abstract: A frequency divider of an injection locked type capable of division by 2, division by 4, and further division by 8 with a simpler configuration is disclosed and the frequency divider includes a ring oscillator including M (M is an even number) delay elements, the tails of two delay elements M/2 delay elements apart from each other are connected to a differential pair and transistors, to the gates of which the input oscillation signal is applied, are connected to the differential pair, and the differential pair is caused to generate a differential signal of the input oscillation signal, which is a divide-by-2 signal of the input oscillation signal, and when dividing the frequency of the input oscillation signal by 8, the portion of the differential pair to be connected to the tail of the delay element is caused to have a two-stage configuration, which is a vertically stacked configuration.

Abstract: An oscillator configured to obtain a frequency output corresponding to a frequency setting value includes: an oscillation circuit portion that receives the frequency setting value; a setting value output portion that outputs a digital value for designating the frequency setting value; an interpolation circuit portion that performs interpolation for a digital value of lower-order bits out of the digital value output from the setting value output portion; and an adder that adds an output of the interpolation circuit portion and a digital value of higher-order bits out of the digital value output from the setting value output portion, wherein a signal output from the interpolation circuit portion is sequential data having first and second values different from each other, and output counts of the first and second values are determined based on a ratio corresponding to the digital value of the lower-order bits.

Abstract: Aspects of the embodiments include a method for synchronizing a device having an oscillator to a reference signal. A correction signal can be determined based on the reference signal. A mathematical model of the oscillator can be trained based at least upon the correction signal. A predicted correction signal for the trained mathematical model can be determined. A time error using the predicted correction signal can be generated to assess suitability of the trained mathematical model for disciplining drift in the oscillator and synchronizing the device when the reference signal is not available.

Abstract: A circuit arrangement for generation of radio frequency output signals which form a broadband frequency ramp, with a reference oscillator, a phase detector, a loop filter, a VC oscillator for generating the output signals, a frequency divider, a step-down mixer and a local oscillator for generating a local oscillator signal. The reference oscillator, the phase detector, the loop filter, the VC oscillator, the frequency divider and the step-down mixer belong to a phase-locking loop. The frequency divider and the step-down mixer are in the feedback path of the phase-locking loop. The step-down mixer mixes the output signals and the local oscillator signal. The frequency of the output signal is adjustable by varying the division ratio of the frequency divider. Characteristics of the output signal are improved using the adjustable frequency of the local oscillator signal.

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus generates LO signals. The apparatus includes a LO generator module and an injection signal generator module coupled together. The LO generator module has a plurality of LO outputs and a plurality of injection signal inputs. The LO module is configured to generate the LO signals on the LO outputs based on injection signals received on the injection signal inputs. The injection signal generator module has a plurality of LO inputs and a plurality of injection signal outputs. The LO inputs are coupled to the LO outputs. The injection signal outputs are coupled to the injection signal inputs. The injection signal generator module is configured to generate injection signals on the injection signal outputs based on the LO signals received on the LO inputs and based on a received VCO signal.

Abstract: A digital frequency synthesizer with an automatic calibration system. The digital frequency synthesizer is calibrated by initiating a coarse tuning operation to rapidly reach a preliminary frequency that is proximate to the desired final frequency. A calibration procedure is then executed for adjusting gain in the frequency synthesizer based on the preliminary frequency. This test involves applying one or more test signals to the frequency synthesizer and measuring a signal generated in the frequency synthesizer. This measured signal corresponds to a gain response of the circuit at the preliminary frequency. When the expected gain is known, any difference relative to the gain of the measured signal is used to adjust the gain in a circuit of the frequency synthesizer such that the actual gain substantially matches the expected gain.

Abstract: Methods and systems for processing a signal with a corresponding noise profile are disclosed. Aspects of the method may comprise analyzing spectral content of the noise profile. At least one noise harmonic within the signal may be filtered based on said analyzed spectral content. The filtered signal may be amplified. The noise profile may comprise a phase noise profile. The signal may comprise at least one of a sinusoidal signal and a noise signal. At least one filter coefficient that is used to filter the at least one noise harmonic may be determined. The filtering may comprise low pass filtering. The signal may be modulated prior to filtering. The amplifying may comprise buffering. A non-linearity characteristic of the signal may be determined and a noise harmonic may be low-pass filtered within the signal based on the determined non-linearity characteristic.

Abstract: A new all digital PLL (ADPLL) circuit and architecture and the corresponding method of implementation are provided. The ADPLL processes an integer and a fractional part of the phase signal separately, and achieves power reduction by disabling circuitry along the integer processing path of the circuit when the ADPLL loop is in a locked state. The integer processing path is automatically enabled when the loop is not in lock. Additional power savings is achieved by running the ADPLL on the lower-frequency master system clock, which also has the effect of reducing spur levels on the signals.

Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.

Abstract: An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values.

Abstract: An oscillator auto-trimming method is provided. The oscillator auto-trimming method includes receiving, by a subtractor, a first count result and second count result to output a difference between the first count result and the second count result as an offset frequency, receiving, by a divider, the offset frequency to output a divided signal corresponding to a result of dividing the offset frequency by a reference offset frequency output from a micro control unit, and receiving, by the micro control unit, the divided signal and determine whether to change an oscillator frequency.

Abstract: In a circuit having a runaway detector coupled to a phase-locked loop (PLL), the PLL may include a loop filter to receive a control voltage within the PLL and provide a filtered control voltage and a voltage-controlled oscillator to receive the filtered control voltage and provide an output clock signal. The runaway detector may provide a control signal for adjusting the filtered control voltage in response to a predetermined PLL condition. The runaway detector may include a comparator to receive a first and second input voltages, where the second input voltage is based on the output clock signal. When the predetermined PLL condition exists, the runaway detector may be active to adjust the filtered control voltage, thereby enabling the PLL to return to a lock condition.

Abstract: A Direct VCO (DCO) modulation apparatus and method that provides a wideband modulated signal output. The wideband response is obtained via signal processing to counteract a high-pass frequency characteristic as seen from the VCO modulation input. That is, low frequency components of data signals are compensated before being applied to a VCO input. The high-pass characteristic in combination with the compensated signal provides a relatively flat, wideband frequency response of the DCO modulator.