Abstract: A bandwidth adjusting method for a phase-locked loop (PLL) unit of a phase recovery module includes: adjusting an operating bandwidth of the PLL unit to a first bandwidth; measuring multiple first phase errors between a compensated input signal, which is generated according to an input signal and a phase compensating signal that the PLL unit generates, and a reference clock signal, and obtaining a first statistical value of the first phase errors; adjusting the operating bandwidth of the PLL unit to a second bandwidth; measuring multiple second phase differences between the compensated input signal and the reference clock signal, and obtaining a second statistical value of the second phase differences; and adjusting the operating bandwidth according to the first statistical value and the second statistical value. The first bandwidth and the second bandwidth are obtained by interpolating an upper bandwidth limit and a lower bandwidth limit.

Abstract: Circuits and methods for identifying or verifying frequencies are disclosed herein. A frequency verification circuit comprises: an input port for receiving an input signal; a phase frequency difference detector for determining a difference in phase and frequency between the input signal and a feedback signal and for providing a control signal based on the detected difference; a voltage controlled crystal oscillator for producing an output signal based on the control signal; and a feedback loop including a feedback divider for frequency dividing the output signal by a factor R to produce the feedback signal, the feedback divider being programmable to a plurality of values of the factor R to correspond to a plurality of different test frequencies.

Abstract: A voltage-controlled oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors, coupled between a supply voltage and the two output terminals, two N-type transistors coupled between a ground voltage and the two output terminals, and a control circuit. The control circuit is coupled to the inductor, and is arranged to control a current flowing through the two P-type transistors and the inductor by controlling a voltage of the inductor.

Abstract: In accordance with an embodiment, a method includes driving at least one electronic switch coupled to at least one inductor in a converter stage of a switched mode power supply based on a clock signal, and modulating a clock frequency of the clock signal over a predefined first frequency range around a center frequency such that a frequency spectrum of the clock signal is asymmetric. The switched mode power supply includes a filter coupled between the converter stage and an input of the switched mode power supply.

Abstract: An integrated clock generator includes a tunable LC oscillator, a tunable frequency synthesizer, and a processor. The tunable LC oscillator has an input for receiving an oscillator control signal, and an output for providing an oscillator clock signal. The tunable frequency synthesizer has a clock input coupled to the output of the tunable LC oscillator, a control input for receiving a synthesizer control signal, and an output for providing a clock output signal. The processor has an input for receiving a data input signal, a first output for providing the oscillator control signal, and a second output for providing the synthesizer control signal. The processor provides the oscillator control signal and the synthesizer control signal such that the tunable frequency synthesizer generates the output clock signal at a frequency indicated by the data input signal, and provides the synthesizer control signal further in response to a dynamic condition.

Abstract: The method for calibrating the frequency synthesizer using two-point FSK modulation consists, in a first phase, in supplying an excitation signal generated by a calibration unit to a sigma-delta modulator by deactivating a digital-to-analog converter and transmitting the output signal from a loop filter of the synthesizer to the calibration unit, which digitally converts the incoming signal and offsets the phase shift between the excitation signal and the loop filter output signal in the calibration unit. In a second phase, the excitation signal is supplied to the sigma-delta modulator and to the activated digital-to-analog converter, and the digital-to-analog converter gain is calibrated by checking, in the calibration unit, the polarity of the loop filter output signal with respect to the excitation signal, and using a dichotomy algorithm.

Abstract: A voltage controlled oscillator (VCO) is disclosed. The VCO includes an amplifier that receives a control signal and a feedback signal and generates an amplified output signal based on the difference between the control signal and the feedback signal. The VCO also includes circuitry to generate an oscillating output signal based on the amplifier output signal. Additionally, the VCO includes a feedback amplifier that generates the feedback signal based on the output of the amplifier. The feedback amplifier includes a first resistor connected in parallel with a second resistor, the second resistor having an adjustable resistance.

Abstract: Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.

Abstract: A phase locked loop, comprising: a phase detector configured to determine a phase difference (??) between a reference signal and a feedback signal; a loop filter configured to perform a filtering operation on a signal derived from the phase difference, and to provide a control signal; a frequency controlled oscillator configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal; wherein a low-pass filter is provided between the phase detector and the loop filter and/or between the loop filter and the frequency controlled oscillator to reduce quantization noise from the phase detector.

Abstract: A technique for cancelling or reducing crosstalk signals between controlled oscillators in an integrated circuit is provided. The technique involves an arrangement adapted to reduce a crosstalk signal generated by a first controlled oscillator to a second oscillator both comprised in the integrated circuit, wherein both controlled oscillators are configured to output a respective clock signal. The arrangement comprises a detector adapted to detect the crosstalk signal generated by the first controlled oscillator to the second controlled oscillator, a crosstalk cancellation circuit adapted to generate a cancellation signal having an amplitude substantially the same as that of the crosstalk signal and a phase substantially opposite to that of the crosstalk signal, and a cancellation signal injector adapted to introduce the cancellation signal into the second controlled oscillator.

Abstract: An oscillator comprising a support substrate, at least one transducer mounted on a first surface of the support substrate, and an integrated circuit element mounted on a second surface of the support substrate. The integrated circuit element includes first and second frequency generating components integrated therein. The first frequency generating component generates a first output frequency, and the second frequency generating component generates a second output frequency that is higher than the first output frequency. The oscillator also includes a ground terminal to which the second frequency generating component is closer than the first frequency generating component.

Abstract: The present disclosure is directed towards systems and method for actively tuning a phase locked loop based on vibration excitation levels experienced by the phase locked loop. A bandwidth of the phase locked loop can be actively increased or decreased based upon a detected vibration level. In an embodiment, the phase locked loop includes a controllable oscillator, an output module, a filter module and a detector. The filter module can be configured to receive a bandwidth control signal to modify a bandwidth of the phase locked loop based on a vibration signal. In an embodiment, the vibration signal corresponds to a vibration level experienced by the phased locked loop. The detector can be configured to receive a PLL output signal from the output module and to receive a PLL input signal.

Abstract: A locked loop circuit includes a controlled oscillator generate an output signal having a frequency set by an analog control signal. The analog control signal is generated by a first digital-to-analog converter (DAC) in response to a digital control signal and a bias compensation current signal. The bias compensation current signal is generated by a second DAC in response to a compensation control signal and a bias reference current. A compensation circuit adjusts the compensation control signal during compensation mode in response to a comparison of a frequency of the output signal to a frequency of a reference signal so as to drive the frequency of the output signal toward matching a desired frequency. The bias compensation current signal associated with the frequency match condition during compensation mode is then used during locked loop mode.

Abstract: An apparatus of a mobile device may calibrate RF circuitry for mobile communications. The apparatus may include phase locked loop (PLL) comprising a digital controlled oscillator (DCO) and one or more processors coupled to the PLL. The one or more processors may determine a coarse tuning setting for the DCO based on a target frequency of a wireless channel; and calculate, a DCO gain value for the coarse tuning setting based on a calibration DCO gain value for a calibration coarse tuning setting.

Abstract: A method includes generating a calibration signal by a clock generator, feeding the calibration signal to a first filter through a first switch unit, comparing an output of the first filter with the calibration signal through a frequency detector and a phase comparator and generating a first updated bandwidth code to adjust a bandwidth frequency of the first filter.

Abstract: A phase-locked loop. The phase-locked loop includes a voltage-controlled oscillator having: a control input, and a clock output; and a phase frequency detector having: a reference clock input, a feedback clock input, an up output configured to be either in a set state or a reset state, and a down output configured to be either in a set state or a reset state. The up output and the down output are connected to the control input. The clock output is connected to the feedback clock input. The phase frequency detector includes an adjustable delay block configured to delay, by an adjustable delay time: a transition of the up output from the set state to the reset state, and a transition of the down output from the set state to the reset state.

Abstract: A method for a near field communication circuit includes entering a low power mode and subsequently determining to exit the low power mode. The method further includes generating an open loop clock signal and providing the open loop clock signal to circuits of the near field communication circuit during a low power mode exit duration. Subsequently a reference clock signal is received from a host and used to clock the near field communication circuit.

Abstract: Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.

Abstract: A multi-waveband OFDM receiver and a frequency offset compensation method and system are disclosed. The method includes: performing single waveband frequency offset estimation on an optical comb line of each order; classifying the optical comb lines into a low mutation optical comb line and a high mutation optical comb line; performing joint frequency offset estimation on the low mutation optical comb line; and performing compensation for a frequency offset of a radio frequency drive signal by using an estimated joint frequency offset. The present invention improves accuracy and reliability of the frequency offset estimation of the radio frequency drive signal, so that the degree of the compensation for the frequency offset of the radio frequency drive signal is more comprehensive and accurate.

Abstract: An RF circuit and method for detecting the amount of phase shift applied to an RF signal. An RF heating apparatus including the RF circuit. The RF circuit includes a phase shifter operable to apply a phase shift to a reference signal to produce a phase shifted reference signal. The RF circuit also includes a phase detector operable to detect a phase difference between the phase shifted RF signal and the phase shifted reference signal. The phase detector has a reduced input range at a frequency of the phase shifted RF signal. The RF circuit further includes a controller operable to control the phase shifter to set the phase of the phase shifted reference signal so that the phase difference between the phase shifted RF signal and the phase shifted reference signal falls within the reduced input range of the phase detector.

Abstract: A system and method for calibrating a Voltage-Controlled Oscillator (VCO) having both fine-tuning control and coarse-tuning control. The VCO frequency can vary monotonically with changes in each of one or more operational conditions. The calibration method determines the coarse-tuning control setting for the VCO at system start-up. The method comprises generating frequency characterization data, generating a polynomial function from the characterization data, calculating the fine-tuning control voltage based on the polynomial function and a measurement of the operational conditions, and sweeping through all the coarse-tuning control settings to determine the coarse-tuning control setting that generates the closest VCO frequency to a target frequency when using the calculated fine-tuning control voltage.

Abstract: Techniques for correcting clock distortion. The techniques include use of circuitry for detecting and correcting duty cycle distortion and quadrature clock phase distortion. For phase detection, detection circuitry is made simpler and more accurate through the use of a sampling operation in which device mismatch within detection circuitry is accounted for by sampling charge associated with an ideal clock signal across sampling capacitors. When phase detection is performed with the detection circuitry, the stored charge compensates for the device mismatch, improving the accuracy of the detection circuit. The sampling operation is used for duty cycle distortion detection as well. Specifically, a common mode voltage is applied to sampling capacitors, which effectively zeroes the voltage differential between the sampling capacitors, compensating for offset that might exist due to operation of other components of the detection circuit.

Abstract: Techniques and systems for facilitating the calibration of oscillation frequencies for an analog audio synthesizer are disclosed. Included are embodiments for performing the initial calibration of an audio synthesizer and for continuously compensating for the frequency irregularities which originate from insufficient calibration and/or frequency drift of the oscillator circuits. Embodiments can utilize the microcontroller already present in most synthesizers and require no further hardware.

Abstract: An analog-to-digital converter (ADC) circuit comprises a digital-to-analog (DAC) circuit including at least N+n weighted circuit components, wherein N and n are positive integers greater than zero, and n is a number of repeat bits of the least significant bit (LSB) of the ADC circuit; a sampling circuit configured to sample an input voltage at an input to the ADC circuit and apply a sampled voltage to the weighted circuit components; a comparator circuit configured to compare an output voltage of the DAC to a specified threshold voltage during a bit trial; and logic circuitry configured to perform bit trials for the at least N+n weighted circuit components and adjust one or more parameters for one or more of N bit trials according to values of the n LSB repeat bits.

Abstract: Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (PLL). Methods include minimizing the mixing gain between the oscillation signal and a power signal provided to the PLL. The oscillation signal and the power signal may be mixed in a phase frequency detector (PFD) included in the PLL. The minimizing of the mixing gain for the PFD also minimizes the degrading effect that the spurs have on the overall performance of the communications device. The mixing gain may be minimized by minimizing the impedance provided at nodes included in the PFD where the oscillation signal and the power signal mix. The mixing gain may also be minimized by maximizing the power supply rejection ratio for the PFD.

Abstract: The problem with duty-cycle correction circuits used by conventional frequency doublers is that they typically analog solutions, such as variable delay lines with long chains of inverters or buffers, that directly adjust the reference signal used by a phase-locked loop (PLL). These solutions can considerably increase the noise (e.g., thermal noise and supply noise) of the reference signal, as well as the overall power consumption and cost of the PLL. Rather than directly correct the duty-cycle of the reference signal, the present disclosure is directed to an apparatus and method for measuring the period error between adjacent cycles of a frequency doubled reference signal in terms of cycles of the output signal generated by the PLL (or some other higher frequency signal) and adjusting the division factor of the PLL frequency divider to compensate for the measured period error.

Abstract: A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. A sampled loop filter (SLPF) in the phase locked loop may capture charge from a charge pump (CHP) in the phase locked loop and the charge is captured at a frequency corresponding to the frequency of the reference clock signal. A switch of the sampled loop filter is utilized and controlled to manage holding and releasing of the captured charge, where the switch is controlled utilizing a control signal. By utilizing the sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of the charge pump, disturbance which is associated with duty cycle errors of the crystal clock signal.

Abstract: This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a digital phase locked loop (DPLL) based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client). An example of this DPLL in conjunction with a recursive least squares mechanism for clock offset and skew estimation is also provided.

Abstract: Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.

Abstract: A method and apparatus for harmonic distortion compensation in power line communications. In one embodiment, the method comprises analyzing a waveform generated by a transmitter of a power line communications transceiver (PLCT), wherein the waveform is analyzed to determine harmonic information for one or more harmonics of a carrier waveform of the PLCT; computing, based on the harmonic information, one or more harmonic compensation coefficients; and pre-distorting, based on the one or more harmonic compensation coefficients, the carrier waveform such that the one or more harmonics are reduced below a threshold.

Abstract: The described devices, systems and methods include a voltage controlled oscillator. The voltage controlled oscillator includes a fine-tuning varactor network, a switch capacitor array having a first plurality of binary capacitor array elements and a second plurality of thermometer code capacitor array elements, and a tank inductor network including a first inductor in parallel with a second inductor.

Abstract: Provided is a ramp signal generating apparatus. The ramp signal generating apparatus includes N (N is a natural number) ramp signal generating cells that are connected in series to each other. Each of the ramp signal generating cells includes a power voltage unit for supplying current source, a latch unit for latching an output voltage of the power voltage unit, and a switch unit for outputting the voltage latched by the latch unit as an output voltage in response to an input signal.

Abstract: A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.

Abstract: An apparatus including: a current source configured to generate current; a switching current source circuit coupled to the current source and a first bias node to allow the current to flow through the switching current source circuit into the first bias node; a first bias circuit configured to receive a first control signal from a phase detector, the first bias circuit configured to mirror the current flowing through the switching current source circuit in response to the first control signal; a second bias circuit coupled to the first bias circuit at an output node and a second bias node, the second bias circuit configured to receive a second control signal from the phase detector; and a transconductance amplifier configured to receive a feedback signal from the output node and generate an output current to control the second biasing node.

Abstract: In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.

Abstract: A semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to detected ambient temperature and operating voltage.

Abstract: A mechanism is provided for implementing an operational parameter change within the data processing system based on an identified degradation. One or more degradations existing in the data processing system are identified based on a set of degradation values obtained from a set of degradation sensors. A determination is made as to whether one or more operational parameters need to be modified based on the one or more identified degradations. Responsive to determining that the one or more operational parameters need to be modified based on the one or more identified degradations, an input change is implemented to a one or more control devices in order that the one or more operational parameters are modified.

Abstract: A switching converter with slope compensation circuit, the slope compensation circuit has a first voltage source, a first operation circuit, a first switch, a first capacitor, a second switch and a first controlled current source.

Abstract: Variable capacitor structures and methods of use are disclosed. The variable capacitor structures include a variable controlled oscillator which includes a variable capacitor structure having at least one capacitor set driven by a control gate voltage of a voltage control circuit which comprises a logic cell that senses a selected frequency band and sets the control gate voltage based on the selected frequency band.

Abstract: An apparatus including: a current source configured to generate current; a switching current source circuit coupled to the current source and a first bias node to allow the current to flow through the switching current source circuit into the first bias node; a first bias circuit configured to receive a first control signal from a phase detector, the first bias circuit configured to mirror the current flowing through the switching current source circuit in response to the first control signal; a second bias circuit coupled to the first bias circuit at an output node and a second bias node, the second bias circuit configured to receive a second control signal from the phase detector; and a transconductance amplifier configured to receive a feedback signal from the output node and generate an output current to control the second biasing node.

Abstract: A variable frequency signal synthesizer includes a phase locked loop including a time-to-digital converter configured to detect differences in phase and frequency between a reference signal and a feedback clock signal and output error signals corresponding to the detected differences, a digital loop filter, a digitally controlled oscillator, and a first frequency divider configured to divide output signals of the digitally controlled oscillator at a predetermined frequency division ratio, a feedback clock generation unit configured to generate sign signals and a phase-modulated feedback clock signal, and a frequency slope tracker configured to generate a frequency control signal by accumulating differences in the error signals according to signs corresponding to the sign signals. The digitally controlled oscillator receives the frequency control signal to supply an output variable frequency signal.

Abstract: Aspects of the disclosure provide a circuit that includes a detector, a loop filter and a controller. The detector is configured to generate a first signal indicative a timing difference between a reference clock signal and a feedback clock signal. The feedback clock signal is generated based on an oscillating signal from an oscillator. The oscillator includes a first tuning circuit and a second tuning circuit to tune a frequency of the oscillating signal. The loop filter is configured to filter out a portion of frequency components from the first signal to generate a second signal for tuning the first tuning circuit of the oscillator. The controller is configured to tune the second tuning circuit based on the first signal and the second signal.

Abstract: The present disclosure provides for a phase-locked loop (PLL) that includes a high-port calibration control module configured to calibrate an input modulation value of a voltage-controlled oscillator (VCO) to a first modulation value that results in an output signal of the VCO having a positive frequency change from an initial output frequency, and capture a positive frequency value of the output signal after a first accumulation time period. The high-port calibration control module is also configured to calibrate the input modulation value of the VCO to a second modulation value that results in the output signal having a negative frequency change from the initial output frequency, capture a negative frequency value of the output signal after a second accumulation time period, and calculate a calibration scale factor based on a difference between the positive and negative frequency values.

Abstract: The time-domain spectroscopy analysis system includes a splitter for splitting pulsed light entered, a variable delayer for delaying timing of a first part of the pulsed light split by the splitter, an electromagnetic wave generator for converting a second part of the pulsed light split by the splitter into an electromagnetic wave, a detector for detecting measurement data from a pulse having passed through a measurement object subjected to the electromagnetic wave emitted from the electromagnetic wave generator, and the pulse outputted from the variable delayer, and a comparator for detecting a phase difference between the pulsed light before being entered into the electromagnetic wave generator and the pulsed light outputted from the variable delayer, wherein a result obtained by the comparator is fed back to the variable delayer.

Abstract: A signal conversion circuit, a PLL circuit, a delay control circuit and a phase control circuit for promoting miniaturization and for reducing quantization noise. TSTC does not require a low-pass filter of capacitor Cm with large layout area conventionally required for converting pulse width to voltage, which promotes miniaturization and cost reduction. TSTC 8 generates analog voltage adequate for transition state at boundary where pulse signal transits, which reduces quantization noise, compared with conventional digital PLL circuits.

Abstract: Systems and methods for compensating for a known interferer to a Controlled Oscillator (CO) of a Phase-Locked Loop (PLL) are disclosed. In one embodiment, a system includes a PLL and a compensation system. The compensation system is configured to generate a compensation signal based on a complex correlation of an output signal of a phase detector of the PLL and a signal derived from a replica of a known interferer to the CO. The compensation system is further configured to apply the compensation signal to the control signal provided by the low-pass filter of the phase-locked loop to thereby provide the compensated control signal for the CO of the phase-locked loop. In this manner, the compensation system mitigates the known interferer at the CO of the PLL.

Abstract: A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a digital control circuit configured to generate a curve select signal using a closed loop curve search operation to select one of the operating curves in the multi-curve VCO, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit implements a binary jump method and an operating curve is selected when the operating curve has an output frequency meeting the target frequency with the control voltage being within a first voltage range being a narrowed and centered voltage range within the control voltage range.

Abstract: Systems and methods for compensating for a known interferer to a Controlled Oscillator (CO) of a Phase-Locked Loop (PLL) are disclosed. In one embodiment, a system includes a PLL and a compensation system. The compensation system is configured to generate a compensation signal based on a complex correlation of an output signal of a phase detector of the PLL and a signal derived from a replica of a known interferer to the CO. The compensation system is further configured to apply the compensation signal to the control signal provided by the low-pass filter of the phase-locked loop to thereby provide the compensated control signal for the CO of the phase-locked loop. In this manner, the compensation system mitigates the known interferer at the CO of the PLL.

Abstract: A clock and data recovery (CDR) circuit employing zero-crossing linearizing (ZCL) technique. The circuit including a voltage controlled oscillator (VCO), an inject-locked divider (ILD), a variable delay unit, a linearized loop, a bang-bang loop, and a loop filter (LP). The differential clock generated by VCO passes through ILD for frequency dividing and variable delay unit to generate 8-phase clocks. Then using these clocks, the PDs over-sample the input data, followed by synchronization and logic operation to control the CPs output current pulses. These currents filtered by LP control the VCO to finish the loop. The circuit recovers 4 channel data and corresponding clocks of the input with low power broken-down and preferable jitter performance and locking property.

Abstract: A power converter includes a ramp generating unit, a first comparator, a second comparator, and a pulse width modulation (PWM) signal generating unit. The ramp generating unit provides a ramp signal. The first comparator receives the ramp signal and a control signal to provide a normal operation control signal. The second comparator receives the ramp signal and the control signal to provide a dynamic response control signal. The PWM signal generating unit generates a PWM signal according to the normal operation control signal or dynamic response control signal. When the control signal is higher than a threshold of ramp signal, the second comparator provides the dynamic response control signal to the PWM signal generating unit to control it to adjust a duty cycle of the PWM signal.