Abstract: A phase locked loop (PLL) control system includes a voltage-controlled oscillator (VCO) circuit including an inductor and a plurality of capacitors arranged in parallel with the inductor. Digitally enabling or disabling the capacitors in a thermometer coded manner via switches creates tuning states that provide additional frequency range, and each has a limited range of VCO frequency tuning. Slowly ramping the switched capacitance, by implementing the capacitor as a varactor, from one thermal code to the next, provides a wider continuous VCO frequency tuning range for use in the PLL. The slow transition between tuning states allows the PLL to remain in lock, useful under changing operating conditions. Specifically, under changing operating conditions, digital logic detects the PLL tuning control voltage approaching the edge of a VCO band and will add/reduce VCO capacitance effectively transitioning into the adjacent VCO band while the PLL maintains lock via its normal feedback loop.

Abstract: A sensing device with a phase locked loop circuit that has an oscillator to provide an oscillator output signal is presented. The sensing device has a power amplifier to provide at an output of the power amplifier an amplified output signal based on the oscillator output signal. The amplified output signal has an interfering signal component at the oscillator frequency. The sensing device has a measurement circuit to measure offset information regarding a frequency offset between the oscillator frequency and a target frequency of the oscillator. The frequency offset is due to a frequency pulling effect at the oscillator caused by the interfering signal component of the amplified output signal. The sensing device has a control circuit to use the offset information for trimming the phase locked loop circuit and/or the power amplifier, and/or for determining information regarding an environmental situation at the output of the power amplifier.

Abstract: Exemplary embodiments of the present disclosure relate to a touch driving circuit that operates according to an internal clock signal and a touch controller that calibrates a variation in internal clock signal between touch driving circuits. The touch driving circuit operates using an internal clock signal, thus preventing electromagnetic interference caused by a clock signal line that connects the touch controller and a plurality of touch driving circuits. Further, the touch controller calibrates the output frequencies of internal clock signals of the respective touch driving circuits to be the same on the basis of the counting values of the internal clock signals of the touch driving circuits, which are obtained during a certain period before performing touch sensing, and performs touch sensing, thereby performing touch sensing while controlling the plurality of touch driving circuits operating with the internal clock signals without any operational variation.

Abstract: Embodiments are directed towards employing a non-repudiation process for consumer credit requests based on an affirmative authentication of a one-time-pin (“OTP”) generated from a consumer biometric smartcard. The biometric smartcard may authenticate biometric information (e.g. fingerprint, facial image, iris image, or the like) of the consumer based on biometric templates stored on the biometric smartcard. In at least some of the various embodiments, the OTP may be authenticated by an identity authority, such that an associated credit request to a provider may be authenticated. In some embodiments, the provider may request and utilize a credit report for an authentic credit request to determine whether or not the consumer has an acceptable credit rating. If the consumer has an acceptable credit rating, then the provider may provide credit to the consumer.

Abstract: A switched capacitor arrangement for tuning a differential circuit is disclosed. The switched capacitor arrangement comprises a first node, a second node and a third node. The switched capacitor arrangement further comprises a first capacitor coupled between the first node and the second node, a second capacitor coupled between the second node and the third node, and a first switch branch comprising a first switch coupled between the second node and a signal ground node. The first switch has an on state and an off state. The first node and third node are configured to be connected to respective differential nodes of the differential circuit. The switched capacitor arrangement is configured to tune the differential circuit by controlling the state of the first switch.

Abstract: Systems, methods, and circuitries are provided for resonator-based local oscillator signal generation for receiving self-interference signals. An interference cancellation system for a transceiver includes a resonator configured to generate a high-frequency signal and a local oscillator circuitry. The local oscillator circuitry includes a digital-to time converter configured to receive the high-frequency signal and, in response, generate a clock signal for receiving an interfering signal having an interference frequency. Digital cancellation circuitry is configured to adapt operation of the transceiver based, at least in part, on the received interfering signal.

Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.

Abstract: A mechanism is provided for detecting errors and parametric deviations in phase-locked loops (PLLs) by measuring the effectiveness of a PLL in recovering from an introduced delay in phase at a phase comparator of the PLL. Embodiments measure a proxy for the area under a phase difference recovery curve of the PLL. If the phase difference recovery is out of predefined thresholds for the PLL, then an error in the PLL is flagged or responded to. In some embodiments, the PLL is automatically re-trimmed to bring the PLL back within the predefined thresholds.

Abstract: A gesture recognition system includes a transmission unit, a first reception chain, a second reception chain, a customized gesture collection engine and a machine learning accelerator. The transmission unit is used to transmit a transmission signal to detect a gesture. The first reception chain is used to receive a first signal and generate first feature map data corresponding to the first signal. The second reception chain is used to receive a second signal and generate second feature map data corresponding to the second signal. The first signal and the second signal are generated by the gesture reflecting the transmission signal. The customized gesture collection engine is used to generate gesture data according to at least the first feature map data and the second feature map data. The machine learning accelerator is used to perform machine learning with the gesture data.

Abstract: A two-point modulation Phase-Locked Loop (PLL) has a dual-input Voltage-Controlled Oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to an offset Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. The loop path through the VCO has a higher gain than the DAC path through the VCO, which has better linearity. A calibration unit divides the VCO output and counts pulses. The offset DAC has a data input and a gain input. During calibration, the data input of the DAC is set to minimum and then maximum values and VCO output pulses counted, and repeated for two values of the gain input to the DAC. From the four counts a K(DAC) calculator calculates the calibrated gain to apply to the gain input of the offset DAC.

Abstract: A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period; a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.

Abstract: An example frequency converter includes a drift canceling loop with a balanced delay and a linear signal path (e.g., linear with respect to frequency scaling, amplitude modulation, and/or phase modulation). One side of the drift canceling loop includes a fixed delay, and the opposite side includes an adjustable, complementary delay. The adjustable, complementary delay facilitates precision matching of the signal delays on each side of the loop over a range of frequencies, which results in a significant improvement in noise cancellation, particularly at large offsets to the carrier, while permitting the use of a higher noise, but very fast tuning course scale oscillator. The linear signal path from the signal generator to an RF output facilitates modulation of the signal by the signal generator. A modular format is an advantageous embodiment of the invention that includes the removal of the frequency synthesizer's low phase noise reference into a separate module.

Abstract: For example, a digital PLL may include a digitally controlled Ring Oscillator (DCRO) configured to generate a frequency output based on a control signal, the DCRO comprising a plurality of stages in a cyclic order, a first stage of the plurality of stages comprising a plurality of inverter modules controlled by the control signal and comprising a plurality of outputs that drive inputs of a plurality of second stages in the plurality of stages; a decoder to decode a phase of the DCRO based on a plurality of sampled phases of the plurality of stages of the DCRO; and a phase error estimator to estimate a phase error based on the phase of the DCRO and a frequency control word, the control signal is based on the phase error.

Abstract: A phase locked loop (PLL) includes: a phase frequency detector configured to: generate one or more comparison signals indicating whether a reference input signal is leading a feedback signal or whether the feedback signal is leading the reference input signal; a charge pump coupled to the phase frequency detector and configured to convert the one or more comparison signals into a driving current; a loop filter coupled to the charge pump and configured to split the driving current to generate a first voltage signal and a second voltage signal; and a voltage controlled oscillator coupled to the loop filter and configured to: receive the first voltage signal and generate a first control current; receive the second voltage signal and generate a second control current; and combine the first and second control currents to jointly drive a charge controlled oscillator such that the output signal of a desired frequency is generated.

Abstract: A method comprises: using a plurality of gain stages cascaded in a ring topology to form a ring oscillator configured to output an oscillation signal; controlling a supply voltage of said ring oscillator using a low-speed DAC (digital-to-analog converter) in accordance with a coarse control word; providing a capacitive load at an inter-stage node of said ring oscillator using a varactor array controlled by a control voltage array; establishing said control voltage array using a high-speed DAC array in accordance with a fine control word; adjusting the coarse control word upon a start-up to make an oscillation frequency of said oscillation signal approximately equal to target value; and adjusting the fine control word in a closed loop manner in accordance with a detection of a timing error of said oscillation signal.

Abstract: A method of demodulating a signal that is phase modulated to convey R chips having phase transitions between adjacent ones of the R chips to represent chip states, and an overlay symbol spanning the R chips, wherein R>1, and wherein the phase transitions are rotated in a same direction according to an overlay symbol state, comprises: first processing the signal including: accumulating a respective phase of each chip into a respective first chip magnitude, to produce R first chip magnitudes; and accumulating the R first chip magnitudes to produce a first magnitude; second processing the signal including: accumulating a respective phase of each chip into a respective second chip magnitude, to produce R second chip magnitudes; and accumulating the R second chip magnitudes to produce a second magnitude; and determining the overlay symbol state based on the first magnitude and the second magnitude.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may receive an otw signal that is associated with low-path pass information and transmission data. The apparatus may apply a cost function and an update function to the otw signal prior to sending the otw signal to an oscillator. The apparatus may determine a correction factor for use in estimating a gain of the oscillator based at least in part on an output of the update function.

Abstract: An oscillator includes a tunable oscillator, a phase detector circuit communicatively coupled with an output of the tunable oscillator and an input to the oscillator, and an oscillator controller circuit configured to adjust frequency of the tunable oscillator based upon phase detection between output of the tunable oscillator and output of an external resonant element received at the input to the oscillator.

Abstract: Disclosed is a voltage-controlled oscillator (VCO) capable of providing an effective high VCO gain against slow change of an input voltage caused by the variation of manufacturing processes, temperature, voltage, etc. and providing an effective low VCO gain against rapid change of the input voltage for reducing jitter. The VCO includes: an input circuit generating an input current according to an input voltage; a first current supply circuit generating a first output current according to the input current; a second current supply circuit generating a second output current according to the input current; a filter coupled to the input circuit and the second current supply circuit and configured to slow down the influence caused by the variation of the input current on the second current supply circuit; and an oscillating circuit generating an output clock according to the first output current and the second output current.

Abstract: Described is a low power and low jitter phase locked loop (PLL) or delay locked loop (DLL) with digital leakage compensation. The compensation is provided by an apparatus which comprises: a circuitry to generate a pulse with a digitally controlled pulse width, wherein the pulse width is proportional to a static phase error of a PLL or a DLL; and a charge pump coupled to the circuitry, wherein the charge pump is to receive the pulse and to source or sink current to or from a node according to the pulse width.

Abstract: Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.

Abstract: A circuit device includes a driving circuit that generates a clock signal by oscillating a vibrator, a master clock signal generation circuit that generates a master clock signal, and a master clock signal failure detection circuit that detects a failure of the master clock signal. The master clock signal failure detection circuit detects the failure of the master clock signal on the basis of an error detection clock signal, which is the clock signal from the driving circuit, and the master clock signal.

Abstract: A spread spectrum clock generation apparatus includes a frequency modulator configured to generate an output clock signal, a frequency of which is variable with reference to a predetermined center frequency, by frequency-modulating an input clock signal according to a modulation profile signal; and a profile generator configured to generate a nested-modulation profile for controlling the frequency of the output clock signal, generate the modulation profile signal according to the nested-modulation profile, and output the modulation profile signal to the frequency modulator, wherein the profile generator is further configured to generate the nested-modulation profile by varying a cycle and a change range of a triangle modulation profile having a triangle waveform pattern having a pre-designated cycle and a pre-designated amplitude with reference to the center frequency in a time-frequency domain.

Abstract: According to one embodiment, a dual voltage controlled oscillator (VCO) circuit includes a first VCO and a second VCO. The first VCO includes: a first variable capacitor having an input node, a first output node, and a second output node, a second variable capacitor coupled in parallel with the first variable capacitor, a first transistor, and a second transistor, where the first transistor has a first drain coupled to the first output node, a first gate coupled to the second output node, and a first source coupled to a ground, where the second transistor has a second drain coupled to the second output node and a second gate coupled to the first output node, and a second source coupled to the ground. The dual VCO circuit includes a second VCO mirroring the first VCO, a first and a second inductors coupled to the first and the second VCO respectively.

Abstract: A communication system includes a receive antenna for receiving communication signals, processing circuitry for processing the received communication signals and repeating the signals for further transmission and at least one transmit antenna for transmitting the repeated signals. The processing circuitry utilizes configurable settings for controlling the operation of the communication system and the configurable settings are variable for varying the operation of the system. The processing circuitry is further operable for receiving inputs regarding current operating conditions of the communication system and for selectively adapting the configurable settings of the system based upon the operating condition inputs.

Abstract: A circuit device includes an A/D conversion circuit that performs an A/D conversion of a temperature detection voltage, a digital filter that performs digital filter processing of A/D output temperature detection data, a selector that selects A/D output temperature detection data during an activation period and selects filter output temperature detection data during a normal operation period after the activation period, a digital signal processing circuit that outputs frequency control data of an oscillation frequency based on selector output temperature detection data, and an oscillation signal generation circuit that generates an oscillation signal of an oscillation frequency set by frequency control data.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for reducing phase noise in voltage-controlled oscillators (VCOs). One example VCO generally includes a first resonant circuit comprising an inductor and a first variable capacitive element coupled in parallel with the inductor; and a second variable capacitive element coupled to a center tap of the inductor and further coupled to a reference voltage, wherein the center tap of the inductor is further coupled to a voltage source.

Abstract: A fast-locking phase locked loop and a fast locking method are provided. The fast locking method includes dividing a frequency of an oscillation signal by a preset divisor to output a divided signal, detecting a frequency difference between the divided signal and a reference signal, tracking whether a divided frequency of the divided signal falls within a locked frequency range or not, if not, tracking the divided frequency, and if yes, locking the divided frequency, detecting a divided phase difference between a divided phase of the divided signal and a reference phase of the reference signal, recording the phase difference as a tracking reference phase difference, tracking a next divided phase according to the tracking reference phase difference, and determining whether the divided phase falls within a locked phase range, and if not, tracking the divided phase, and if yes, locking the divided phase.

Abstract: A variable capacitor is provided. The variable capacitor includes a plurality of capacitor segments. The plurality of capacitor segments are connected in parallel within the variable capacitor. When a plurality of candidate capacitances allowable to the variable capacitor according to a connection state of the plurality of capacitor segments connected in parallel are sorted in a magnitude sequence, the plurality of candidate capacitances form a geometric series. The variable capacitor is used for a Voltage Controlled Oscillator (VCO), and the VCO is used for a Phase Locked Loop (PLL).

Abstract: A variable capacitor is provided. The variable capacitor includes a plurality of capacitor segments. The plurality of capacitor segments are connected in parallel within the variable capacitor. When a plurality of candidate capacitances allowable to the variable capacitor according to a connection state of the plurality of capacitor segments connected in parallel are sorted in a magnitude sequence, the plurality of candidate capacitances form a geometric series. The variable capacitor is used for a Voltage Controlled Oscillator (VCO), and the VCO is used for a Phase Locked Loop (PLL).

Abstract: Devices and methods for tuning a tunable circuit based on a frequency of operation of the tunable circuit using a clockless frequency detector circuit are described. The clockless frequency detector uses a filter having a slope in its frequency response curve that includes a frequency range of operation of the tunable circuit. Frequency-based attenuation through the filter of an RF signal provided to the tunable circuit is used to provide an indication of the frequency of operation. The tunable circuit, including the clockless frequency detector, can be integrated within a same chip that is autonomously configurable based on the frequency of operation.

Abstract: A semiconductor device according to the present invention has a PLL circuit which includes: a phase comparison part that detects the phase difference between a reference signal and an oscillation signal to produce a phase difference signal indicative of the phase difference in binary and then output the produces signal to outside through a first external terminal; a voltage conversion part that applies, to a phase difference voltage node, a phase difference voltage having a voltage value corresponding to the phase difference represented by the phase difference signal; an oscillation part that produces, as an oscillation signal, a signal having a frequency depending on the phase difference voltage; and a correction circuit that supplies a correction current to the phase difference voltage node, and upon reception of a test control signal at a second external terminal, supplies a current depending on the test control signal to the phase difference voltage node as a correction current.

Abstract: An LC tank circuit, such as an LC tank circuit of a step-tuned voltage controlled oscillator, includes an inductor and one or more capacitors. The inductor can be dog-bone shaped with a body, an extension and a chamfered joint to improve current distribution. The body and the extension can extend along different directions. The body can be narrower than the extension, and the extension can be sufficiently wide to interface with a plurality of switched capacitor circuits coupled to different parts of the extension.

Abstract: A control circuit includes a proportional control unit configured to calculate a proportional value of a difference between an operating value fed back from an object to be controlled and a target value, as a first output value, an integration unit including a suppressing section, the integration unit configured to calculate an integrated value by adding the difference and a previously-calculated integrated value as processed by the suppressing section, and a second output value based on the integrated value, and an output unit configured to output, to the object, a control signal having a value based on the first and second output values. The suppressing section modifies the previously-calculated integrated value to be in a predetermined range if the previously-calculated integrated value is outside the predetermined range.

Abstract: A phase adjusting circuit is provided that can highly precisely adjust frequencies throughout the entire frequency range to be dealt with. A PLL circuit includes: a reference-signal input terminal from which a reference signal is input; a feedback-signal input terminal from which a feedback signal is input; and an output terminal from which an output signal based on a phase difference between the reference signal and the feedback signal is output. A filter circuit is connected to the reference-signal input terminal and the output terminal, and causes a phase of the reference signal to be delayed when the oscillation frequency of an inverter circuit including the PLL circuit falls in a high range. A delay circuit is connected to the output terminal, and causes the output signal to be delayed when the oscillation frequency of the inverter circuit falls in a low range lower than the high range.

Abstract: An oscillator includes a tunable oscillator, a phase detector circuit communicatively coupled with an output of the tunable oscillator and an input to the oscillator, and an oscillator controller circuit configured to adjust frequency of the tunable oscillator based upon phase detection between output of the tunable oscillator and output of an external resonant element received at the input to the oscillator.

Abstract: A method includes: defining a plurality of clock architecture attributes for a plurality of clock domains to be tested; assigning each one of the plurality of clock domains to a first test group; and refining the assignment of each one of the plurality of clock domains based on the plurality of clock architecture attributes until each of the plurality of clock domains is grouped into a current test group.

Abstract: According to one or more embodiments, a method implemented by a digital phase-locked loop of a processor is provided. The method includes turning off, by the digital phase-locked loop, a percentage of active devices of a digitally controlled oscillator to implement a fast path within the digital phase-locked loop. The method also includes reducing, by the digital phase-locked loop, a multiplier of a frequency filter setting to implement a control path within the digital phase-locked loop.

Abstract: Methods and systems are provided for calibrating voltage-controlled oscillators (VCOs). frequency control information, relating to output frequency of a VCO, which varies based on changes in operational conditions, may be determined. The frequency control information enables indicating the output frequency within a range of allowable values for control inputs and a range of expected values based on the operational conditions. For each control input setting, calibration control information for a calibration voltage associated with a control input, may be determined, based on the frequency control information, with respect to the operational conditions, to generate a constant output frequency. The operational conditions may be assessed, and a calibration voltage corresponding to the assessed operational conditions may be determined.

Abstract: A scalable controller circuit that provides faster and simpler regulation of a DC-to-DC converter is provided. Unlike such prior techniques, preferred embodiments do not require any threshold-level generation circuitry or analog compensation circuitry. Preferred embodiments implement a simple control law that requires only a few digital gates. Preferred embodiments can therefore significantly reduce the overhead power consumption and area of the controller in DC-to-DC converters to new levels.

Abstract: Exemplary embodiments disclosed herein relate to a radar device. The radar device may transmit an RF oscillator signal to a radar channel and receive a respective first RF radar signal from the radar channel. The radar device may further generate a second RF radar signal. Frequency conversion circuits are also disclosed to down-convert the first RF radar signal and the second RF radar signal. An analog-to digital conversion unit may digitize the down-converted first RF radar signal and the down-converted second RF radar signal to generate a first digital signal and a second digital signal, respectively. A digital signal processing unit is disclosed to estimate a phase noise signal included in the second digital signal and to generate a cancellation signal based on the estimated phase noise signal. The cancellation signal is subtracted from the first digital radar signal to obtain a noise compensated digital radar signal.

Abstract: An illustrative digital communications receiver and a fractional-N phase lock loop based clock recovery method provide substantially reduced sensitivity to nonlinearities in any included phase interpolators. One receiver embodiment includes: a fractional-N phase lock loop, a phase interpolator, a sampling element, a phase detector, a phase control filter, and a frequency control filter. The phase interpolator applies a controllable phase shift to the clock signal from the frac-N PLL to provide a sampling signal to the sampling element. The phase detector estimates timing error of the sampling signal relative to the analog receive signal. The phase control filter derives a phase control signal for the phase interpolator which operates to minimize a phase component of the estimated timing error. The frequency control filter derives the frequency control signal in a fashion that separately minimizes a frequency offset component of the estimated timing error, reducing the interpolator's phase rotation rate.

Abstract: A system for determining a correction for an output value of a time-to-digital converter within a phase-locked loop is provided. The output value relates to a time difference between an input signal and a reference signal supplied to the time-to-digital converter. The system includes a digitally-controlled oscillator configured to generate a first signal independently from the output signal. The first signal has a first frequency different from an integer multiple of a reference frequency of the reference signal. The system further includes a frequency divider configured to generate the input signal for the time-to-digital converter based on the first signal. The input signal has a second frequency being a fraction of the first frequency. Further, the system includes a processing unit configured to calculate the correction using a distribution of output values of multiple time differences.

Abstract: An energy supply device comprises an analysis unit for determining a signaling information which indicates a state of operation of the energy supply device, and a communication interface for outputting said signaling information. The analysis unit is designed to detect an operating variable of the energy supply device; to set a characterization parameter; and to characterize the detected operating variable of the energy supply device as a function of the characterization parameter in order to obtain the signaling information.

Abstract: A frequency tuning apparatus includes: a frequency tuner configured to tune an oscillation frequency of an oscillator based on target information extracted from a mapping table in correspondence to a target frequency, and oscillation information collected from the oscillator; and a frequency compensator configured to compensate for a compensation error between the tuned oscillation frequency and the target frequency based on an offset table.

Abstract: A digital phased lock loop includes a digital controlled oscillator configured to produce an output signal at an output signal frequency, and a phase comparator configured to compare the output signal or a signal derived from the output signal, with a reference signal at a reference signal frequency or a signal derived from the reference signal to produce a phase error signal. A first loop filter produces a first control signal for the digital controlled oscillator. A frequency error measuring circuit produces a frequency error signal that directly represents a frequency difference between the output signal frequency and the reference signal frequency. A second loop filter produces a second control signal for the digital controlled oscillator from an output of the frequency error measuring circuit. A circuit combines the first and second control signals and providing the combined control signals to the digital controlled oscillator.

Abstract: Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.

Abstract: Systems and methods are disclosed for detecting and compensating for timing excursions in a data channel. If a signal contains discontinuities in phase, a detector of the channel may lose lock on the signal, resulting in the channel incorrectly adjusting a sampling phase toward a following symbol or previous symbol. This is referred to as a cycle slip, where the integer alignment of the sampling of a signal contains a discontinuity over the duration of a sector, preventing decoding of the signal. A circuit may be configured to detect a cycle slip during processing of a signal at a data channel based on timing error values, and when the signal fails to decode, shift an expected sampling phase of a detector for a subsequent signal processing attempt. Shifting the expected sampling phase can cause the channel to adjust the sampling phase in the correct direction, thereby preventing a cycle slip.

Abstract: An oscillator module used with a plurality of power sources includes an oscillator unit, a clock monitor unit (CMU), a software module and a digital calibration circuit. The oscillator unit generates a clock signal. The CMU is coupled to the oscillator unit, determines whether an amplitude of the clock signal exceeds a predetermined threshold, and outputs an alarm signal if the amplitude of the clock signal is lower than the predetermined threshold. The software module is coupled to the CMU, and receives the alarm signal to output a calibration signal. The digital calibration circuit is coupled to the oscillator and the software module, and outputs a control signal in response to the clock signal and the calibration signal, adjusting the plurality of power sources to modify the clock signal.

Abstract: A method of generating a spread spectrum signal is disclosed. The method includes selecting a first pseudorandom slope for a modulation curve. A current frequency on the modulation curve is selected. An oscillating signal is produced at the current frequency for a respective time. The current frequency is set to a next frequency on the modulation curve. The steps of producing an oscillating frequency and setting the current frequency to a next frequency are repeated until the current frequency is a final frequency on the modulation curve.