Abstract: A receiving apparatus has a clock frequency generating circuit comprising in a first embodiment a low cost oscillator whose frequency is higher than the wanted clock frequency and in a second embodiment a low cost oscillator whose frequency can be higher or lower than the wanted clock frequency. By means of subtracting pulses from (first embodiment) or adding/subtracting pulses (second embodiment) to/from the output of the low cost oscillator, a clock frequency is generated which is stable within a specified tolerance range.

Abstract: A current-controlled oscillator (ICO) circuit including an all p-channel transistor based ring oscillator, a first current mirroring stage, and a second current mirroring stage. The all p-channel transistor based ring oscillator, p-channel transistors in the input structure of each amplification stage, and metal lines in the ring and from the ring to the amplification stages over an n-well improve noise immunity and tolerance. The first current mirroring stage utilizes an input current to generate a first voltage controlling a series of differential delay cells connected in a ring topology that forms the ring oscillator. The second mirroring stage utilizes a precision current to generate a second voltage controlling at least one amplification stage, which converts corresponding delay cell output signals to a single-ended logic level signal compatible with external circuitry needs.

Abstract: Increase of frequency and reduction of power consumption are advanced for a voltage controlled oscillation circuit. A capacitor C1 is connected between emitters of first and second transistors Tr1, Tr2 to receive an electric current from constant current sources Cs1, Cs2. Also, emitters of third and fourth transistors Tr3, Tr4 receive an electric current from a constant current source Cs3 and have their respective collectors connected through third and fourth resistors R3, R4 to a power supply terminal VCC. The respective collectors and bases of the third and fourth transistors Tr3, Tr4 are connected to bases and collectors of the first and second transistors Tr1, Tr2. Due to this, oscillation outputs are caused at respective ends of the capacitor C1, which has a voltage amplitude equal to a voltage drop due to the third and fourth resistors R3, R4 and values of currents flowing through them. The voltage drop can be decreased to such an extent that the first and second transistors Tr1, Tr2 can be turned on.

Abstract: A variable frequency oscillator including an oscillation unit including a ring oscillator having multiple loops, and a frequency control unit controlling switching among the multiple loops in accordance with a control input indicative of an oscillation frequency and thus generating an oscillation signal having the oscillation frequency.

Abstract: A ring-type signal controlled oscillator comprising a series of active delay elements, each including a respective differential pair of transistors. The inputs and outputs of the differential pair transistors are interconnected in a closed ring to produce oscillations at a frequency determined by the delay of each delay element. The differential pair of transistors further has a pair of current source inputs for controlling an amount of delay of the delay element, and a pair of load inputs for stabilizing the amount of delay. The invention advantageously provides high frequency operation with substantially symmetric rise and fall time, while limiting spread in oscillation frequency and spread in amplitude in relation to fabrication process variability and power supply variability.

Abstract: Of the MOSFETs used to implement an oscillator circuit or a delay circuit in a semiconductor device, minimally the MOSFETs P12 (N12) used in a part of the circuit that affects the oscillation period or delay time are low-threshold-voltage type MOSFETs.

Abstract: The present invention includes a voltage control circuit having at least one voltage-controlled oscillator and at least one voltage controller connected to the voltage controlled oscillator. The voltage controller has at least one voltage input for supplying an input voltage to the voltage controller, a control signal input for supplying a control signal to the voltage controller, and a voltage output connected to the voltage controlled oscillator for supplying an output voltage thereto. The output voltage controls the delay of the voltage controller oscillator by supplying the control signal to the voltage controller.

Abstract: A digital oscillation generator has a first feedback-supplied adder that has an input side connected to a first control input, a second feedback-supplied adder that has an input side connected to a second control input, a further adder that has an input side connected to a third control input and to the respective outputs of the first and second feedback-supplied adder, and a memory that has an input side connected to an output of the further adder and that has a first oscillation output.

Abstract: An oscillator circuit having a first programmable divider for obtaining a reference signal by dividing the frequency of an oscillation signal of a piezoelectric resonator by a frequency dividing number M. A PLL circuit using the reference signal as input thereto to obtain a multiplied signal, the multiplied signal being formed by multiplying the input signal by a second frequency dividing number N for a second programmable divider provided in a feedback circuit. A third programmable divider capable of dividing the frequency of the multiplied signal by a third frequency dividing number X and outputting the frequency-divided signal. The frequency dividing numbers M, N, and X can be set to values independent of each other. Therefore, innumerable combinations of the frequency dividing numbers M, N, and X can be used and the number of frequencies producible by one oscillator can be largely increased by enabling selection of any suitable one of such combinations.

Abstract: In a phase locked loop (PLL) circuit, a phase comparator compares an input signal and a feed back signal in phase to generate a phase difference voltage signal. A loop filter filters the phase difference voltage signal, and generates a filter output voltage signal. A bias signal generating section automatically generates a bias signal. A voltage controlled oscillating section generates an oscillation output signal based on the filter output voltage signal and the bias signal. The voltage controlled oscillating section generates the oscillation output signal having a same frequency as that of the input signal based on the bias signal. A counter generates the feed back signal based on the oscillation output signal.

Abstract: An oscillator having a feedback loop circuit formed by two transductors and one amplifier, and two capacitors respectively connected to the outputs of these transconductors. The transconductors and the amplifier are constructed by common-source configuration transistors to which common bias current is supplied. Since they have invert characteristics for the input voltage, the feedback loop is also self-biased by means of negative feedback operation. The oscillation signal is outputted from an arbitrary position on the feedback loop of the oscillator. According to the oscillator as constituted, the oscillation frequency can be controlled in a wide range by varying the bias current to the common-source transistors.

Abstract: In a voltage controlled oscillator including an odd number of inverter circuits connected in a ring shape, at least one of the inverter circuits is constructed by an inverter and a current control circuit connected in series between a pre-stage inverter circuit and post-stage inverter circuit, and a voltage control circuit connected between the pre-stage inverter circuit and the post-stage inverter circuit. The inverter receives an output signal of the pre-stage inverter circuit to generate an inverted signal. The current control circuit supplies a current in accordance with the inverted signal to the post-stage inverter circuit. The current is controlled by an input voltage. The voltage control circuit charges and discharges an input capacitance of the post-stage inverter circuit in accordance with the output signal of the pre-stage inverter circuit.

Abstract: In plural oscillation systems each of which can be described by the van der Pol equation, each oscillation system is reciprocally connected with at least one oscillation system other than the own oscillation system by a coupling factor to realize automatically the phenomenon of synchronization of the respective oscillation systems to enable spontaneous tuning of the entire system. A self-excited oscillation of an oscillation system prescribed by a van der Pol equation is controlled on/off by varying an applied voltage as a variable.

Abstract: A voltage controlled ring oscillator (VCRO) that can operate at low voltage and provide a variable periodic output. A plurality of transistors form a ring oscillator and a selected transistor in the ring oscillator has a body which can float with respect to ground potential. The selected transistor has a threshold voltage which is controllable by a voltage applied to the transistor body. A control input is coupled to the transistor body such that the body of the transistor can be charged by the control input. Charging the body alters the threshold voltage of the transistor and thereby controls the oscillation frequency of the oscillator.

Abstract: An RF/Microwave oscillator is disclosed that has the high-Q, low-loss, and phase noise performance of a DRO, without the need of a dielectric resonator to achieve such performance. The RF/Microwave oscillator includes a field effect transistor having a drain coupled to an output circuit, a source coupled to a series feedback circuit, and a gate coupled to a resonator circuit. Each of these circuits are comprised of cascaded pairs of coupled transmission lines designed to resonate at the operating frequency of the oscillator. The RF/Microwave oscillator may also include a frequency-adjustable bias circuit, a frequency-adjustable FET gate return, and a frequency tuning circuit.

Abstract: An integrated circuit (11) has a frequency detection circuit (22) which provides one or more digital signals (50) to a current source (26) based upon a detected frequency of operation of a generated reference clock (48). The signals (50) allows the current source (26) to change its operational state between two or more discrete current output levels in a digitally-controlled manner. Using signals (50), a high current output level can selected and provided by the current source (26) to the external oscillator circuit (16) during a start up mode to ensure that the integrated circuit (11) can start up in an optimally reduced time period. After a start up operation is complete, the signals (50) can then be used to switch the current source (26) into a lower current operational mode whereby electromagnetic interference (EMI) effects are reduced during the normal modes of operation occurring after start up.

Abstract: A method for centering the frequency of an injection locked oscillator or (ILO) includes producing measurements of the magnitude and sign of the phase difference between ILO output signals in response to alternate high level and low level RF drive signals, and tuning the center frequency of the ILO in accordance with the measurements to minimize the phase difference.

Abstract: A variable high frequency voltage controlled oscillator (VCO) which is fully integrated. By controlling, with a control voltage, the collector current flowing through one transistor of the integrated oscillator circuit, the diffusion capacitance (also known as base-charging capacitance) of that transistor is varied. Since, in conjunction with an inductance, this capacitance to a large degree determines the frequency of oscillation of the integrated circuit, a fully integrated VCO is made possible.

Abstract: An oscillator circuit contains a switching circuit which periodically charges and discharges a capacitive node. The capacitive node is coupled to the input of the switching circuit via a loop circuit, so that signal transitions at the capacitive node travel through the loop circuit and cause new transitions. The oscillator contains a power supply current source and a mode breaker circuit which function to stabilize the oscillating frequency and to suppress spurious modes of operation, respectively. The mode breaker circuit contains a conduction path which is used to frustrate charging of the capacitive nodes in certain spurious signal configurations. To prevent the mode breaking function from interference between the stabilizing function, the mode breaker circuit is arranged so that it blocks the conduction path during the critical time-intervals when the loop operates in a desired mode.

Abstract: The present invention comprises a CMOS voltage controlled oscillator (VCO) circuit for operation at frequencies of 1 GHz and above. The circuit of the present invention includes a voltage-to-current converter circuit for receiving a VCO input, a replica circuit coupled to the voltage-to-current converter circuit, and a first and second VCO cell coupled to the replica circuit. The first and second VCO cells are also coupled to one another. The circuit of the present invention also includes a VCO output for transmitting a VCO output signal. A first current source is coupled to the first VCO cell to transmit a first current from a power supply to the first VCO cell. A second current source is coupled to the second VCO cell to transmit a second current from the power supply to the second VCO cell.

Abstract: A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit comprising: a voltage controlled oscillator having a control node and an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.

Abstract: A differential delay circuit type ring oscillator allows for an increase in operation enabling frequency and dynamic range. At each stage of the ring, delay circuit output signals arc linearly varied above and below the circuit switching level. The ring oscillator includes a plurality of differential delay circuits coupled in series in a ring configuration, a differential amplifier, and a comparator. Each of the differential delay circuits receives first and second differential input signals, and delays the received signals by a predetermined time in response to a predetermined control signal to generate first and second differential output signals. The differential amplifier receives the first and the second differential output signals of one of the differential delay circuits and amplifies the received signals to generate first and second differential amplified signals.

Abstract: A CMOS (complementary metal-oxide semiconductor) high-frequency ring oscillator is provided for generating an output frequency in response to a control voltage in a wide bandwidth. The ring oscillator is of the type including a plurality of cascaded delay circuits, such as CMOS CSL (common-sense logic) inverters. The ring oscillator is characterized by the additional incorporation of each of the CMOS CSL inverters with either a positive-feedback gate structure or a positive-feedback drain structure so as to improve the output-to-output characteristics of the ring oscillator. More specifically, the ring oscillator is still operable to output an oscillating signal even though the control voltage is reduced to below a certain level, at which point the gain is still larger than 1. The ring oscillator is therefore more advantageous than the prior art both in gain and output-to-output characteristics and is operable over a wide variety of output frequencies, particularly in the low-frequency regions.

Abstract: Disclosed is a multiple feedback loop ring oscillator and delay cell with high oscillation voltage. It is an object of the present invention to implement a new ring oscillator for the VCO of a high speed PLL and a proper delay cell with a high speed and low noise. The apparatus is composed of multiple feedback loop ring oscillator that 4 delay cells which have the first main input stage, the second main input stage, the first subsidiary input stage, the second subsidiary input stage, the third subsidiary input stage, the forth subsidiary input stage, the first output stage and the second output stage is connected to the main loop and subsidiary loop. The present invention has advantages that it can be operated in high speed, it has a low power sensitivity, there is no power noise because there is no variation of a supply current and it can improve noise characteristics.

Abstract: An oscillator having an adjustable output frequency comprises a resonator, an inverting amplifier coupled to the resonator, a variable capacitance coupled to the resonator and to the amplifier, and a shift register coupled to the variable capacitance. The variable capacitance comprises a first bank of switchable capacitors coupled to an input of the oscillator and a second bank of switchable capacitors coupled to an output of the oscillator. The shift register includes a plurality of bits and is configured such that the logic state of each bit determines the switching state of a corresponding capacitor from each bank of switchable capacitors. By shifting the bits in the shift register, the variable capacitance is varied, causing an adjustment in the output frequency of the oscillator.

Abstract: A source for a linear homodyne transceiver that generates repeated linear chirps. A YIG oscillator with a main coil and an FM coil receives a basic linear current ramp at the main coil to generate a chirp. The FM coil is coupled to receive a PLL error signal. The PLL receives a sample of the output signal from the YIG oscillator at one input and a linear chirp reference signal at the other input generated by a DDS chirp generator. Any variation between the linear chirp frequency at any instant and the actual frequency output by the YIG is corrected by an error signal to the FM coil to correct for nonlinearities of the YIG caused by variations in the chirp rate, the rate of change of frequency per second per chirp, temperature variations and microphonics.

Abstract: A voltage-controlled oscillator has a feedback circuit connected to the gate of a transistor which controls a current flowing through an oscillation unit. The feedback circuit applies a voltage depending on the DC voltage of an oscillated signal to the gate of the transistor. When the oscillated signal is reduced in level to lower the DC voltage, the feedback circuit lowers the voltage applied to the gate of the transistor. The current flowing through the oscillation unit is reduced to increase the level of the oscillated signal. When the oscillated signal is increased to increase the DC voltage, the feedback circuit increases the voltage applied to the gate of the transistor. The current flowing through the oscillation unit is increased to reduce the level of the oscillated signal. The feedback process prevents the voltage-controlled oscillator from operating unstably regardless of manufacturing variations of transistors from design values.

Abstract: An oscillator circuit residing internally to a semiconductor device for generating a clock signal for use by digital circuits. The oscillator circuit includes a voltage regulator circuit responsive to frequency selection signals for selecting a predetermined frequency and a supply voltage. The voltage regulator circuit is operative to generate a voltage reference signal having a voltage level being adjusted to compensate for variations due to temperature, process and supply voltage variations. The oscillator circuit further includes a ring oscillator circuit responsive to the voltage reference signal for generating a clock out signal having a particular frequency based upon the voltage level of the voltage reference signal. Wherein the frequency of the clock out signal remains substantially constant despite temperature, process and supply voltage variations in the semiconductor circuit.

Abstract: A voltage controlled oscillator which causes little interference to and receives little interference from other circuits via a parasitic capacitance of an integrated capacitor, has a good control linearity, and is capable of being used over a wide range of frequency including ultra high frequencies, constituting a ring oscillator by being provided with three or more logic buffer circuits having differential input and output terminals cascade connected at the differential inputs and outputs and making the n-th differential output a negative feedback to the terminal of the 1st differential input. Each of the logic buffer circuits comprises a differential transistor pair comprised of first and second transistors, first and second diode array each comprising at least one diode, first and second integrated capacitors, and a current source for frequency control. The sum of emitter currents of the pair of the differential transistors is set by the current source for frequency control.

Abstract: A PLL (phase locked loop) oscillator suitable as a clock signal source for use in a computer system or the like includes a piezoelectric resonator, an oscillating circuit for generating an oscillating signal in cooperation with the piezoelectric resonator, and a PLL circuit which operates using the oscillating signal generated by the oscillating circuit as a reference signal, all these elements being housed in a package, the frequency of the output signal of the PLL oscillator being determined by the oscillation frequency of the oscillating circuit and the frequency dividing ratio of a programmable frequency divider in the PLL circuit, wherein the frequency dividing ratio of the programmable frequency divider is set by writing the data representing the frequency dividing ratio into a programmable read only memory thereby setting the output frequency to a desired value.

Abstract: A tunable local oscillator (10) with a tunable circuit (12) that includes a resonator (16) and a transistor (14) as an active element for oscillation. Tuning of the circuit (12) is achieved with an externally applied dc bias (22, 24) across coupled lines (20) on the resonator (16). Preferably, the resonator (16) is a high temperature superconductor microstrip ring resonator with integral coupled lines (20) formed over a thin film ferroelectric material. A directional coupler (38) samples the output of the oscillator (14) which is fed into a diplexer (40) for determining whether the oscillator (14) is performing at a desired frequency. The high-pass and low-pass outputs (42, 44) of the diplexer (40) are connected to diodes (48, 46) respectively for inputting the sampled signals into a differential operational amplifier (50). Amplifier (50) compares the sampled signals and emits an output signal if there is a difference between the resonant and crossover frequencies.

Abstract: A ring oscillator comprising: a plurality of sub-feedback loops, each comprising a pair of serially connected inverters and a feedback inverter having its input coupled to the output of the pair of inverters and its output connected to the input of the pair of inverters, the pairs of inverters being connected in a ring, and a downstream inverter of each respective pair of inverters forming an upstream inverter of an immediately following pair of inverters.

Abstract: An oscillation device includes a buffer device, a feedback device for feeding back an output of the buffer device to an input thereof and a charging device and a discharging device connected to the input of the buffer device. The charging device includes a first switching device that is turned on and off based on the output of the buffer device and a first current control device that controls the current flowing into the input of the buffer device through the first switching device. The discharging device includes a second switching device that is turned on or off based on the output of the buffer device and a second current control device that controls the current flowing out of the input of the buffer device through the second switching device. The first and second switching devices include first and second transistors and the first and second current sources that include third and fourth transistors.

Abstract: With a VCO 1 which constitutes the voltage controlled oscillator according to the present invention, since NMOS transistors N11, N12 and N13 are provided in each of inverter circuits 11, 12 and 13, the oscillating frequency band can be divided into three sub ranges. As a result, even when the VCO gain effected by a control signal VCN is reduced, a wide frequency band is assured, thereby making it possible to easily support the clock frequency required by the system into which the VCO 1 is to be incorporated.

Abstract: A ring oscillator generates a pulse signal having a frequency determined in response to a level change in the source voltage.

Abstract: An internal voltage generation circuit down converts an external power supply voltage on the basis of a reference voltage. An oscillator outputs a pulse voltage according to a power supply voltage. A pump circuit generates the internal voltage according to the pulse voltage. A control circuit for the oscillator may include a current mirror amplifier so that when the power supply voltage is reduced the frequency of the pulse voltage becomes higher a corresponding amount and when the power supply voltage is increased the frequency of the pulse voltage becomes lower a corresponding amount.

Abstract: A duty cycle control buffer uses an edge detector input stage to detect the transitions of an unpredictable clock signal input. The edge detector generates one shot output signals in synchronism with the clock signal. A pulse width controllable monostable multivibrator converts the one shot signals into rectangular pulses, at the same frequency as the original clock input. The rectangular pulses are inverted and then averaged, to provide a voltage input to one side of an operational amplifier. A reference voltage is supplied to the other side of the operational amplifier, such that the difference between the average voltage and the reference voltage generates an output control voltage from the operational amplifier. This control voltage provides negative feedback to a pulse width control stage within the monostable multivibrator, thereby adjusting the pulse width of the rectangular pulse output until a steady state is reached.

Abstract: The invention provides an improved variable capacitance circuit which is substantially linearly controlled using voltage or current control. The circuit comprises two emitter connector transistors and a constant current source or drain forming a current steering circuit. A fixed capacitor is connected to the emitters of the transistors forming a port into the circuit. AC current into the port flows through the fixed capacitor and is fed back through the transistors in a proportion depending on the voltage at their bases. The effective capacitance of the circuit is varied using this variable AC feedback arrangement. Other embodiments use current control to vary the circuit capacitance by varying the effective constant current source level.

Abstract: A relaxation oscillator includes a first capacitor at the terminals of which there is a first voltage V.sub.1, a circuit to charge the first capacitor from a power supply voltage, a circuit to discharge the first capacitor, and a switch which alternately charges and discharges the first capacitor responsive to a control signal. The relaxation oscillator also includes a relaxation circuit to generate the oscillation signal and the control signal from the first voltage. The oscillator also includes a regulation circuit to cause the first voltage applied to the relaxation circuit to be approximately equal to a reference voltage. The circuit for charging the first capacitor includes a resistance R.sub.1. The relaxation oscillator is particularly applicable to phase locked loops.

Abstract: A voltage controlled oscillator (VCO), for use in a phase locked loop for clock multiplication, for example in recovery of data pulses from a data stream input comprising digital data with unknown phase. According to the invention, the VCO comprises a plurality of VCO stages, each stage being implemented as a differential amplifier. The amplifier load is formed of two cross-coupled gate devices and of two gate devices which are connected as diodes. The differential input is applied to a source coupled input pair as well as to two pull-down gate devices.

Abstract: An integrated circuit complementary metal-oxide silicon (CMOS) voltage controlled oscillator (VCO) includes a plurality of variable delay elements, connected in a ring configuration, each variable delay element including a pair of parallel connected differential CMOS sections. The parallel-connected differential CMOS sections of each variable delay element are controlled by a differential control voltage whose magnitude sets relative levels of operation of the two differential sections of each variable delay element. These relative levels of operation determine the delay through the variable delay element. A current mirror circuit provides the differential control voltage.

Abstract: A single-gate SCFL delay cell is disclosed for implementation in a common ring oscillator VCO. The delay cell has a differential input stage the output current from which is fixed by two resistors. The differential input stage drives a source follower output stage providing an output capable of driving the differential input of the next stage of the oscillator. The current sources typically used in the source follower output stage have been replaced by voltage-to-current converters. The voltage-to-current converters are comprised of two MESFET devices the gates of which are coupled to a differential control voltage. The source of each of the two devices is coupled to a current source the value of the two current sources being equal. The resistor couples the two sources together such that the voltage drop across the resistor governs how much current is conducted by each of the two devices.

Abstract: A voltage-controlled oscillator VCO capable of reliably generating an oscillation even if it, after stopping with electric charges remaining on both of its capacitors, is restarted under the same conditions. Even if the VCO is started with charges remaining on capacitors, N-channel transistors are both turned on because outputs of differential circuits are both at H level. N-channel transistors are both turned off because their gates are connected with the drains of the N-channel transistors. Therefore, in no case, the levels at points C and D as outputs on both sides of latch circuit go to L level at the same time.

Abstract: An oscillation circuit that improves the duty controllability by cross-coupling ring oscillators that are comprised of current inverters. The sources of current supply circuits 4a-4c and 6a-6c are connected to a power supply and their drains are connected to terminals A in corresponding current inverters, respectively. Each of the gates of those current supply circuits receives an output of a current inverter corresponding, one to one, to a current inverter to which the current supply circuit is connected.

Abstract: An integrated circuit complementary metal-oxide silicon (CMOS) voltage controlled oscillator (VCO) includes a plurality of variable delay elements, connected in a ring configuration, each variable delay element including a pair of parallel connected differential CMOS sections. The parallel-connected differential CMOS sections of each variable delay element are controlled by a differential control voltage whose magnitude sets relative levels of operation of the two differential sections of each variable delay element. These relative levels of operation determine the delay through the variable delay element. The control circuit provides the differential control voltage. The control circuit includes a first section for generating a control current and a pair of current mirror sections that divide the control current, generating a pair of differential control signal components as VGS potentials of a pair of CMOS transistors configured as current mirrors.

Abstract: A CMOS voltage controlled oscillator (VCO) having an improved voltage-to-current converter and an active MOS load operating in the triode region to provide improved performance characteristics including a small differential logic swing and a high frequency output. The voltage-to-current converter of the CMOS VCO comprises a pair of MOS transistors, one of which has an aspect ratio (W.sub.P /L.sub.P) and the other of which has an aspect ratio (W.sub.P /L.sub.P)/n, wherein 1<n<4. This configuration causes a third MOS transistor in the voltage-to-current converter to operate exclusively in the triode region. The CMOS VCO also includes an ICO portion having a plurality of delay stages connected in a ring configuration. Each of the delay stages comprises a pair of input MOS transistors and a pair of load MOS transistors. In accordance with the invention, the voltage-to-current converter causes each of the load MOS transistors to operate in the triode region.

Abstract: An object is to keep the oscillation gain nearly constant and attain an oscillation frequency with high stability and low jitter. A voltage controlled oscillator circuit (VCO) is constructed by a VCO control circuit and a ring oscillator. The VCO control circuit has two input terminals (n input, w input). The VC control circuit multiplies the n input by the w input, and outputs a control signal (PMOS n input, NMOS n input) obtained by adding the result of multiplication to the n input. The ring oscillator is constructed by delay circuits of an odd number of stages serially connected.

Abstract: This invention provides a voltage control oscillator that can reduce swing width and more precisely can control a period of the oscillator by applying a back bias voltage to a back bias terminal of a transistor so that an output pulse of the oscillator is controlled. The present invention comprises a plurality of inverters which are connected to each other in the form of a chain, each inverter having a pull up device and a pull down device; a first control block connected to a bulk of each pull up device to supply a desired voltage to said bulk so that threshold voltage of each pull up device is controlled; and a second control block connected to a bulk of each pull down device to supply a desired voltage to said bulk of each pull down device so that threshold voltage of each pull down device is controlled. The present invention can precisely control the oscillator since variation width of the period is small and can minimize a circuit without addition of a buffer since swing width is constant.

Abstract: A quadrature oscillator based on two cross-coupled gm/C cells utilizes the inherent nonlinearity of positive and negative impedance cells to control the amplitude of oscillation, thereby simplifying the oscillator and eliminating the need for an outer control loop. The oscillator includes a pair of cross-coupled gm/C stages. A negative impedance cell is coupled to each gm/C cell for assuring proper start-up and enhancing the amplitude of oscillation. A positive impedance cell is also coupled to each gm/C cell to dampen the amplitude of oscillation. The transconductance of each impedance cell varies in response to the bias current provided to the cell. Thus, by controlling the bias currents through the cells, the negative and positive impedances seen by each gm/C cell can made to cancel at the desired oscillation amplitude, so that the circuit oscillates without any damping or enhancement.

Abstract: A ring oscillator comprises a ring of delay stages in which the output of each stage is input to the next stage in the ring. Tuning of the oscillation frequency of the oscillator is achieved by additionally taking outputs from delay stages elsewhere in the ring as one or two secondary inputs to each delay stage and mixing this or these in variable proportions with the primary input.