Abstract: An apparatus of a station (STA) includes memory and processing circuitry coupled to the memory. The processing circuitry is configured to encode a capabilities element for transmission to an access point (AP). The capabilities element including a media access control (MAC) capabilities information field indicating a trigger frame MAC padding duration. The processing circuitry decodes an extremely high throughput (EHT) protocol data unit (PPDU) received in response to the capabilities element. The EHT PPDU includes an EHT trigger frame (EHT-TF) in a data portion of the EHT PPDU, a packet extension (PE) field, and a dummy orthogonal frequency division multiplexing (OFDM) symbol extending the PE field. The processing circuitry performs physical layer (PHY) and MAC processing of the EHT PPDU based on a duration of the dummy OFDM symbol.

Abstract: Various embodiments of the invention relate to calibrate a wideband segmented Voltage Controlled Oscillator (VCO). Upon initial calibration, information of frequency spanning ranges of each segment in the VCO may be saved into a memory. When the VCO is used or activated, a microcontroller reads data from the memory and applied selected information accordingly. The initial calibration involves a frequency sweep process beginning from a first segment with an initial frequency and records any lock detection (LD) signal to the MCU when a frequency/phase lock is engaged from an unlock status or interrupted from a lock status. With the LD signals, frequency bands of the segments may be calibrated, adjusted for temperature compensated, and finalized after associating adjacent segment frequency overlap zone. A frequency band for a segment may be further segmented into multiple sub-bands with corresponding charge pump currents designated respectively for improved phase lock loop phase noise performance.

Abstract: A ring voltage controlled oscillator (VCO) circuit is herein provided. According to one embodiment, a ring VCO circuit includes a plurality of stages connected in series, wherein each stage includes a first inverter, a second inverter, a third inverter and a fourth inverter, the first inverter connected in parallel with the third and fourth inverters and the second inverter connected in parallel with the third and fourth inverters, and a first biasing resistor connected to a first node and coupled to an input of the first inverter. The first biasing resistor includes a first switch configured to set the first biasing resistor to about zero voltage.

Abstract: Aspects of this disclosure relate to reducing settling time of a ramp signal in a phase-locked loop. An offset signal can be applied to adjust an input signal provided to an integrator of a loop filter of the phase-locked loop to cause the settling time to be reduced. Disclosed methods of reducing settling time of a ramp signal can improve settling time of a ramp signal independent of the profile of the ramp signal.

Abstract: An ultra-low power (ULP) oscillator that down-converts the current of a resonator to DC, then amplifies it when its still in DC, followed by up-converting the amplified signal back to the oscillation frequency. The disclosed oscillator eliminates the minimum transconductance (gm) requirement of a Pierce oscillator, by processing the signal at DC. In addition, the circuit only requires the DC amplifier's feedback resistor to be greater than the resistive loss of the resonator, i.e., Rf>Rm.

Abstract: A phased-locked loop (PLL) includes a first oscillator supplying a first oscillator signal with a first jitter component and a second oscillator supplying a second oscillator signal with a second jitter component. The second jitter component is higher than the first jitter component. A selector circuit selects either the first oscillator signal or the second oscillator signal as the PLL output signal. The first oscillator signal and the second oscillator signal may have different frequencies with the lower frequency signal having more jitter. The oscillator producing the signal with less jitter utilizes more power. A continuous time delta-sigma modulator analog-to-digital converter (ADC) receives the PLL output signal as an input clock signal. A high gain setting of an amplifier supplying an input signal to the ADC selects a lower jitter signal input clock signal and a lower gain setting selects a higher jitter input clock signal.

Abstract: A biasing circuit for biasing a switching transistor, wherein the switching transistor is used for switching a respective capacitor cell into/out of a capacitor array, wherein the capacitor array comprises one or more such capacitor cells, and wherein the capacitor array is coupled in parallel with a primary inductor to form an inductive/capacitive tank. The biasing circuit comprises a secondary inductor which is inductively coupled to the primary inductor, the secondary inductor configured to provide a bias signal for biasing the switching transistor.

Abstract: A method and apparatus select an optimal frequency band of a plurality of frequency bands of a multi-band voltage-controlled oscillator (VCO) to achieve a particular output frequency from the multi-band VCO. The optimal frequency band is selected, automatically, based on performing a one-point calibration phase followed by a multi-point calibration phase. The one-point calibration phase produces an initial frequency band selection and the multi-point calibration phase selects the optimal frequency band from a group of frequency bands including the initial frequency band selection, a higher frequency band consecutively higher in frequency relative to the initial frequency band selection, and a lower frequency band consecutively lower in frequency relative to the initial frequency band selection.

Abstract: A locked-loop circuit includes a time-to-digital converter (TDC) having a reference clock input and an error input. A digital loop filter receives an output from the TDC representing a difference between the reference clock input and the error input. A digitally-controlled oscillator (DCO) receives an output from the digital filter in the form of output bits. The DCO has a codeword gain associated with a DCO control word. The codeword gain is applied to the output bits received from the digital loop filter. Calibration logic determines a scaling factor based on a process-voltage-temperature (PVT) operating characteristic. The scaling factor is applied to normalize an actual DCO codeword gain to the codeword gain. The DCO includes an output to deliver an output timing signal having a frequency based on the scaling factor.

Abstract: Apparatus for monitoring a predetermined fill level of a medium in a container, including a mechanically oscillatable unit, a driving/receiving unit for exciting the mechanically oscillatable unit to execute mechanical oscillations and for receiving the oscillations of the mechanically oscillatable unit, and an electronics unit for producing an electrical exciter signal and for evaluating an electrical, received signal.

Abstract: A method and system for injecting a pulsed radio frequency signal into a fluid-containing system in order to create and propagate an electromagnetic field throughout the fluid-containing system. The electromagnetic field may be used to prevent the formation and build-up of scale in the fluid-containing system and/or to prevent the proliferation of bacteria within the fluid-containing system. The method and system may also be used to inject a pulsed radio frequency signal at a number of points in a fluid-containing system, or to inject a pulsed radio frequency signal to a number of independent fluid-containing systems.

Abstract: Methods and systems for a distributed transmission line multiplexer for a multi-core multi-mode voltage-controlled oscillator (VCO) may comprise a plurality of voltage controlled oscillators (VCOs) arranged adjacent to each other, where each of the plurality of VCOs are operable to generate an output signal at a configurable frequency, an impedance matching circuit comprising a respective driver and impedance matching elements coupled to each of the plurality of VCOs, and an output device coupled to the impedance matching circuit. The impedance matching elements may include capacitors and inductors. Between each adjacent pair of the respective drivers coupled to each of the plurality of VCOs, the impedance matching elements may include two inductors coupled in series between the drivers and a capacitor coupled to ground and to a common node between the two inductors. Impedance values of the capacitors and inductors may be configurable.

Abstract: A resonator is supplied with voltage from a constant-voltage source, and the constant-voltage source outputs output voltage adjusted by a voltage adjustment signal to the resonator. The resonator outputs a clock signal having a frequency varied by varying capacitance in accordance with a received control signal and a frequency adjustment signal, and a frequency of the clock signal is varied by voltage output from the constant-voltage source.

Abstract: Low noise switchable varactors and digital controlled oscillator (DCO) circuitry are presented for creating alternating signals at controlled frequencies, including a first transistor for selectively coupling two capacitors between varactor output nodes when a control signal is in a first state, second and third transistors for selectively coupling first and second internal nodes between the respective capacitors and the first transistor with a third internal node when the control signal is in the first state, and an inverter disconnected from the first and second internal nodes to mitigate phase noise and operable to control the voltage of the third internal node according to the control signal.

Abstract: Techniques to determine settings for an electrical distribution network are described. Some embodiments are particularly directed to techniques to determine settings for an electrical distribution network using power flow heuristics. In one embodiment, for example, an apparatus may comprise a model reception component, a forecast component, and an optimization component. The model reception component may be operative to receive a model of an electrical distribution network having multiple capacitor banks and multiple voltage regulators, each of the multiple capacitor banks represented in the model by a model capacitor bank, each of the multiple voltage regulators represented in the model by a model voltage regulator, the electrical distribution network having a radial layout in which power flows from a source to multiple nodes in which each node is associated with one voltage regulator. The forecast reception component may be operative to receive a forecast for demand on the electrical distribution network.

Abstract: Methods of operating a display driver integrated circuit (IC) are provided. A method of operating a display driver IC may include generating a first clock signal, and calculating a frequency of the first clock signal using a second clock signal. Moreover, the method may include generating an adjustment signal using the frequency of the first clock signal and a target frequency, and adjusting the frequency of the first clock signal using the adjustment signal. Related display driver ICs and portable electronic devices are also provided.

Abstract: A phased locked loop (PLL) incorporates multiple voltage controlled oscillators including one that operates in a lower frequency range than an operational VCO used by the PLL. A VCO selection circuit allows the system to select from one or more alternate VCOs. A ring oscillator VCO may be used as the alternate VCO for a PLL that uses a LC VCO for the operational VCO. While the ring oscillator VCO provides lower performance, the ring oscillator VCO allows the system with the PLL to be run at a lower speed for testing, debugging or characterization.

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus tunes a frequency provided by a VCO. The apparatus determines a relative capacitance change associated with a first frequency and a desired frequency from a look-up table. The apparatus adjusts a capacitor circuit in the VCO based on the determined relative capacitance change determined from the look-up table in order to tune from the first frequency to the desired frequency. The apparatus determines that the frequency provided by the VCO is a second frequency different than the desired frequency after adjusting the capacitor circuit. The apparatus performs an iterative search to further adjust the capacitor circuit when a difference between the second frequency and the desired frequency is greater than a threshold.

Abstract: A digitally-controlled oscillator includes a base frequency generator having an odd number of base inverters connected end-to-end to generate an output signal that oscillates at a predetermined frequency and a frequency-adjusting unit connected to the base frequency generator. The frequency-adjusting unit includes a first string of switchable inverters connected in series with each other, the switchable inverters having sizes that decrease from an input end of the first string to the output end of the first string.

Abstract: A clock distributor includes a first oscillator and a second oscillator, to each of which a signal controlling an oscillation frequency is input and to one of which a clock is input; a wiring portion that connects the first oscillator and the second oscillator; a first conversion element that converts an output from the first oscillator into electric current, and outputs a result to a first connection portion connecting to the wiring portion; a second conversion element that converts voltage of the first connection portion into electric current, and outputs a result to the first oscillator; a third conversion element that converts an output from the second oscillator into electric current, and outputs a result to a second connection portion connecting to the wiring portion; and a fourth conversion element that converts voltage of the second connection portion into electric current, and outputs a result to the second oscillator.

Abstract: Apparatus and methods are also disclosed related to an oscillator that includes a switching network configured to tune a resonant frequency of a resonant circuit. One such apparatus includes a switching network having a circuit element, such as a capacitor, that can be selectively coupled to the resonant circuit by a switch, such as a field effect transistor. For instance, the switch can electrically couple to circuit element to the resonant circuit when on and not electrically couple the circuit element to the resonant circuit when off. An active circuit can assert a high impedance on an intermediate node between the switch and the circuit element when the switch is off.

Abstract: There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (20), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.

Abstract: A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal.

Abstract: A phase locked loop system, comprises: a voltage controlled oscillator circuit, comprising a first plurality of switchable varactors for selecting a frequency band of the VCO, that has a gain that changes with frequency band, and a second plurality of switchable varactors for varying the gain in the selected band. The PLL system has a PLL feedback circuit comprising a switching device for switching the feedback circuit to an open loop state wherein a plurality of predefined tuning voltages can be applied to the VCO; a frequency measurement device for measuring the synthesized VCO frequency; and a control unit operable to determine the gain with respect to the synthesized frequency and the tuning voltages.

Abstract: In one embodiment, an apparatus includes a first circuit of a digitally controlled oscillator (DCO). The first circuit has a loss component. A second circuit is coupled to the first circuit and configured to transform a positive impedance into a negative impedance in series with a negative resistance. The negative impedance includes an adjustable reactive component used to adjust a frequency of an output signal of the DCO. An equivalent reactance seen by the first circuit is less than a reactance of the adjustable reactive component.

Abstract: A clock distributor includes unit circuit parts each including an oscillator, a first element configured to convert output voltage of the oscillator into a current, a second element having a voltage current conversion characteristic of an opposite phase to that of the first element, the second element being feedback connected to the first element and the oscillator, a third element configured to convert output voltage of the oscillator into a current, a fourth element having a voltage current conversion characteristic of an opposite phase to that of the third element, the fourth element being feedback connected to the third element and the oscillator; a wiring part to connect a connection part of the first and second elements of a unit circuit part to a connection part of the third and fourth elements of another unit circuit part; and a synchronization circuit connected to the oscillator of a unit circuit part.

Abstract: A frequency synthesizer for a WLAN transceiver is disclosed that may be used to generate 5.4 GHz and 2.4 GHz signals. The frequency synthesizer may be configured to minimize VCO pulling by using VCO operating frequencies that are not integer multiples of the RF bands. Further, the frequency synthesizer may be configured to minimize interference with other frequency bands used by existing wireless systems.

Abstract: In an FSK receiver according to the present invention, a correction operation for a DC offset component is performed based on a maximum value and a minimum value of a demodulation signal. If a difference between the maximum and minimum values is less than a predetermined threshold value TH1, the correction operation is halted. Thus, the FSK receiver can rapidly perform an appropriate offset removal from a multi-level FSK signal.

Abstract: A wideband frequency generator has two or more oscillators for different frequency bands, disposed on the same die within a flip chip package. Coupling between inductors of the two oscillators is reduced by placing one inductor on the die and the other inductor on the package, separating the inductors by a solder bump diameter. The loosely coupled inductors allow manipulation of the LC tank circuit of one of the oscillators to increase the bandwidth of the other oscillator, and vice versa. Preventing undesirable mode of oscillation in one of the oscillators may be achieved by loading the LC tank circuit of the other oscillator with a large capacitance, such as the entire capacitance of the coarse tuning bank of the other oscillator. Preventing the undesirable mode may also be achieved by decreasing the quality factor of the other oscillator's LC tank and thereby increasing the losses in the tank circuit.

Abstract: A voltage controlled oscillator includes a split ring resonator (SRR) configured to have meta-material characteristics fabricated on a board, and an energy compensation circuit configured to cause resonant oscillation of the SRR. The energy compensation circuit is fabricated in the form of an integrated circuit.

Abstract: A system and method for frequency hopping precalibrates a subset of a plurality of channels, storing the channels' associated curves in a computer readable medium. Before hopping to a new channel, decision making circuitry can access the precalibrated curves. If the destination channel has an associated curve, then the system can use the values from that curve when hopping to a new channel. If the destination channel does not have an associated precalibrated curve, then the system can identify a closely situated channel with a precalibrated curve and use an offset value to settle at the destination channel. According to another aspect of the present invention, the offsets can be updated. According to a further aspect of the invention, the updated can be done dynamically.

Abstract: The embodiments described herein provide a voltage controlled oscillator (VCO). The VCO may include, but is not limited to a voltage-to-current converter configured to receive a control voltage and to convert the control voltage to a current, a current bias circuit coupled to the voltage-to-current converter and configured to receive frequency band select digital inputs and to bias the current generated by the voltage-to-current converter based upon the band select inputs, and a ring oscillator coupled to receive the biased current and to output an oscillating signal based upon the biased current.

Abstract: A digitally controlled variable capacitance integrated electronic circuit module (100) comprises a set of basic cells in a matrix arrangement. Each basic cell itself comprises a functional block (11) which can be switched between two individual capacitance values, a control block (12), and a control junction connecting the control block and the functional block of said basic cell. The functional blocks and the control blocks are grouped into separate regions (110, 120) of the matrix arrangement, to reduce capacitive interaction between output paths and power supply paths of the module. The functional blocks can still be switched in a winding path order within the matrix arrangement. A module of the invention can be used in an oscillator capable of producing a signal at 4 GHz.

Abstract: A semiconductor trimming circuit includes parallel coupled PMOS devices coupled in parallel with parallel coupled NMOS devices and an additional pair of dummy NMOS devices. The dummy NMOS devices are coupled in parallel with the NMOS devices. A trimming circuit for an internal clock source may be formed with an array of such switches for selecting one or more trimming capacitors of the trimming circuit. Such an array has a low leakage current and permits good trimming linearity.

Abstract: A method and apparatus is disclosed for voltage-controlled oscillator selection in a multi-mode system having multiple voltage-controlled oscillators. Part of oscillator selection is a calibration operation that utilizes maximum and minimum capacitance limits for a voltage-controlled oscillator, which translates to a frequency range, to calculate overlap regions. Overlap regions comprise frequency ranges that overlap such that the overlap region may be generated by two voltage-controlled oscillators with adjacent frequency ranges. One voltage-controlled oscillator selection routine comprises a real time voltage-controlled oscillator calibration and selection routine that executes every time the system requests a new frequency. Another selection routine comprises a start-up routine that executes only at power up or periodically.

Abstract: A method for compensating NCO jitter by changing a step value used to increment an accumulator in the NCO to make up for inaccuracies, or jitters. In one approach, a remainder in the accumulator may be monitored and a compensated clock close to the current edge of an ideal clock may be generated. In another approach, a compensated clock close to the next edge of the ideal clock may be generated after the current edge of the ideal clock is missed. The step value may be stored in a memory, which may be a register. A jitter compensator may include a comparator for monitoring the remainder in the accumulator or a detector for detecting whether an ideal clock has been missed. The jitter compensator may also change the step value to a step value for a faster clock to compensate jitter.

Abstract: A local oscillation generator (LO-GEN) maintains a fixed bandwidth using a voltage controlled oscillator (VCO) calibration module and gain calibration module that together compensate for variations in the VCO gain based on the oscillation frequency. During an open loop calibration of the LO-GEN, the VCO calibration module programs the VCO gain to an initial coarse value based on the oscillation frequency and then the gain calibration module adjusts the charge pump current to compensate for VCO gain changes.

Abstract: An oscillator circuit includes a clock oscillator which outputs a main clock signal having an oscillating frequency switched between a high frequency and a low frequency in response to a frequency selection signal, and a frequency divider circuit which outputs a sub-clock signal having a divided frequency equivalent to a frequency division ratio of the oscillating frequency of the main clock signal, the frequency division ratio being switched in response to the frequency selection signal. The divided frequency of the sub-clock signal is predetermined for each of the high frequency and the low frequency to which the oscillating frequency is switched in response to the frequency selection signal.

Abstract: An oscillation circuit includes a plurality of MEMS vibrators each having a first terminal and a second terminal, and having respective resonant frequencies different from each other, an amplifier circuit (an inverting amplifier circuit) having an input terminal and an output terminal, and a connection circuit adapted to connect the first terminal of one of the MEMS vibrators and the input terminal to each other, and the second terminal of the MEMS vibrator and the output terminal to each other to thereby connect the one of the MEMS vibrators and the amplifier circuit (the inverting amplifier circuit) to each other.

Abstract: An oscillator includes: a plurality of MEMS vibrators each having a first terminal and a second terminal, and having respective resonant frequencies different from each other; an amplifier circuit having an input terminal and an output terminal; a connection circuit adapted to connect the first terminal of one of the MEMS vibrators and the input terminal to each other, and the second terminal of the one of the MEMS vibrators and the output terminal to each other; a signal reception terminal adapted to receive a switching signal used to switch a state of the connection circuit; and a switching circuit adapted to make the connection circuit switch the MEMS vibrator to be connected to the amplifier circuit based on the switching signal, wherein the MEMS vibrators are housed in an inside of a cavity, and the signal reception terminal is disposed outside the cavity.

Abstract: A voltage-controlled oscillator (VCO) control circuit, used for controlling a VCO to process phase locking procedure after receiving a frequency locking signal, comprises an operating frequency controller and a judgment unit. The operating frequency controller, coupled to the VCO and the judgment unit, generates one of a first control code and a second control code to the VCO. The judgment unit, coupled to an input end of the VCO, generates a phase locking signal according to a voltage control signal inputted to the VCO. When the operating frequency controller receives the frequency locking signal, the operating frequency controller generates a first control code to control the VCO to switch from a first candidate VCO curve to a second candidate VCO curve. When the operating frequency controller receives the phase locking signal, the operating frequency controller generates a second control code to control the VCO to switch from the second candidate VCO curve to the first candidate VCO curve.

Abstract: An apparatus comprising a transconductance control circuit, a boost control circuit, a current computation circuit and an oscillator circuit. The transconductance control circuit may be configured to generate a current control signal in response to (i) a voltage control signal and (ii) a plurality of range control signals. The boost control circuit may be configured to generate a current boost signal in response to a reference current signal and an enable signal. The current computation circuit may be configured to generate a first control signal and a second control signal in response to the current boost signal and the current control signal. The oscillator circuit may be configured to generate an output signal oscillating at a particular frequency in response to the first control signal and the second control signal.

Abstract: An oscillating device is provided that has several oscillators. Each oscillator has a capacitive inductive resonant circuit and a flow-through conduction circuit having a negative flow-through conduction. The inductive elements of the oscillators are mutually coupled. Each oscillator also has short-circuit or not short-circuit the capacitive element of the oscillator. The oscillating device also has a controllable commutating means arranged to activate one oscillator at a time.

Abstract: A circuit includes a controllable oscillator and a controller coupled to the controllable oscillator. The controller is configured to provide a current control and a gain control to the controllable oscillator. The gain control is configured to change a gain of the controllable oscillator during a calibration process.

Abstract: A method and apparatus for compensating for temperature variation in a phase locked loop (PLL) includes receiving an error signal by a controller in which the error signal representative of an instantaneous frequency difference between a reference frequency signal and an output frequency signal of a voltage controlled oscillator of the PLL, and determining when a voltage of the error signal is outside of a predetermined voltage range. When the voltage is outside the predetermined voltage range, the method includes generating a new digital compensation signal based upon a previous digital compensation signal, and converting the new digital compensation signal to be an analog compensation signal. The method further includes filtering the analog compensation signal by a filter to produce a filtered analog compensation signal, and adjusting the output frequency of the voltage controlled oscillator in accordance with the filtered analog compensation signal.

Abstract: An oscillator is provided and includes a resistance unit, a capacitance unit, a first inverter and a second inverter. The resistance unit is serially connected between a first reference point and a second reference point. The capacitance unit is coupled between the first reference point and an output point, and includes capacitors. One terminal of each of the capacitors is coupled to the output point, and the other terminal of each of the capacitors is coupled to the first reference point or a reference ground according to a control signal. The input terminal of the first inverter is coupled to the first reference point, and the output terminal of the first inverter is coupled to the second reference point. The input terminal of the second inverter is coupled to the output terminal of the first inverter, and the output terminal of the second inverter is coupled to the output point.

Abstract: A digitally controlled oscillator is provided. The digitally controlled oscillator includes a pair of transistors cross-coupled to each other, a switched capacitor array coupled to the pair of transistors and a plurality of frequency tracking units coupled to the pair of transistors. The pair of transistors provides an output signal. The switched capacitor array tunes a frequency of the output signal. The frequency tracking units tune the frequency of the output signal to a target frequency. At least one of the frequency tracking units is capable of selectively providing a first capacitance and a second capacitance. A tuning resolution of the frequency tracking unit is determined by a difference between the first and second capacitances.

Abstract: Described embodiments provide a method of calibrating, by a calibration engine, a phase-locked loop (PLL) having one or more adjustable oscillators. The method includes entering a calibration mode of the PLL. The PLL is set to an initial state, thereby selecting one of the adjustable oscillators for calibration, an initial threshold window, and an initial tuning band of the selected adjustable oscillator. If the control signal of the selected adjustable oscillator is not within the initial threshold window, the calibration engine iteratively adjusts at least one of: (i) the selected tuning band of the selected adjustable oscillator, (ii) the selected adjustable oscillator, and (iii) the selected threshold window until the control signal of the selected adjustable oscillator is within the adjusted threshold window. If the control signal is within the threshold window, the one or more calibration settings of the PLL are stored and used to set the PLL operation.

Abstract: A system and method for frequency hopping precalibrates a subset of a plurality of channels, storing the channels' associated curves in a computer readable medium. Before hopping to a new channel, decision making circuitry can access the precalibrated curves. If the destination channel has an associated curve, then the system can use the values from that curve when hopping to a new channel. If the destination channel does not have an associated precalibrated curve, then the system can identify a closely situated channel with a precalibrated curve and use an offset value to settle at the destination channel. According to another aspect of the present invention, the offsets can be updated. According to a further aspect of the invention, the updated can be done dynamically.

Abstract: A voltage-controlled oscillator generates a first signal and a second signal having a phase reverse to that of the first signal. A switch supplies a current signal generated by a first charge pump to a loop filter. A counter counts a cycle number of the second signal included in one cycle period of a reference signal. A second charge pump supplies, to the loop filter, a first current signal having a constant value and a second current signal having a constant value whose polarity is reverse to that of the first current signal. The control circuit controls the switch and the second charge pump based on a comparison between the cycle number of the second signal counted by the counter and a value X.