Abstract: A phase locked loop configured as a frequency multiplier capable of nonintegral feedback path division utilizes a multiphase voltage controlled oscillator (5) which generates a plurality of signals (10a-10f) having a substantially identical frequency but each offset equally from the other by a given phase angle. A commutator (3) selects signals of adjacent phases so as to give the time average output signal (9) a frequency higher or lower than the frequency 10a-10f. Frequency translation is accomplished by periodically selecting signals having a longer or shorter period as desired so that a commutator output signal (9) is delayed or advanced by an appropriate amount. In the preferred embodiment, the phase locked loop is capable of converting a 1.544 MHz signal to a 2.048 MHz signal or vice versa.

Abstract: A method and apparatus for stably maintaining an output clock signal from a phase-locked loop (PLL) frequency multiplier when switching from one clock source to another clock source is described. This method and apparatus maintains the phase relationship between the external signal to the phase detector and the feedback signal from the divider to the phase detector.

Abstract: A digital phase detector comprises a first input for receiving an output of a voltage controlled oscillator and a second input for receiving a reference signal. When a phase of the first input is in advance of that of the second input or when a frequency of the first input is higher than that of the second input, the phase detector operates to output a first control signal for decrease of an oscillation frequency of the voltage controlled oscillator. When the phase of the first input is delayed from that of the second input or when the frequency of the first input is lower than that of the second input, the phase detector operates to output a second control signal for increase of the oscillation frequency of the voltage controlled oscillator. In addition, the phase detector is configured to output neither the first control signal nor the second control signal when both of the first input and the second input are at a low level.

Abstract: A clock formation circuit to form, from a digital signal, a formation clock signal corresponding to a data clock controlling an inversion timing of the digital signal and providing an information signal of the phase difference between the digital signal and the formation clock signal and also providing a formation clock signal having a frequency controlled so as to be coincidental with a data clock frequency of the digital data signal and a phase not offset from that of the digital data signal.

Abstract: An all-digital phase-locked loop (ADPLL) is disclosed having a wide bandwidth while maintaining relatively small steps for phase error correction. A random walk filter with memory and a pattern sensitive phase adjustment circuit cooperate to control the ADPLL frequency/phase adjustment rate by taking multiple, relatively smnall steps in phase error correction at fixed intervals of time. A short cycle occurs when the phase disparity is large, interrupting the execution of the fixed interval cycle expediting the ADPLL phase lock time without sacrificing resolution in the phase error correction steps.

Abstract: A frequency synthesizer phase locked loop includes a voltage controlled oscillator (VCO) providing a variable frequency signal, a reference frequency oscillator providing a reference frequency signal, a phase comparison circuit for comparing the phases of the variable frequency and reference frequency signals and providing an output signal to a loop filter, the output of the loop filter providing a frequency control signal to the VCO. The phase comparison circuit includes a digital phase detector providing an output signal on an output line coupled to a charge pump for providing a first output signal to the loop filter; and an analog phase detector including a sample and hold circuit, and a control circuit responsive to the variable and reference frequency signals for providing a signal for sampling to the sample and hold circuit, the sample and hold circuit providing a second output signal to the loop filter.

Abstract: A frequency synthesizer having a frequency divider and a frequency multiplier in the feedback loop is disclosed. The minimum frequency separation between two adjacent synthesized channels is equal to the reference frequency divided by the multiplication ratio of the multiplier. The division ratio of the frequency divider, which can be analyzed as the sum of an integer and a fractional portion, is varied with time by a digital sequence, resulting in a minimum frequency increment equal to a fraction of the reference frequency. The multiplier acts to reduce the nonlinearities of the frequency synthesizer when the fractional portion of the division ratio causes a large variation in the instantaneous division ratio by reducing the effective division ratio of the loop.

Abstract: In a PLL synthesizer, the tolerance to gain and component variations is greatly reduced when the gain of the loop in increased above that which the loop was initially designed for and if the third order loop symmetric ratio is reduced to a value within the range of 2.0 to 2.5. Higher order loops based on the third order symmetric ratio range have correspondingly lower transmission pole frequency to open unity gain frequency ratios.

Abstract: A phase detector particularly suited for high speed, digital data. The data is auto-correlated with the data shifted through a flip-flop where the flip-flop is clocked by the clocking signal. The data is also delayed by one period by an analog delay line. The output of the flip-flop is auto-correlated with the data and with the data shifted by one period to provide an error signal for a VCO. Ordinary ECL circuits in leaded packages may be employed with data rates in the 300 MHz range.

Abstract: A digital phase locked loop is employed to realize an output clock signal from a reference signal having a frequency which is not an integer multiple of the output clock signal frequency. This is realized by employing a programmable divider for dividing the reference signal which is dynamically controlled by a controllably variable base divisor. The base divisor control is responsive to the reference signal and to a phase error signal. The base divisor is generated to obtain a desired fractional division of the reference signal frequency and in a manner to minimize the amplitude of any resulting "high" frequency jitter in the output clock signal from the loop.

Abstract: The device comprises preprocessing circuitry which deliver to a phase locked loop a preprocessed signal obtained from a replica of the incident digital signal staggered in time by a fraction of the cycle of the clock signal of the phase locked loop. This device then allows a fast synchronization of the clock of the phase locked loop in relation to the incident digital signal, in particular at high transmission rates.

Abstract: An oscillator circuit is tuned to the frequency of reference pulses, for example, the spindle index pulses of a rotating magnetic storage system. A ring oscillator circuit includes a series transmission gate. The transmission gate is controlled by the output signal from a programmable delay line to interrupt operation of the ring oscillator and, in effect, provide fine tuning of the ring oscillator frequency in programmed steps. The output signal of the ring oscillator is divided down in a programmable divider, which provides a coarse frequency adjustment for an output pulse signal provided by the divider. Output signals from the divider are also provided as inputs to the programmable delay line. The frequency of the output pulse signal is compared to the frequency of the reference pulses to generate control signals for the programmable delay line. The control signals are generated by a microprocessor.

Abstract: A slip phase control phase-locked loop includes a voltage-controlled oscillator for generating a frequency signal, and a binary programmable frequency divider for producing a frequency-divided signal in response to the frequency signal supplied thereto, the binary programmable frequency divider including a 2-scale-factor prescaler, a swallow counter, and a main counter. The phase of the frequency-divided signal is compared with the phase of a reference frequency signal. A phase-compared signal is integrated and the integrated signal is applied to the voltage-controlled oscillator. A D/A converter swallow counter and a D/A converter counter are operable with the binary programmable frequency divider for D/A-converting a signal derived from the frequency signal into a pulse-width-modulated signal corresponding to the phase-compared signal at a present count ranging from 0 to 2.sup.M -1, where M is a positive integer.

Abstract: A system for steering mutually phase-locked time-of-day (TOD) clocks in unison to a higher-precision reference clock. Periodically the count stored by a TOD counter responsive to one of the TOD clocks is compared with a reference count to provide an error signal. A proportional correction signal derived from the error signal is applied together with an offset to each of the TOD clocks to adjust the clock frequencies and thereby steer the TOD count toward the reference count. The steering offset is dynamically adjusted in such a manner that, when the offset signal is applied alone as a correction signal, the frequencies of the TOD clocks track that of the reference clock.

Abstract: A fractional-N type frequency synthesizer includes a frequency divider having a selectable integer divide number which is periodically temporarily altered to provide an average rational divide number for the frequency divider. A number of modulator circuits coupled in cascade fashion provide a zero sum modulation signal which varies the value of the frequency divider divisor value such that the net change in divisor value due to the modulation signal is zero thereby reducing phase noise resulting from the temporary altering of the integer divisor value close to the frequency synthesizer carrier frequency.

Abstract: A phase locked loop circuit generates an output clock that is in phase with a reference clock and is frequency jitter compensated at lower frequencies by translating intrinsic jitter frequency from low frequency to a predetermined range of higher frequencies. The phase locked loop circuit utilizes dithering circuitry to control a switched capacitor network in order to reduce the magnitude of the frequency jitter at lower frequencies. A phase detector and a loop filter of the phase locked loop circuit are implemented using digital circuitry. An oscillator of the phase locked loop is an analog oscillator which is digitally controlled and includes the switched capacitor network. Quantization error in the output clock is minimized by switching an LSB weighted capacitor in the oscillator at a frequency established by the dithering circuitry.

Abstract: This invention provides a digital auto-phase-controlled retiming circuit which automatically locates the retiming clock phase in the center of input data eye pattern by detesting the phase difference between retiming clock and data and tracking adoptively the mutual phase variation in a case that the mutual phase difference between data and retiming clock is uncertain and changes according to time in digital transmission and/or digital signal processing systems.

Abstract: A phase-locked loop system having as input a stable refernce clock signal and outputting a master clock signal. The phase of the stable reference clock signal is compared to that of the pre-scaled master clock signal and the difference represented by an analog error signal which is converted to a digital signal by an A/D converter (116). The digital signal is then transformed into an analog control signal by a D/A converter (120) and applied to a VCO (128) which generates the master clock signal, If the stable reference clock signal has degraded or is lost the A/D converter (116), which receives its sampling clock in part from the stable reference clock signal, stops sampling and thus stops producing digital signals. The last good digital signal is maintained, the last good analog control signal is maintained and thus the master clock signal is maintained.

Abstract: A phase-detector circuit for a phase-locked loop clock recovery system detects the phase difference between an information signal and a clock signal and produces a phase error signal representative of the phase difference. The phase detector includes, in one embodiment, five latches, serially interconnected, with the first latch receiving the information signal and each subsequent latch receiving the data output of the previous latch. The latches are enabled, in an alternating pattern, by the high-level and low-level portions of the clock signal. A first exclusive-OR (XOR) gate receives a delayed information signal and the data output of the second latch. A second XOR gate receives the data output of the second latch and the data output of the third latch. A third XOR gate receives the data output of the third latch and the data output of the fourth latch. A fourth XOR gate receives the data output of the fourth latch and the data output of the fifth latch.

Abstract: A synthesizer circuit with spur compensation utilizes fractional division in the synthesizer loop. The fractional divider includes means for compensating the spurs when the fractional numerator N=0. The synthesizer includes means for selecting a reference divisor R such that a non zero value of fractional numerator is produced and such that the generated spurs fall below the side band noise limits of the synthesizer's voltage controlled oscillator.

Abstract: A digital Phase-Locked Loop (PLL), comprising a voltage-controlled oscillator (VCO) and a phase meter including a delay line with taps, wherein phase measurements are effected by sending a pulse through the delay line and determining the location of this pulse in the delay line at the rate of the output signal of the VCO. This location is determined by a processing circuit connected to the taps, which circuit generates in response to the location found a VCO control signal corresponding therewith.

Abstract: A PLL architecture is disclosed which incorporates a coarse adjustment feedback loop and a fine adjustment feedback loop together providing a combined error signal to a single VCO. The coarse adjustment feedback loop includes two digital counters set to divide the VCO output frequency by two different numbers. The outputs of the counters are coupled to the inputs of respective phase-frequency detectors, and the pump-up output of one of the detectors and the pump-down output of the other detector are used as the coarse adjustment pump-up and pump-down signals, respectively, in the coarse adjustment feedback loop. The coarse adjustment feedback loop thereby establishes a frequency range limitation for the fine adjustment feedback loop.

Abstract: A PLL lock indicator circuit for indicating when a phase-lock-loop circuit is in lock includes a gate circuit coupled to the phase/frequency detector of the phase-lock-loop circuit for providing an output logic signal that is responsive to output logic signals from the phase/frequency detector being in a predetermined state. A counter circuit is enabled by the output logic signal of the gate circuit for providing an output logic signal when the counter circuit has reached a predetermined count. A latch circuit is responsive to the output logic signal of the counter circuit for providing a lock signal at an output terminal of the circuit, the lock signal being indicative of when the PLL circuit is in phase lock.

Abstract: A phase locked loop circuit including ramp generating circuitry for generating a dual slope ramp signal having alternating positive and negative slopes that are controlled by the level of the control signal, and sampling circuitry responsive to sample command pulses for providing a sample output representative of the level of the dual ramp signal at the time of sampling. The sample output is provided to a loop which provides the control signal for the ramp generating circuit. Also disclosed is a phase locked loop having ramp generating circuitry for generating a ramp signal, and track and hold circuitry having a plurality of track/hold capacitors that are controlled to track the ramp voltage or hold the ramp signal voltage in response to a sample command signal, such that only a capacitor that is tracking is switched to hold the ramp voltage in response to the sample command signal.

Abstract: Apparatus for synchronizing a clock signal to a pulse comprises a clock signal generator (1) for generating a first clock signal having a frequency equal to that of a desired clock signal. A delay circuit (2) to which the first clock signal is fed generates a number of time delayed versions of the first clock signal, each time delay being less than the period of the first clock signals. Logic (9) compares the time delayed versions of the first clock signal and the original clock signal at the time of occurrence of the pulse and selects as the desired clock signal, a version of the first clock signal which has changed state close to the time of occurence of the pulse.

Abstract: A Phase Locked Loop (PLL) circuit includes a control signal generator, a digital phase detector, logic gates, a charge pump (charge/discharge circuit), a transmission gate, a loop filter, a lead-lag filter and a voltage controlled oscillator (VCO). Outputs of the digital phase detector are coupled through the logic gates to inputs of the charge pump. An output of the charge pump is coupled to the capacitor and to a first input/output of the transmission gate. A second input/output of the transmission gate is coupled to an input of the loop filter whose output is coupled to an input of the VCO whose output is coupled to a first input of the digital phase detector. A second input of the digital phase detector is coupled to a source of a reference frequency signal. The control signal generator generates non-overlapping complementary control signals with one of same connected to the logic gates and the other connected to the transmission gate.

Abstract: In a phase locked loop frequency synthesizer, the frequency of a VCO is switched by changing the division ratio of a variable ratio frequency divider in the feedback path of the loop. At the time of switching, a prepositioning voltage is applied to the VCO to realize fast frequency switching. To correct for nonlinear response of the VCO, the prepositioning voltage is adjusted according to information received from a voltage measuring circuit connected to the VCO control circuit.

Abstract: An additional mixer is included in the feedback loop of a PLL which can be one of the local oscillators of a dual conversion system. A fine tuning frequency synthesizer is coupled to an input of the additional mixer for providing fine frequency control of the PLL. The fine tuning frequency synthesizer can include an additional phase locked loop. Also, a feedback signal for suppressing noise created by another local oscillator can also be applied to the additional mixer.

Abstract: The invention relates to automatic phase adjustment in a phase locked loop including an oscillator (Os) with a controllable frequency. The oscillator generates a timing signal which is used together with a received data signal (1) to form two pulse trains (9,10) which comprise pulses of a duration which in the first pulse train (9) is independent of, and in the second pulse train (10) is responsive to, the phase position of the timing signal relative the phase position of the data signal. The pulse trains are utilized to form a control signal to the oscillator (Os). In forming the pulse trains (9,10) there is utilized a first array of signals (6-8) which are formed by the data signal (1) being sampled in several different phase positions with the aid of mutually phase shifted clock signals (2-4). A rapid locking-in of the phase locked loop is obtained in accordance with the following.

Abstract: A phase locked loop has a phase detector which receives an input signal, a divided output signal from a VCO and a local clock signal, and produces a binary number representing the phase relationship between the input and divided signals. The binary number is applied to a microprocessor which compares it to a predetermined number n and controls the VCO through a D/A converter. To reduce output signal jitter, the microprocessor adjusts the VCO frequency so that the binary number alternates between n and n--1 or between n and n+1.

Abstract: An analog/digital voltage controlled oscillator includes a voltage to pulse converter which responds to a control voltage to generate appropriate control pulses to change the mode of operation of a divider to thereby vary the output frequency of the oscillator.

Abstract: There is provided a phase-locked loop clock circuit being operable in a tracking mode in response to a reference signal and in a sustaining mode in the absence of a reference signal. The circuit provides a relatively stable output clock signal in either of the two modes and permits smooth switchovers from one reference signal to another in a system with multiple reference signals. The circuit further provides a stable output clock if a reference signal temporarily fails.

Abstract: In a serial data communications system, an embedded clock is recovered from a data signal by incrementally controlling the frequency (thus phase) of a voltage-controlled oscillator in response to the difference in phase between the incoming data signal and the clock oscillator output. A transition of the data signal is detected and used to initiate a control pulse which is terminated upon the next transition in the clock oscillator output. A reference pulse is also generated which has a width about equal to a half cycle of the clock. These pulses are used to generate the voltage control for the oscillator, so that the phase relationship varies to see an equilibrium where the pulses are of equal width and the transitions of the clock are at midpoint of potential transitions of the data signal. The control can tolerate relatively long periods where there is no transition of the data signal.

Abstract: A phase locked loop (PLL) with a narrow bandwidth, and small phase noise which is particularly useful in a FM stereo decoder includes both analog and digital circuitry and has the advantages of both types of systems, performing better than standard PLL's without the need for any external components. An externally referenced digital voltage controlled oscillator, establishes the center frequency of the PLL while analog portions of the circuit permits accurate locking to the input signal and provides a high level of quietness of the system.

Abstract: A circuit for high-efficiency tuning of video frequencies comprises a closed control loop including a voltage controlled oscillator, a frequeny divider, a phase comparator, and a low-pass filter cascade interconnected via respective inputs and outputs, with the filter output connected to the oscillator input to form the loop. The circuit further comprises a second comparator connected in parallel to the phase comparator between the frequency divider output and the low-pass filter input to compare a reference frequency to a frequency from the divider when the values of each frequencies lie far apart.

Abstract: A linearized three state phase detector (300) that exhibits a linear transfer function of phase to current or charge at and around the zero phase error region. The inputs to the D flip-flops (301 and 302) are tied to a logic high. the first flip-flop (301) is clocked with reference signal F.sub.r while the other flip-flop (302) is clocked with a variable frequency feedback signal F.sub.v. F.sub.v is typically from a voltage controlled oscillator in a phase locked loop. The outputs of the flip-flops are ANDed together with the result of this operation going through a delay element (304) before reseting one of the flip-flops (301). The other flip-flop (302) is reset by the output of the AND gate (304) without the delay element (304). Each flip-flop output enables a charge pump--one negative polarity (306) and one positive polarity (305).

Abstract: A phase locked loop for extracting an output signal synchronized with an input signal. The present invention is structured so that a phase locked loop can prevent loss of control due to high frequency noise generated by a level conversion circuit in the feedback loop after oscillation of the VCO has stopped due to a failure. The phase locked loop includes an exchange circuit connected between an output of the phase detector and an input to the feedback loop. When the exchange circuit determines that the output of the phase detector is below a reference voltage, it applies a signal having a frequency which is lower than that of the input signal to the phase detector in place of a signal from a frequency divider in the feedback loop. In such a case, the phase detector outputs a pulse signal which restarts oscillation of the VCO and leads to normal phase control operation.

Abstract: A PLL frequency synthesizer IC chip having a sample frequency input terminal, data and address lines and a plurality of different output devices, and a mode control circuit for turning off any selected ones of the different output devices. The mode control circuit comprises a plurality of inputs connected to at least one of the data and address lines for determining different modes of operation, and a plurality of outputs connected to the plurality of different output devices for selecting ones of the plurality of different output devices to allow outputting therefrom and shutting off outputs from all of the remaining different output devices, based on the determined mode of operation.

Abstract: A fully digital phase-locked loop comprises a sampler (1), an analog-to-digital converter (2), two quadrature demodulators (3 and 4) and their associated filters (5 and 6), and a decision logic (7) effecting the correction of the sampling phase around the value of the free-running frequency (f.sub.e) by the addition or subtraction of machine cycles of a signal processor (9).

Abstract: An indirect frequency synthesizer suitable for use in a cellular radio system has finer resolution and reduced spurious frequencies and/or phase noise, which facilitates a large number of channels in a given bandwidth. The synthesizer comprises a phase detector responsive to a reference signal and a phase control signal for generating a control signal that varies in dependence upon the phase difference between the reference signal and the phase control signal. A voltage controlled oscillator responsive to the control signal generates an output signal whose frequency varies in dependence upon the control signal. A variable modulus divider divides the output signal to provide the phase control signal. The variable modulus divider varies its division ratio in dependence upon a ratio control signal derived by a second or higher order sigma-delta modulator in response to a frequency control signal .delta..phi. and to the phase control signal.

Abstract: A differential charge pump for use in a phase locked loop. The charge pump generates a voltage difference signal proportional to the duration of first and second pulse trains provided by a phase comparator. The charge pump includes a differential amplifier for generating the difference signal, first and second RC filter networks connected between the noninverting and inverting terminals of the differential amplifier and a reference node, respectively. Parallel, all-NPN switching networks apply charging current pulses to the first RC filter network in response to the first pulse train and they apply charging current pulses to the second RC filter network in response to the second pulse train.

Abstract: A coherent direct digital waveform synthesizer, capable of generating a waveform in response to a decimally or other non-binary related reference frequency while obtaining the advantages of the use of a binary radix phase accumulator generating binary addresses for a waveform memory. The interface between these elements include a frequency converter including a voltage controlled oscillator and a further binary radix phase accumulator in the feedback path of a phase locked loop. A binary radix related digital waveform synthesizer may be thus made to produce non-binary related frequency waveforms coherent with a non-binary radix reference frequency source, and of decimal or other non-binary radix related resolution.

Abstract: A phase locked loop for providing a programmable frequency output signal with reduced phase-frequency lock time. A phase detector detects a phase difference between a reference frequency divided by a first number, and a frequency of the output signal divided by a second number. First and second counters receive the first and the second input numbers to divide a respective frequency. Whenever an input number is loaded, a load signal resets the phase detector and causes each counter to be loaded, which reduces the lock time of the loop.

Abstract: A digital locked loop which can act as a slave clock. The digital loop is able to monitor a master clock signal and adjust its own output to accurately track the frequency of the master clock signal. In addition, the digital loop can generate a highly accurate timing signal in the absence of the master clock. An oscillator supplies a signal having a fixed frequency to a digital synthesizer. The synthesizer treats the oscillator frequency as a known standard. The synthesizer uses that standard to generate an output signal with a different frequency. The frequency of the output signal is chosen so that it is equal to a frequency supplied by an external master clock. The present invention utilizes a digital feedback loop to detect any phase shift between the output signal and the master clock signal. The presence of any phase shift indicates that the frequency of the master clock signal has changed.

Abstract: A control circuit, particularly for use in a phase-locked loop includes a read-only memory (ROM) having n address inputs divided into two groups, each group being addressed by first (A) and second (B) signals, and the memory device having words preprogrammed therein to provide an output having values (C) of a predetermined function of the first and second signals. In one embodiment the control circuit is employed in a phase-locked loop where one address group provides an analog version of the first signal to a voltage controlled oscillator, and application of the second signal to the second address group permits a step change in the output voltage to the VCO. In another embodiment, the first and second signals may comprise carrier signals and modulating signals in a phase-locked loop employed for frequency modulation.

Abstract: A PLL circuit comprises a phase comparator for inputting input and output clock signals and detecting a difference in phase between these both signals and outputting a signal based on the phase difference; a proportional circuit for converting the output signal based on the phase difference from the phase comparator to a first voltage approximately proportional to the phase difference; an integral circuit for converting the output signal based on the phase difference from one of the phase comparator and the proportional circuit to a second voltage approximately proportional to an integral value of the phase difference; and a voltage-controlled oscillator for inputting the first output voltage from the proportional circuit and the second output voltage from the integral circuit, and generating an output clock signal having a frequency controlled by the first and second output voltages.

Abstract: A circuit for recovering clock information from an incoming data signal preferably in NRZ1 form, the circuit including a VCO (18) providing a clock signal (CK) to four integrate/hold circuits (I1to I4) which receive an incoming data signal, the integrate/hold circuits providing an error signal to the VCO (18) for adjusting the phase thereof to that of the incoming data signal, the integrate/hold circuits being sequenced by logic (10) to provide within each period of the clock signal three functions: (1) an integration of the incoming data signal in every bit period in which a voltage transition occurs, (2) a holding of the integrated value within a subsequent bit period or periods, and (3) a resetting of the integrated value following the next voltage transition in the incoming data signal, whereby the held integrated value, whose magnitude is dependent of the phase of the clock signal relative to the phase of the incoming data signal, provides said error signal.

Abstract: Frequency counter-locked-loop apparatus for controlling digitally programmable oscillators includes an arrangement for locking the output frequency of the oscillator to an accurate frequency reference. Frequency, reference and delay registers, a counter and a comparator are configured in a feedback path from the output of the oscillator to its input for continuous control of the output frequency.

Abstract: A synthesizer is provided to include a phase detector, a loop filter, a current source and two current sinks. The current source and the second current sink selectively supplies current to and from the loop filter, respectively. The first current sink selectively sinks current from the current source. Responsive to signals from the phase detector, a controller actuates the current source on prior to switching at least one of the first and second current sinks.

Abstract: A microprocessor or other integrated circuit including a clock generator circuit which is dependent on an externally-provided reference signal includes the capability of detecting the loss of this externally-provided reference signal and producing an alternate clock signal despite the loss of the reference. In a particular embodiment, the clock generator comprises a phase locked loop frequency synthesizer which normally relies on an external crystal oscillator for its reference frequency signal. The generator includes a circuit for detecting abnormalities in the crystal signal and switching the voltage controlled oscillator of the frequency synthesizer to an internally-generated reference voltage. In the particular embodiment, the clock generator is also capable of producing a reset signal in response to the loss of the reference signal.