Abstract: A constant loop gain phase lock loop for recovering a clock from non-uniformly spaced data pulses utilizes a programmable current source and charge pump whereby the current into the charge pump is proportional to the number of VCO clock periods between data pulses. As the time between pulses increases the current charging the pump increases and when the time between pulses decreases the current charging the pump decreases to maintain a constant loop gain independent of the data pattern.

Abstract: A phase/frequency-locked loop (P/FLL) circuit for generating output signals synchronized with input signals in frequency and phase. The circuit includes a phase comparator which responds to the input signals and to the output signals to develop therefrom phase comparison signals in the form of positive or negative voltages corresponding to the phase differences between the input and output signals. A filtering circuit produces from the phase comparison signals a control signal for a voltage controlled oscillator (VCO) which produces in turn an oscillation signal having a frequency corresponding to the control signal. A phase controller responds to the control signal for the VCO as well as to the output oscillation signal thereof and produces the output signals in a form and wave shape which cause the control signal for the VCO to have a single voltage polarity. The P/FLL circuit of the invention reduces the time required to pull-in the frequency of the VCO and also expands the pull-in range.

Abstract: A monolithic phaselock loop circuit (PLL) for controlling the phase and frequency of a VCO to compensate for process induced variations in the VCO natural frequency and to extend the pull-in range by .+-.50% of the frequency of a reference clock. The PLL is comprised of a VCO, a digital phase comparator, a digital frequency divider and a digital sequential phase error detector (SPED). The SPED circuit comprises two up-down counters, one to control the phase; the other, the frequency; a first one-shot circuit that drives the phase up-down counter to detect every level transition of the reference clock and a second one-shot circuit that drives the frequency up-down counter to provide a pulse for every falling edge of the reference clock; and a shift register responsive to the phase comparator to store the value of the phase comparator thereby providing indication of a frequency lock between the reference clock and the VCO.

Abstract: A PLL synthesizer circuit includes a lowpass filter including capacitors for restricting an output voltage of the lowpass filter, a charge pump circuit for controlling the output voltage of the lowpass filter by charging or discharging the capacitors of the lowpass filter, a voltage controlled oscillator for outputting an output signal having a frequency which is controlled by the output voltage of the lowpass filter, a frequency divider for frequency-dividing the output signal of the voltage controlled oscillator to output a comparison signal and having a variable frequency dividing ratio, a phase comparator for comparing a phase of a reference signal having a predetermined frequency and a phase of the comparison signal output from the frequency divider to output phase error information which indicates a phase lead and a phase lag of the comparison signal with respect to the reference signal, and a charge pump control circuit for forming control information based on the phase error information when switching

Abstract: A fractional-N type frequency synthesizer (700) for use in a radiotelephone (901). The synthesizer (700) utilizes multiple latched accumulators (401, 403, 405, 407), within an accumulator network, to perform multiple integrals of an input signal (439). The outputs of the accumulators are combined in series to form a data output signal (453). The data output signal (453) is input to a divider network (703) and used as a variable divisor of the frequency input from a variable oscillator (701) into the divider network (703).

Abstract: A phase-locked loop having automatic internal phase offset calibration includes a voltage-controlled oscillator circuit for generating a recovered data signal in response to an error signal. A phase detector determines the phase difference between the recovered data signal and a reference data signal. The phase-locked loop further includes a charge pump circuit, coupled to the phase detector, for generating an error signal in response to the detected phase difference. The charge pump circuit includes first and second pump generators for respectively providing first and second sets of pump signals, with the pump generators being interconnected to facilitate generation of the error signal. The phase-locked loop is designed to alternate between operation in phase correction and phase calibration cycles. In each phase correction cycle an error signal is synthesized as described above on the basis of the most recent phase comparison.

Abstract: A charge pump having gate control voltages multiplexed to gates of FET driver circuits to precisely control charge injected by the charge pump to a low pass filter network. Large capacitors between the supply voltages and the respective gate control voltage derived from the particular supply voltage provide greater noise immunity which further reduces phase errors introduced by injected charge variations. The large capacitors help to hold the gate voltages constant, further controlling the injected charge.

Abstract: A phase-locked oscillation circuit system for dividing a clock whose frequency is an integral multiple of a signal produced by dividing the frequency of an input clock. While the input clock to the circuit is shut off, a phase comparator included in the circuit is supplied with a reference signal which is the signal being applied to the compare input of the comparator and the timing of which is modified by a small amount. The system protects the output of a voltage controlled oscillator and, therefore, the output clock of a phase-locked oscillation circuit thereof against disturbances ascribable to the shut-off and recovery of an input clock.

Abstract: A circuit is provided for detecting out-of-lock condition in a phase lock loop. The phase lock loop receives a first signal having a first frequency and a voltage controlled oscillator of the phase lock loop produces a second signal having a second frequency. The circuit comprises a first data flip-flop coupled to the phase lock loop for receiving the first signal and clocked by the second signal. The first flip-flop produces an inverted output of the first signal. A second flip-flop is coupled to the phase lock loop for receiving the second signal clocked by the first signal, and produces a non-inverted output of the second signal. Additionally, an EXCLUSIVE-OR gate is coupled to the first and second flip-flops for receiving the inverted and non-inverted output thereof and producing a signal indicative of an out-of-lock condition.

Abstract: A PLL system having a variable oscillator and apparatus for generating both phase and frequency error signals for controlling the variable oscillator, includes apparatus, responsive to the polarity of the frequency error signal, to selectively disconnect the frequency error signal from the variable oscillator when the PLL system approaches phase lock.

Abstract: A timing recovery loop comprising a multi-point sampling phase comparator 10, a data independent smoothing filter 12, a command sequencer 14, a digitally controlled ring oscillator with clock phase selection 16, a clock divider 18, a sampling clock generation control 20, a bandwidth controlling filter 166, a sequential prioritizer 168, a quarter bit detector 170, and a filter 172. The timing recovery loop has a triple loop structure for improved jitter tolerance and bandwidth control. All three loops share the common components of the ring oscillator 16, the clock divider 18, the sampling clock generation 20, the sampling phase comparator 10, and the command sequencer 14. The remaining components are used among one or more of the loops.

Abstract: A digital PLL circuit has a serial shift register receiving input pulses and producing time-delayed output pulses, a clock generator applying clock pulses to the shift register to drive it and set the phase shift of the output pulses, and a digitally-controlled potentiometer connected in series with the clock generator and being adjustable to change its resistance in increments in order to adjust the resistance of the clock generator and thereby set the frequency of the clock pulses applied to the shift register and the time delay produced by the shift register. A feedback control arrangement receives the same digital input pulses as received by the shift register and detects the periods of the input pulses by counting to produce control pulses proportional to the detected periods. A ROM unit stores a look-up table of values representing an array of different counts of increments by which the potentiometer resistance can be adjusted.

Abstract: A phase locked loop IC comprising a voltage controlled oscillator which generates a clock signal in accordance with a control voltage, a first ECL input buffer which is an input buffer for a signal to be synchronized, a phase-lock capture circuit for producing a current determinative of the control voltage in accordance with the phase difference and the frequency difference between the signal to be synchronized and the clock signal, and a phase-lock follow-up circuit for producing a current determinative of the control voltage in accordance with the phase difference between the clock signal and the signal to be synchronized; wherein the supply voltage system of the first ECL input buffer is so disposed as to be isolated from any of the supply voltage systems of the voltage-controlled oscillator, the phase-lock capture circuit and the phase lock follow-up circuit, while the ground system of the first ECL input buffer is so disposed as to be insolated from any of the ground systems of the voltage-controlled osc

Abstract: A phase detector for a phase locked loop frequency synthesizer, in which frequency-divided signals from a variable frequency oscillator and a reference oscillator are used to trigger respective ramp waveform generators, and a sample pulse generator is arranged to be responsive to the reference ramp waveform to provide sample pulses centered at the mid-point of that ramp waveform to respective sample and hold circuits, the relative phases of the ramp waveforms being determined from the sampled and held voltages.

Abstract: A clock generator (30) dynamically generates a system clock in response to a high or a low frequency oscillator. An amplified oscillator input is provided to a first input of a multiplexor (62), a divider (56), and a comparator circuit (58, 60). Divider (56) divides an oscillator input frequency to provide a divided input to a second input of multiplexor (62). Comparator circuit (58,60) compares the input frequency with a reference frequency to determine whether the input frequency is high or low. If the input frequency is low, multiplexor (62) is enabled to provide the oscillator input as the system clock. If the input frequency is high, multiplexor (62) provides the divided input as the system clock. Additionally, comparator circuit (58,60) provides a control signal to enable an amplifier (50) to amplify the oscillator input using a high or low gain factor in accordance with the input frequency.

Abstract: A system eliminates the adverse effects of serration and equalization pulses (periodically generated during the vertical sync interval) in regulating the frequency of horizontal sync pulses. These sync pulses provide timing information to regulate a video display. The system includes circuitry for stripping and processing the horizontal and vertical sync signals and the serration pulses from the video signals. These pulses are introduced to a first AND gate and through a first display line to an input of a second AND gate. Frequency divider output signals are introduced to the first AND gate and to a third AND gate through a second delay line having an equal delay with the first delay line. The output from the first AND gate passes to second inputs of the second and third AND gates. The second and third AND gates produce signals which represent the time difference between the sync and divider output signals and which have a maximum time difference equal to the delays of the delay lines.

Abstract: A phase lock loop for a sector servo system. A servo phase lock loop oscillator provides the control timing function of the servo. Initially, the PLO is locked in frequency to a frequency reference obtained from a counter/timer in a digital signal processor (DSP) used to control the servo system. Subsequent to acquisition of the nominal operation frequency, the PLO is caused to lock in turn to gap and frame character markers derived from the digital information encoded into the servo burst. Transition between PLO reference sources is commanded by the microprogram running in the DSP, based upon microprogram assessment of servo PLO status. The PLO outputs timing control tags to the servo control logic and PES demodulator, a reference clock to the file read/write channel, and interrupt pulses to the DSP to synchronize DSP operation with the servo hardware, and initiate periodic DSP computation of the control algorithm.

Abstract: The frequency of a local oscillator is maintained within a small frequency window around any one of a number of reference frequencies so that it can lock onto the frequency of an incoming color burst (CHRM). The oscillator (10) may be a current-controlled oscillator. Its control input is switched via a fet (32) to a capacitor (20) charged to a voltage level which will, when connected to the oscillator control input, result in the correct oscillator frequency (Fo). The connection to this capacitor (20) is made when the charge on either one of two control capacitors (22,24) exceeds a threshold value. The threshold values are exceeded when the local oscillator frequency (Fo) is respectively greater than or less than the reference frequency (Fr) by a predetermined frequency difference.

Abstract: Synchronization of a local clock in a transmission system node is achieved by using synchronization circuitry such as a phase-locked loop (PLL). This synchronization circuitry is provided with a selected one of a multiplicity of timing signals derived from incoming bit streams to the node. The selected timing signal is employed by the synchronization circuity as a reference timing signal to which the local clock is synchronized. The timing-signal selection is facilitated by a switch controlled by a process or to relay the timing signal, derived from the most desirable bit stream, to the synchronization circuitry. This processor determines such a bit stream based on various indicators of the signal quality thereof. Moreover, the switch operates at such a speed that the synchronization circuitry is precluded from free-running during any switching period.

Abstract: A phase comparator has a switching circuit controlled by a switch signal and a phase comparing unit. The switching circuit receives a reference pulse signal having a duty ratio of 50% and a reception data signal having a duty ratio of less than 50%. One of these signals is selected by the switching circuit on the basis of control of the switch signal. The selected signal and an output signal from a voltage-controlled oscillator are supplied to the phase comparing unit. The phase comparing unit compares phases of the two signals. When the phase of the output signal from the voltage-controlled oscillator lags behind the phase of the selected reference pulse signal or reception data signal, the phase comparing unit outputs a first pulse signal, having a width corresponding to a phase difference between the two signals, for advancing the phase of the output signal from the voltage-controlled oscillator.

Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

Abstract: An asynchronously resettable counter/divider (25) in a phase-locked loop (PLL) for a frequency synthesizer (12) reduces the lock-up time for the PLL by resetting the resettable counter/divider when the phase difference between the output signal from a VCO (20, 21) and a low frequency reference signal (30) exceeds a predetermined value.

Abstract: An adaptive lock time controller for a phase locked loop having dividers for generating first and second loop timing signals, a phase detector, a voltage controlled oscillator, and a charging circuit for generating at least a first control signal for converging the output frequency to one or more predetermined frequency channels and a second control signal for maintaining the output frequency substantially constant, comprises a synchronization generator, a phase lock detector, and a control signal selector. The synchronization generator is responsive to the phase detector for synchronizing the phase lock detector. The phase lock detector detects phase locked and unlocked conditions by generating a count representative of the phase difference between the first and second loop timing signals. When the count generated exceeds a predetermined count, a phase locked condition exists, otherwise the loop is unlocked.

Abstract: A phase lock detector circuit for detecting the lock state of a phase locked loop (PLL) such that it is known when a synthesized clock has achieved a stable phase relationship with its reference clock signal. The PLL includes an input for receiving the reference signal, a digital phase detector, a voltage controlled oscillator, and a frequency divider. The phase lock detector of the present invention includes a loss of lock detector (LOLD) connected to the frequency divider, the phase detector and the input. The LOLD detects the occurrence of a selected phase difference between the reference signal and an output of the frequency divider for a selected number of cycles. Also included is a gain of lock detector (GOLD) connected to the frequency divider and the input. The GOLD detects the occurrence of the reference signal within a selected phase difference of an output of the frequency divider for a second selected number of cycles.

Abstract: A variable clock delay circuit provides a clock output signal (CLKOUT) whose phase can be varied with respect to an incoming reference signal (REFIN). A voltage controlled ring oscillator (24) having a plurality of delay stages (26-33) locks to a predetermined factor of the frequency of the incoming reference signal. A multiplexer circuit (14) selectively provides a signal (or its inversion thereof) appearing at a selected input of any one of the plurality of delay stages to its output. A divider circuit (16) divides the signal appearing at the output of the multiplexer circuit by the predetermined factor to obtain the clock output signal whose frequency is substantially equal to the frequency of the incoming reference signal and whose phase can be adjusted with respect to the incoming reference signal.

Abstract: A one-shot whose period is a fraction or multiple of the VCO period in a clock recovery circuit. In a clock recovery circuit using PLL, the one-shot is coupled to the PLL in order to enable/disable the phase detector for cases when the data stream does not consist of uniformly spaced pulses. Without a one-shot, the phase detector in the PLL generates a large error signal whenever a clock pulse occurs without a data pulse. During the times when the phase detector is enabled, a phase comparison is made between the next data edge and the next clock edge. When this comparison is completed, the phase detector is disabled again. In order for the PLL to average out the effects of noise and jitter, the phase detector is enabled one half clock period before the data edge. By doing this, the data edge can shift up to one half clock period.

Abstract: A synthesizer including a voltage-controlled oscillator, a phase-frequency comparator, a variable-rank frequency divider, a command device to control the oscillation frequency of the voltage-controlled oscillator on a frequency which is a multiple of the frequency of the reference signal as a function of the rank of division of the variable-rank frequency divider. The phase-frequency comparator circuit sends a first series and a second series of pulses as a function of the phase advance or delay respectively of the signals applied to its first and second inputs, to charge or discharge an integration capacitor and provide a signal commanding the advance or delay of the frequency and phase of the oscillator as a function of the voltage developed at the terminals of the capacitor.

Abstract: A digital oscillator clocked by clock pulses (T) produces an output rectangular wave, the phase of which is controlled by a magnitude supplied to a D register (8'). The most significant bits of that magnitude are derived from the contents of a counter (4) clocked by the output signal (S), while some less significant bits of that magnitude, representing the progression of equal fractions of the period of the output wave are generated by a combination of the undelayed output wave and at least one delayed output wave which combination is stored at intervals of the reference frequency to which the oscillator is locked. That stored combination is converted from a Gray code to a binary code for compatibility with the counter state. The converted additional bits also control a multiplexer which selects the correspondingly delayed reference frequency signal for clocking a D register (15) which is loaded with the counter content and the converted additional bits.

Abstract: A phase lock loop for use in gate array applications with fixed transistors geometries maintains a predetermined phase delay between an input signal and an output signal. The phase comparison cycle operates over multiple periods of the input signal for increasing the operating frequency and simplifying timing considerations throughout the phase lock loop. A phase detector circuit detects a predetermined phase difference between the input signal and the output signal and provides a control signal and a clock signal at different transitions of the input signal. An up/down counter provides a count value migrating within a range of values in response to the control signal at the occurrence of the clock signal. The counter value selects a tap point of a delay line having single inverter resolution for delaying the input signal and maintaining the predetermined phase relationship between the input signal and the output signal of the phase lock loop.

Abstract: A circuit for the regeneration of the clock signal within a message containing a preamble and random data. No assumption as to the message structure is required for the operation of such a circuit. The circuit operates on an autocorrelation principle which allows a voltage controlled oscillator (VCO) which is used to reconstruct the clock signal to operate free of the data format. The device is essentially formed as a phase correlator connected to a feedback loop which contains in series a filter, an amplifier and a voltage controlled oscillator. The correlator is formed by a delay line feeding a delayed data signal to two multipliers. The data is also fed to a shift register, the output of which is also fed to the multipliers. The multiplier outputs are fed to a differentiating element which outputs an error signal which acts as a clock correction signal feeding the VCO which, when necessary, adjusts the VCO output so as to match the clocking within the circuit with the clock timing of the message received.

Abstract: A voltage controlled reference oscillator with a high Q and narrow tunability bandwidth produces an output oscillator frequency which is frequency divided by four alternative constants to produce four different clock frequencies for four different digital video standards, D1 component at 270 MHz, NTSC D2 composite at 143 MHz, PAL D2 composite at 177 MHz, and a proposed new composite video standard that is to operate at a 360 MHz clock rate. Automatic identification of which serial digital video is present is accomplished by having the clock generator produce a clock signal at the frequency required by one of the video formats while a phase lock loop attempts to lock onto the incoming signals at that frequency. If no lock occurs within a predetermined time interval, the clock generator is made to produce a clock signal at the frequency required by a different one of the video formats and the phase lock is attempted again. This is repeated until a lock is attained.

Abstract: A digital phase locked loop system uses a clock signal from an oscillator which is frequency-divided by a frequency divider, thereby causing a phase locked loop clock signal locked to the input signal being produced. At this time, the phase difference between the input signal and the phase locked loop clock signal is computed by a counter. Then, by setting a frequency dividing ratio on the basis of the computed figure, the phase locked loop clock signal from the frequency divider is locked to the input signal. Furthermore, to correspond to fluctuation when the input signal is digitally pulse-width modulated, the pulse width of the input signal is computed by counter on the basis of the clock pulse. The computed figures are converted to the values which match the minimum repeatable frequency of the input signal.

Abstract: A circuit configuration includes a controllable oscillator issuing an output signal. A phase detector is acted upon by a reference signal and by the output signal of the oscillator. A first charge pump is controllable by the phase detector and has an input connected to the phase detector and an output. A loop filter is connected between the first charge pump and the oscillator for triggering the oscillator. A second charge pump is connected parallel to the output of the first charge pump.

Abstract: A phase comparison circuit includes phase comparison device for generating an output signal corresponding to the difference in phase between a first input signal and a second input signal. The phase comparison device has an active mode, and a standby mode in which power consumption is reduced. A phase-difference detecting device is connected to the phase comparison device for outputting a control signal when the phase difference between the first and second input signals is smaller than a predetermined value. The phase comparison device is switched from the standby mode to the active mode in response to the control signal.

Abstract: The charge pump circuit of a phase locked loop has a sensing device, latch and charge pump. When there are contemporaneous up and down signals being produced by the charge pump, a reset signal is provided from the sensing device to a latch which is coupled between the input to the circuit and the pump. Input signals are then inhibited from reaching the charge pump.

Abstract: A latched accumulator fractional-N synthesizer having reduced residual error for use in digital radio transcievers is disclosed. The divisor of the frequency divider (103) of the synthesizer is varied with time by the summation of accumulator carry output digital sequences which result in frequency increments equal to a fraction of the reference frequency. The accumulators (615,617) are latched such that upon the occurrence of a clock pulse, data is transferred through each accumulator one clock pulse step at a time, such that the delay through the system is equal to that of only one accumulator. The latched output of the second highest order accumulator (619) is subtracted from the latched output of the highest order accumulator (621) and differentiated before being applied to the loop filter (109).

Abstract: A monolithically integrated microcomputer clocked at a processor clock rate includes a clock generator in the form of an RC oscillator being synchronizable by external signals for controlling at least one functional unit operating asynchronously with the processor clock rate. The RC oscillator has a frequency-determining resistor and a frequency-determining capacitor being monolithically integrated. The frequency-determining capacitor is formed of a plurality of switchable capacitors to be interconnected to make a total capacitor with a variable size. Registers are each connected to a respective one of the capacitors for defining a switching state of the switchable capacitors. A central processing unit is connected to the registers for adjusting the frequency of the clock generator by setting the registers.

Abstract: In methods and apparatus for aligning the phase of a local clock signal with the phase of a data signal, an incoming data signal is delayed to provide a delayed data signal and regenerated with a local clock signal to provide a regenerated data signal. A difference between the phase of the delayed data signal and the phase of the regenerated data signal is detected. The phase of the local clock signal is retarded by a predetermined fraction of a bit period if the regenerated data signal leads the delayed data signal and is advanced by the predetermined fraction of the bit period if the regenerated data signal lags the delayed data signal. The retiming, detecting, retarding and advancing steps are repeated continuously to obtain and maintain approximate alignment of the phase of the local clock signal with the phase of the delayed data signal. The methods and apparatus are useful in high speed packet switches.

Abstract: A variable frequency signal generator includes a phase locked loop having a variable frequency oscillator which has a control port to which a frequency determining signal is applied, the output of the oscillator being fed via a frequency divider to a phase sensitive detector where it is compared with a reference frequency signal, the result of said comparison being arranged to generate a comparison signal which is fed to a loop filter which is coupled to said control port; and the signal generator having a frequency control signal applied thereto and comprising a first path being arranged to adjust the division ratio of the frequency divider, and a second path including a combiner for combining said frequency control signal and said comparison signal to produce said frequency determining signal; and a calibrator for adjusting the relative characteristics of said first and second paths to compensate for effects arising from tuning sensitivity dependence on frequency of said variable frequency generator.

Abstract: A phase lock loop for use in gate array applications with fixed transistors geometries maintains a predetermined phase delay between an input signal and an output signal. The phase comparison cycle operates over multiple periods of the input signal for increasing the operating frequency and simplifying timing considerations throughout the phase lock loop. A phase detector circuit detects a predetermined phase difference between the input signal and the output signal and provides a control signal and a clock signal at different transitions of the input signal. An up/down counter provides a count value migrating within a range of values in response to the control signal at the occurrence of the clock signal. The counter value selects a tap point of a delay line having signal inverter resolution for delaying the input signal and maintaining the predetermined phase relationship between the input signal and the output signal of the phase lock loop.

Abstract: A fractional-N frequency synthesizer having a programmable divider and a control circuit therefor, wherein said control circuit incorporates a digital delta-sigma modulator operating as an interpolator.

Abstract: In a programmable device wherein a circuit can be designed by programming the device according to a certain design specification, and the circuit is phase or frequency synchronized to an externally supplied signal. The device further allows for redesign by reprogramming the device.

Abstract: A synthesizer is placed in standby mode when a standby portion of a control register is set. Once standby is activated, any detectors and counters are inhibited. The inputs and outputs are reconfigured so as to minimize current drain and to stabilize the VCO control voltage. Recovery from standby is accomplished in two phases. The first phase is started by the receipt of a terminate standby signal. This enables the inputs and starts the counters. The second phase is activated when a signal is received from a feedback counter indicating it has completed a cycle. This causes the preset data to be loaded into the reference counter. The counters are then synchronized; the detector is initialized; and the detector output is enabled. The device also controls an output lock detector and reference frequency signal during the standby mode. The system is also compatible with variable modulus prescalers.

Abstract: A phase-locked loop responsive to both phase and frequency difference between the incoming signal and the feedback signal is provided. Using a reference signal, this phase-locked loop accepts a wide range of frequencies similar to a phase-locked loop having a phase frequency detector, and also achieves the noise performance of a phase-locked loop having only a simple phase detector. In one embodiment, the phase-locked loop is a combination including first and second phase-locked loops. The reference signal is provided to the first phase-locked loop, which includes a phase frequency detector. This first phase-locked loop is used to control a second phase-locked loop, which includes a phase detector. A voltage clamp can also be provided to enhance the ability to lock a signal among several signals, or from a noisy background.

Abstract: A multiple latched accumulator fractional-N synthesizer for use in digital radio transceivers is disclosed. The divisor of the frequency divider (103) of the synthesizer is varied with time by the summation of accumulator carry output digital sequences which result in frequency increments equal to a fraction of the reference frequency. The accumulators (615, 617) are latched such that upon the occurrence of a clock pulse, data is transferred through each accumulator one clock pulse step at a time, such that the delay through the system is equal to that of only one accumulator. The carry outputs of each accumulator are coupled through delays (645, 647, 649, 631, 633) equal to one less delay than the number of accumulators and added (635) such that all higher order accumulator carry outputs add to a net summation of zero so as to not upset the desired fractional setting of the first accumulator.

Abstract: A digitally controlled timing recovery loop is comprised of a digitally controlled Phase Locked Loop (PLL) consisting of a phase detector, loop filter, and voltage controlled oscillator (VCO). The phase detector is a multi-point sampling phase comparator. The loop filter is comprised of a data independent smoothing filter and a command sequencer. The VCO is a digitally controlled ring oscillator with clock phase selection. The timing recovery loop tolerates a relatively large amount of incoming jitter and minimizes data dependent, ISI-induced, intrinsic jitter.

Abstract: The method of the present invention provides fast frequency acquisition in a PLL. The peak voltage for a phase error signal is detected at time t.sub.p and a voltage controlled oscillator warp voltage is sampled at t.sub.p. The new warp voltage to the voltage controlled oscillator is set to what the warp voltage was at t.sub.p. The bandwidth of the loop is then narrowed and the warp voltage is averaged over a number of samples. The warp voltage is then set to the average warp voltage and the loop bandwidth is widened.

Abstract: In a phase locked loop having a variable divider, a dual modulus counter is used to provide the variable divider with selection signals. The variable divider is capable of providing an overall division ratio in increments of one over a contiguous range of values. The dual modulus counter includes a counter, a comparator and logic gates which generate selection signals that allow the variable divider to divide an input signal by at least division ratios R1 and R2. A phase locked loop utilizing the dual modulus counter is particularly well suited for use in a digital frequency synthesizer.

Abstract: A fractional-division synthesizer for a digital transceiver is disclosed in which the fractional divisor may be separated into an integer, N, and a fraction made up of two integers, [n/d]. The integer n is the numerator of the fraction part of the fractional divisor. The integer N is the whole number portion of the fractional divisor. The integer d multiplied by the value of the transceiver channel spacing is algebraically related to the frequency of the reference oscillator. A bit rate clock is also derived from the reference oscillator.

Abstract: A digital phase-locked loop comprises a phase comparator, a controllable oscillator whose output signal is compared with an input signal in the phase comparator, and a loop filter preceding the oscillator. The filter comprises a clocked input register for storing the last phase-measuring value of the phase comparator, and an integrator which comprises a clocked register whose output signal is fed back to the register input. When the input signal of the phase comparator is absent or disturbed, a switching signal is generated which immediately erases the input register in the loop filter and after whose appearance the register in the integrator of the loop filter is reset to zero within a limited number of clock cycles.