Abstract: A phase-locked loop (PLL) frequency synthesizer is connected in reverse to a reference signal and a controlled oscillator loop including a low pass filter and a voltage-controlled oscillator (VCO). Rather than receiving a reference signal through a reference oscillator input and a VCO output signal through a VCO input, the PLL frequency synthesizer receives a reference signal through the VCO input and receives the VCO output signal through the reference oscillator input. Additionally, the output of the PLL is taken from the buffered reference output, thereby eliminating the need for an external buffer. Accordingly, the data loaded into the PLL frequency synthesizer accommodates the reversed input scheme by altering the divide ratios and inverting the phase detector output signal.

Abstract: A digital phase lock loop (DPLL) (10) includes a first comparator (12), a second comparator (14), a third comparator (16), and adjuster (18), feedback divider (20), a threshold unit (21), a digital oscillator (23), and a loop filter (24). The first comparator (12), loop filter (24), digital oscillator (23), and feedback divider (20) of the DPLL (10) operate to produce a controlled oscillation. The second comparator (14), third comparator (16), and adjuster (18) provide a divisor to the feedback divider (20) that allows the DPLL (10) to operate with a variety of unknown system clock (22) frequencies.

Abstract: An autoranging digital/analog (D/A) phase locked loop (PLL) 10 includes a frequency discriminator circuit 12 connected to a shift register 14. Shift register 14 is connected to a voltage controlled oscillator circuit (VCO) 16. VCO 16 is connected to generic counter 17. Counter 17 is optional in this preferred embodiment. Counter 17 is connected to a phase detector 13 and frequency discriminator 12. Phase detector 13 is connected to a charge pump control circuit 15. Charge pump control circuit 15 is also connected to VCO 16. A second generic counter 11 is connected to frequency discriminator 12. Second counter 11 is also optional in this preferred embodiment. First generic counter 17 and second generic counter 11 can be implemented to reduce the phase detector frequency relative to VCO 16 or a reference clock signal frequency. Ratios of M to N allow frequency multiplication or division of VCO 16 relative to the reference clock signal frequency.

Abstract: A phase-locked variable frequency oscillator arrangement includes a voltage controlled oscillator (VCO) which is controlled by a control signal produced by charging or discharging of a capacitor in a charge pump circuit, the charge pump circuit including current sources driven by up or down command signals from a phase detector which detects the phase of the VCO output. When the command signals are simultaneously active, a logic gate circuit supplies a reset pulse to the phase detector via a delay device which is adapted to the rise times of the current in the current sources. The delay device includes a transistor (the "annexed" transistor) which forms a switched pair with one of the transistors which form the current sources. The reset signal is produced when the current of the annexed transistor reaches a selected fraction of its normal current, after being turned on by the logic gate circuit.

Abstract: An apparatus (500) for generating first and second output signals having predetermined frequency shifts relative to a frequency provided by a reference signal is included in a system comprising a phase-locked loop (206) coupled to the reference signal for generating the first and second output signals. The apparatus (500) includes pulse deletion circuitry (204) coupled to the reference signal and the phase-locked loop (206) for deleting pulses from the reference signal at a first deletion rate to generate the first output signal and for deleting pulses from the reference signal at a second deletion rate to generate the second output signal.

Abstract: A lock detection circuit (112) includes a first sampler (113) which samples an input signal (102) at a rate of an output signal (109) to provide a sampled input signal. A second sampler (114) which samples a feedback signal (111) at the rate of the output signal (109) to provide a sampled feedback signal. The sampled input signal is subsequently sampled by a third sampler (115) at the rate of the feedback signal. The sampled feedback signal is subsequently sampled by a fourth sampler (116) at the rate of the input signal. The second sampled input signal and the second sampled feedback signal are subsequently compared (117) and when they substantially match, an indication (122) is set to indicate that phase and/or frequency lock has been obtained.

Abstract: Simplifying measurement equipment so that any two frequency sources can be accurately and quantitatively compared to each other. With this simplified measurement equipment, calibration can be performed on an oscillator using an external reference signal, while the oscillator is being used in an active system. By simplifying the measurement equipment, the equipment can be built into a time base unit allowing recalibration to be performed at relatively short time intervals. A frequency difference detector based on ring counters and an existing controller in a telecommunication switching system compare an accurate external reference against an oscillator of the time base unit for calibration in the field. Within the telecommunication switching system, a highly accurate external reference signal is normally available from an interconnected telecommunication network.

Abstract: A clock circuit for supplying an output clock signal to a logic circuit, includes a phase difference-to-voltage converter producing a voltage signal corresponding to a phase difference between a basic clock signal and a feedback clock signal, a voltage-controlled phase controller controlled by the voltage signal from the phase difference-to-voltage converter and outputting a first clock signal, a clock supply circuit receiving the first clock signal, and supplying a second clock signal, as the output clock signal, through to the logic: circuit, a dummy clock circuit having a dummy capacitance circuit, receiving the first clock signal, and outputting a third clock signal, and a selector selectively supplying the phase difference-to-voltage converter, with a selected one of the output of the clock supply circuit and the output of the dummy clock circuit, as the feedback clock signal.

Abstract: A PLL device includes a VCO (10) forming a phase-locked loop and an amplifier (18) for outputting a phase change signal having phase function with respect to frequencies, a synthesizer (20) having a first input receiving an error signal (phase comparison signal) from a phase comparator (2) through an LPF (4) and a second input for synthesizing signals at the first and second inputs to output a synthetic signal, and a phase and amplitude changer (15) for changing the phase and amplitude of the synthetic signal to provide a phase and amplitude change signal to the second input of the synthesizer in response to the error signal, the synthetic signal acting as an oscillation signal of the VCO (10), whereby the PLL device has a small variation in free-running frequency and a wide lock range.

Abstract: A method and apparatus for generating a controlled output clock signal which is frequency and phase referenced to an input signal is disclosed. The compensation is programmable to allow an external source, such as a processor, to download a compensation factor to create a variable frequency phase locked loop. A separate programmable divider is downloaded with a complimentary value to adjust the varied frequency signal to the frequency of the input signal.

Abstract: In a device for encoding a pulse phase difference or controlling an oscillation frequency based on delayed signals sequentially output by a delay circuit, the encoding of a pulse phase difference or the oscillation control can be simultaneously performed using a single delay device. There is provided a frequency converter including a ring oscillator consisting of inverting circuits interconnected in the form of a ring, a pulse phase difference encoding circuit for encoding the cycle of a reference signal into a binary digital value based on a pulse output by the ring oscillator, an arithmetic circuit for multiplying or dividing the binary digital value by a predetermined value to generate control data and a digitally controlled oscillation circuit for generating a pulse signal in a cycle in accordance with the control data based on the pulse output by the ring oscillator, the ring oscillator being shared by the encoding circuit and oscillation circuit.

Abstract: An array oscillator circuit is disclosed herein. The array oscillator circuit includes a plurality of ring oscillators, each ring oscillator having a plurality of buffer stages for generating output signals on a like plurality of oscillator output ports. Interconnections are provided between each of the plurality of ring oscillators and at least one other of the plurality of ring oscillators such that the plurality of ring oscillators oscillate at identical frequencies and such that the output signals on the each ring oscillator's plurality of oscillator output ports have a phase offset from the signals generated on corresponding ones of the other ring oscillator's oscillator output ports. A multiplexer provides an electrical connection to a selected one of the plurality of oscillator output ports of the plurality of ring oscillators.

Abstract: A method and apparatus for performing, after frequency acquisition, phase acquisition and phase maintenance in a digital phase-locked loop 10. A phase detector (12), determines the phase relation of an oscillator output to a reference clock signal, and provides a control signal to a controller (13), indicative thereof. When a subsequent logic state of the control signal provided by the phase detector is equal to an initial logic state of the control signal, the controller (13) increments or decrements a control value initially corresponding to a baseline frequency of the oscillator by the gain value, based upon the logic state of the control signal. When the control signal changes state, phase-lock has been acquired, and a gain value which determines the magnitude of change of the oscillator frequency is decreased. On every subsequent change in the logic state of the control signal, the gain value is decreased, unless at a minimum.

Abstract: A clock generation circuit includes a reference clock for putting out a stable reference clocking signal. A digital ring oscillator includes a series circuit loop having at least one inverting gate and a programmable delay line of plural delays formed a series of tapped digital transmission gates connected between an output and an input of the inverting gate. A multiplexer selects among the series of taps in accordance with a tap selection signal. A clock monitoring circuit is connected to compare the clock output with a stable reference clocking signal to produce a digital clock cycle count. A programmed microcontroller generates the tap selection value as a function of the digital clock cycle count and a desired clock output frequency set point.

Abstract: A digital phase lock loop for producing an output signal based on an input signal which is subject to jitter and frequency offset. The output signal follows the center of the jitter on the input signal to produce a jitter-filtered signal which compensates for the frequency offset. The digital phase lock loop includes a phase detector, a pulse scaler counter, a phase error counter and a first digitally controlled oscillator. The phase detector detects a phase difference between the input signal and the output signal and outputs up or down pulses depending on the phase difference. The pulse scaler counter increments an up/down counter when an up pulse is received from the phase detector, and decrements the up/down counter when a down pulses is received from the phase detector. When the up/down counter overflow or underflows, a correction pulse is output. The phase error counter resets during every cycle of the input and output signals.

Abstract: A digital decoder for a biphase-mark encoded serial digital signal detects edges in the encoded serial digital signal by sampling with a sample clock to produce a blivet signal. The blivet signal is filtered by a one-bit digital lowpass filter to recover a decoded clock signal and to generate a transition window signal. The blivet and window signals are used to detect whether there is a transition within each bit interval defined by the decoded clock signal. A decoded serial digital signal has a logical one for each bit interval in which a transition occurs, and a logical zero otherwise.

Abstract: A nested digital phase lock loop (DPLL) circuit (400) provides center bit sampling for incoming recovered data (406). Included in the nested DPLL circuit (400) are a narrow bandwidth DPLL (402) and a wide bandwidth DPLL (404) which generate first (410) and second (428) recovered clock signals respectively. Initially the first recovered clock signal (410) is used to clock in the recovered data (406) until the narrowband DPLL (402) is stabilized. Once the narrowband DPLL (402) is stabilized, the second recovered clock signal (428) generated from the wideband DPLL (404) is switched in by a multiplexer (424). If for any reason the center bit sampled data becomes corrupted, a RESET occurs in the wideband loop (404) to zero out the phase shift of the second recovered clock signal (428) to match that of the narrow loop. Thus, when a RESET occurs, the wideband loop is tracking at exactly the same clock rate as the narrowband loop.

Abstract: A phase lock loop frequency synthesizer is applied to radio communication devices or the like, in order to reduce frequency error at a time of frequency changing, and considerably reduce a frequency changing time. At the time of frequency changing, a first loop filter performs frequency coarse adjustment, and charges or discharges a capacitor in a second loop filter to voltage corresponding to target frequency. Further, a controller feeds a voltage controlled oscillator with a frequency fine control data so as to output the target frequency, and controls a loop filter in a phase lock loop to be switched over from the first loop filter to the second loop filter.

Abstract: A frequency synchronous circuit has a first selection unit, a first counter unit, a second counter unit, a storage/average unit, and a comparison unit. The first selection unit is used to select one sampling signal from a first sampling signal having a first sampling time and a second sampling signal having a second sampling time shorter than the first sampling time. The first counter unit is used to count a reference signal supplied from outside the frequency synchronous circuit during the sampling time of the selected one sampling signal, and the second counter unit is used to count a synchronous clock signal to be output from the frequency synchronous circuit during the sampling time of the selected one sampling signal. The storage/average unit, which is operatively connected to the first counter unit, is used to store and average an output signal of the first counter unit.

Abstract: A frequency synchronous circuit has a first counter unit, a second counter unit, a storage/average unit, and a comparison unit. The first counter unit is used to count a reference signal supplied from outside the frequency synchronous circuit during a sampling time which is defined by a sampling signal, and the second counter unit is used to count a synchronous clock signal to be output from the frequency synchronous circuit during the sampling time of the sampling signal. The storage/average unit, which is operatively connected to the first counter unit, is used to store and average an output signal of the first counter unit. The comparison unit, which is connected to the storage/average unit and the second counter unit, is used to compare an output signal of the storage/average unit with an output signal of the second counter unit, and the frequency synchronous circuit outputs the synchronous clock signal whose frequency is synchronized in accordance with an output signal of the comparison unit.

Abstract: A phase-locked loop circuit which utilizes multiple reference signals is formed with control circuitry to minimize time interval error. The phase-locked loop (PLL) comprises a switching device, phase detector, loop filter governable oscillator, frequency divider, signal sensing circuit and a TIE reduction control circuit. The PLL maintains a substantially constant .pi./2 radians between a first reference signal and its phase-locked output. Upon loss of the first reference signal, the signal sensing circuit causes the switching device to switch to a second reference signal. The second reference signal is of the same frequency but unknown phase relationship with the interrupted first reference signal. Upon switch over, the TIE reduction control circuit causes the frequency divider output to be interrupted and forced high for a quarter-cycle of the period of the reference signals to force the PLL to phase-lock on the second reference signal with minimal TIE.

Abstract: A phase detector is described. The phase detector receives a data signal from an external circuit. The phase detector generates a first signal when a transition edge of the dock signal occurs after a transition edge of the data signal. The phase detector generates a second signal when the transition edge of the dock signal occurs before the transition edge of the data signal and generates a third signal when the data signal remains in a same signal state for at least two transition edges of a same type of the dock signal.

Abstract: A frequency synthesizer has the configuration of a phase locked loop (PLL) having a voltage controlled oscillator (VCO) generating an output signal, a phase detector for outputting a control signal to the VCO, and circuitry coupled to an output port the VCO for offsetting the frequency of a sample of the output signal. The synthesizer includes a sampling mixer operative with a source of reference signal and interconnecting the offset circuitry with the phase detector. The sampling mixer mixes the offset sample with the reference signal to output a comb frequency spectrum of signals differing in frequency from each other by multiples of the reference frequency. A filter selects a signal outputted by the sampling mixer at one of the comb frequencies for application to the phase detector. The phase detector is operative with a source of input signal having an input signal frequency for phase locking with the signal selected by the filter.

Abstract: A timing generator contains an oscillator section (10) formed with a plural number of stages (S.sub.1 -S.sub.N) for respectively producing a like number of stage signals (V.sub.S1 -V.sub.SN) that sequentially change signal values at a basic oscillator frequency (f.sub.O). The oscillator section is typically implemented as a ring oscillator. In response to the stage signals, a timing-signal generating section (14) generates one or more timing signals (V.sub.T1 -V.sub.TM), each having at least two transitions corresponding to transitions of two or more of the stage signals. A control section (12), preferably arranged in a phase-locked loop, causes the oscillator frequency and a reference frequency (f.sub.R) to have a substantially fixed relationship.

Abstract: An apparatus and method for improving the performance of a satellite communications modem is disclosed. The invention is particularly applicable to mobile satellite receivers, and includes a variable-gain automatic frequency controlled (AFC) loop, the gain of which is controlled adaptively, based on the AFC lock status and the lock status of the modem's inner loop, in addition to other parameters determined by the invention.

Abstract: This specification concerns signal processing apparatus for processing line synchronization pulses in a line synchronization signal that define an analog video signal line period. The apparatus comprises a phase locked loop (40) for generating a clock signal of a frequency that is a multiple of the line synchronization signal frequency. The phase locked loop (40) comprises a counter (100) for dividing the clock signal by said multiple. The apparatus further comprises logic (110,50) for resetting the counter (100) upon detection of a spurious pulse introducing a time interval into the line synchronization signal of less than the line period of the video signal. The apparatus is particularly useful in image processing systems for digitizing analog video signals that have been replayed via a conventional, domestic video tape player, and therefore may comprise spurious line sync pulses introduced by playback head skip.

Abstract: A phase lock loop (PLL) circuit and method in which a PLL circuit locks on a variable input phase by providing an instantaneous phase value of a signal from an oscillator at periodic intervals, and by providing phase corrective signals to the oscillator at the same periodic intervals by comparing an instantaneous value of the variable phase to the corresponding instantaneous value of the oscillator signal phase, the phase corrective signals adjusting the phase of the oscillator signal to the predetermined phase. The PLL circuit may also lock on a predetermined frequency by providing frequency corrective signals until a difference between the predetermined frequency and the frequency of oscillator signal is smaller than a predetermined threshold.

Abstract: Briefly, in accordance with one embodiment of the invention, an electrical circuit comprises: a digital-controlled oscillator. The digital-controlled oscillator includes an edge delay oscillator being adapted to produce digital oscillator pulses in response to digital clock pulses, each of the oscillator pulses having a rising edge and a falling edge. The edge delay oscillator is further adapted to delay at least one of the oscillator pulse edges in response to a delay signal. In accordance with another embodiment of the invention, an electrical circuit comprises: a digital-controlled oscillator, the oscillator including a clock having a substantially predetermined frequency. The oscillator is adapted to produce a digital output signal comprising a series of digital output pulses.

Abstract: The voltage-controlled oscillator (VCO) of the present invention is designed with reduced sensitivity to power supply voltage variations. The VCO includes multiple inverter stages with dc supply inputs tied to a filtered control dc signal, and a disabling circuit for disabling oscillation. The disabling circuit includes a disabling gate connected to the input to said inverter stages and an enabling gate connecting to the output of the inverter stages for enabling transmission of output from the VCO.

Abstract: A phase detector circuit (10) for generating an analog signal (VR) dependent upon the phase difference between two digital signals (VE, VA) includes two NOR circuits (20, 27) to the inputs (18, 26; 28, 24) of which the two digital signals are supplied on the one hand delayed and negated and on the other directly. The output signals of the NOR circuits (20, 27) control two current sources (S1, S2), one of which in the activated state furnishes a constant charge current (I1) for a storage capacitor (C) whilst the other of which leads a constant discharge current (I2) of equal magnitude away from said storage capacitor (C). The charge voltage at said storage capacitor (C) is an analog signal (VR) which represents a measure of the phase deviation between the digital signals (VE, VA).

Abstract: A multi-marker microwave sweep linearization system comprising a voltage controlled microwave oscillator utilizing an adaptive sweep control circuit is presented. The oscillator control voltage is to be adjusted as necessary to maintain a constant spacing between markers. To produce the markers, the output of the oscillator is mixed with the output at a comb generator having harmonics. The lower side bands generated as the oscillator sweeps past the comb frequencies generates a series of `chirps`, centered about each of the comb harmonics. It will be noted, that the frequency of the chirp passes through zero when the oscillator frequency is exactly equal to one of the comb harmonics. The marker is to be associated with a higher frequency in the chirp envelope to avoid phase uncertainties. This can be accomplished with a frequency-detector circuit which may comprise a retriggerable monostable multi-vibrator having a time constant equal to the period of the frequency to be detected.

Abstract: A frequency multiplier includes a ring oscillator having a number of logic gates arranged in a plurality of rings. Control inputs enable the selection of individual gates so as to connect them into the ring or, conversely, remove them from the ring. As additional gates are removed, the combined delay imposed by the gates remaining in the ring is reduced and the frequency of the oscillator increases. A variable delay element, preferably a group of tri-state inverters connected in parallel, is connected between two of the gates. The oscillator is fine tuned by controlling the delay inserted by the variable delay element. The frequency multiplier also includes a frequency comparator. A reference frequency is passed through a divide-by-K unit and the output of the ring oscillator is passed through a divide-by-N unit, N being greater than K.

Abstract: A PLL circuit comprising a phase comparator unit which forms a differentiation signal based upon both edges of an external signal, outputs an early pulse only during a period in which the differentiation signal is overlapped on a period from the leading edge to the trailing edge of a reference signal, and outputs a late pulse only during a period in which the differentiation signal is overlapped on a period from the trailing edge to the leading edge thereof, a charge pump unit which calculates and compares the amounts of integration of the early pulse and the late pulse, lowers the output voltage when the amount of the late pulse is larger than the amount of the early pulse and raises the output voltage when it is smaller, and a VCO which outputs a corrected reference signal of which the frequency decreases or increases accompanying the increase or decrease in the output voltage of the charge pump unit, wherein the VCO is controlled by the output voltage of the charge pump unit and by the early pulse and the

Abstract: A pro-capture circuit for a phase locked loop detects when the phase locked loop is operating outside of its operating range, and then forces the phase locked loop back into the proper range. The principle of detection is general and may be adapted to work in distinct phase locked loop designs. More particularly, the pro-capture circuit is used in a phase locked loop having a normal operating range in which an output signal of the phase locked loop varies between a minimum normal value and a maximum normal value. The pro-capture circuit includes circuitry for sensing when the output signal is outside the normal operating range and circuitry for forcing the output signal to reenter the normal operating range.

Abstract: A phase-locked-loop (PLL) with stable phase discrimination includes a charge pump with a current source and current sink to control a VCO, and a phase discriminator to compare the VCO's signal to a stable reference signal for controlling the charge pump. The phase discriminator includes a resettable D-flipflop to provide the current source control signal and a resettable D-flipflop to provide the current sink control signal. The reset signal keeps both sink and source temporarily alive to avoid a dead zone region. The reset signal is produced under the combined control of the sink and source control signals and, in addition, of the reference signal to enhance stability.

Abstract: A phase lock loop (PLL) circuit which includes an input for inputting an incoming signal which is to be tracked, a phase lock loop subcircuit, a phase state indicator subcircuit, and a synchronized blanking window generator. These elements create a phase lock loop circuit capable of producing a stable output which closely tracks the incoming signal, even when the incoming signal shifts in phase by 180 degrees. The phase state indicator subcircuit detects a phase reversal in the incoming signal and outputs a signal indication such. This indicating signal is used by the phase lock loop subcircuit to produce a stable reference signal tracking the incoming signal most of the time. However, during a short period of time between the inversion of the incoming signal and the output of the indicating signal by the phase state indicator subcircuit, the synchronized blanking window generator provides a signal to the phase lock loop subcircuit which is used to stabilize the reference signal.

Abstract: A phase lock loop (PLL) arrangement includes a voltage controlled ring oscillator (VCRO) including delay elements whose delay is controlled by a control voltage produced by the PLL. A phase error detector is provided which compares pulses of a PLL feedback frequency with pulses of a delayed reference signal, the delay being provided by further delay elements controlled by the same control voltage. The phase error detector produces an output signal which indicates when phase error exceeds a predetermined tolerance, and also indicates an absence of frequency lock.

Abstract: A fully differential voltage controlled oscillator having a large common mode rejection ratio is disclosed with a first and a second phase detector disposed between the output of a differential comparator and the input of a differential triangle wave generator to insure 180 degree out of phase operation.

Abstract: A phase locked loop (10) has a first (24) and a second (28) feedback path by which a generated clock signal may be phase and frequency matched to an input reference clock signal. The two feedback paths are delay matched so either one may be used to maintain "PLL lock." However, the first path consumes significantly less power than the second path. Control circuitry (22) selects which path is fed back through a multiplexer (126) and disables the second path when the path is not needed.

Abstract: A phase-lock-loop circuit for generating a clock signal at a frequency higher than a horizontal frequency of a video signal includes a phase detector. The phase detector includes a flip-flop that is set when a horizontal sync pulse occurs. An output of a counter that provides frequency division is decoded for resetting the flip-flop in each horizontal period. Other than for the flip-flop, and for the counting stages of the counter, only combinational logic components are used for producing a phase error indicative signal that is coupled via a low-pass filter to a control input of an oscillator of the phase-lock-loop circuit.

Abstract: A phase lock loop (PLL) frequency synthesizer is used in a radiotelephone to provide a reference frequency to a transmitter or a receiver. This particular PLL frequency synthesizer has a wide bandwidth control loop having a high current charge pump (417) and a narrow bandwidth control loop having a low current charge pump (411). A deadzone circuit (413) is used at an output of a phase detector (405) to control the application of an error signal to the high current charge pump (417). Additionally, the PLL frequency synthesizer utilizes a loop filter (419). The loop filter (419) receives two correction signals (409', 415') and provides a single control signal for the VCO (voltage controlled oscillator) (423). The loop filter contains two time constants formed from resistive and capacitive elements. The two time constants control the bandwidth of the two control loops.

Abstract: A fully-symmetric high-speed CMOS frequency synthesizer which exhibits minimum dead-zone effects is disclosed. A fully-symmetric phase-frequency detector and a fully differential charge-pump filter combined with a voltage-controlled oscillator are key elements of the invention described.

Abstract: A digitally controllable oscillator is provided with a variable-frequency ring oscillator including an odd number of inverting circuits connected together in a ring formation. The oscillator has a pulse circulation device to circulate a pulse signal through the inverters to introduce some delay in the signal. Digital data is produced by a data controller device. A counter is connected to the pulse circulation device and counts the number of times the pulse signal circulates through the inverters. A pulse is generated at a desired frequency based upon the counter's output and the introduced delay. A control device determines which of a plurality of delay signals is applied to the circuit that generates the pulse at the desired frequency.

Abstract: A method and apparatus for implementing a constant gain in a digitally-controlled variable oscillator (DCO) 16 where the frequency of the DCO 16 is controlled via binary-weighted control signals. The frequency of the DCO 16 is modulated via arithmetic increments or decrements to the binary-weighted DCO control signals. The magnitude of the arithmetic increments and decrements defines the gain of the DCO. To maintain a constant gain, regardless of operating point or environment, a phase gain register 15 bit-shifts a current DCO control value by a predefined number of bit positions, thereby determining a phase gain value. The phase gain value defines the magnitude of an arithmetic increment or decrement of the current DCO control value, used to determine the next DCO control value. Since the phase gain register 15 uses a bit-shifted version of the current value of the DCO control, the gain value dynamically tracks all updates to the DCO control value, thereby implementing a constant gain in the DCO 16.

Abstract: A skew due to distribution of a clock inside a gate array is reduced. Phase comparators (14A), (14B) and (14C) are prepared in the peripheral portion of an internal circuit 71. The phase comparator (14C) is selected which is located nearest an element (77C) which receives an internal clock signal (65C) which is to be synchronized in terms of phase with an external clock signal (73). The selected phase comparator (14C) is connected to a charge pump circuit (16). Without forming a plurality of PLL circuits except for the phase comparators, the phase of any desired internal clock signal is synchronized with the phase of the external clock signal.

Abstract: The transmitter uses a synthesized oscillator (1A) whose reference (24) is provided by the clock (H) of the data (P, Q). The demodulation oscillator (13A) of the receiver is a synthesizer which is functionally identical to that (1A) of the transmitter, and its reference (23) is provided by the clock (H, 36) recovered from the received data.

Abstract: Frequency generators that may be programmed are utilized in a wide variety of applications. Typical applications include radio and television receivers and transmitters, and computer devices that must operate at different clock rates, or be compatible with systems that operate at different clock rates. The present technique provides for programmably generating a frequency. A ring oscillator receives at least one operating voltage through a programmable array of field effect transistors. Digitally selecting a given set of the transistors provides a given operating current for the ring, which establishes the frequency of operation. In one embodiment, the technique is implemented in a CMOS integrated circuit. This technique provides for more rapid frequency changes in a low-power circuit than can be obtained with typical prior-art techniques (e.g., a phase-locked loop).

Abstract: A PLL based deskewed clock generator which may be fully integrated on a microprocessor is disclosed. The clock generator has a skew of less than 0.1 ns with peak to peak jitter of 0.3 ns using a 0.8 .mu.m CMOS technology. The PLL comprises a phase frequency detector, charge pump, loop filter and voltage controlled oscillator from which the internal clock is generated. Since the PLL is on the same chip as the microprocessor, it is difficult to isolate the PLL from the noise generated by the microprocessor core logic and output buffers. Without an external filter, noise from the motherboard also influences the PLL. Power supply noise can cause a direct change in the frequency of the voltage controlled oscillator of the PLL. Circuits which overcome the adverse effects which would be created by such noises are also described.

Abstract: A digital phase locked loop which incorporates a phase comparator which produces a phase deviation signal having a sinusoidal phase comparison characteristic rather than a sawtooth phase comparison characteristic in order to avoid aliases.

Abstract: A system and method for a computer based system for enabling data phase clock corrections. Basing these corrections primarily on errors that cause consistent phase shift errors while reducing the effect of random data phase errors. An improved phase-locked loop (PLL) is used where multiple data bits are examined simultaneously, allowing us to examine "apparent future" and "apparent late" data. The average phase adjustment to the data window is calculated based upon the examined data bits.