Abstract: A frequency synthesizer and a frequency synthesizing method are disclosed. They are used to achieve frequency switching in a short time even though the switched width of an output frequency signal from the frequency synthesizer is narrow. A gate pulse generator circuit generates a gate pulse signal using a frequency division number data activation signal upon setting the output frequency from the frequency synthesizer. A gate circuit interrupts a reference frequency signal over a predetermined time interval with the aid of the gate pulse signal and thereafter drives a voltage-controlled oscillator to oscillate at a new frequency with the aid of a phase comparator, a charge pump circuit, and a low-pass filter.

Abstract: An oscillator system and method in which a time period (inverse of frequency) of a multi-stage ring oscillator (ROSC) is adjusted by a bias current which controls the charging and discharging times of respective capacitors (e.g., interelectrode capacities) within each stage. The time periods of the unadjusted oscillator are counted along with the time periods of a reference clock over a same period of time and a count difference between the two counts is determined. The count difference is applied by a logic circuit in accordance with an algorithm relating count differences to incremental bias current levels to adjust the frequency of the oscillator. The logic circuit generates digital gate signals corresponding to the count difference and these signals automatically select the bias current level needed to bring the oscillator frequency into close agreement with the reference clock frequency.

Abstract: A high speed clock recovery system that provides a precise 90.degree. phase shift at the incoming NRZ data rate by using a series of differential inverters and controlling their delays in accordance with the corresponding delays of differential inverters of a ring oscillator that is part of a phase-locked loop. More particularly, the incoming NRZ data and the phase shifted data are fed to an exclusive OR that provides an output signal including a frequency component of the originating clock of the NRZ data. The phase-locked loop further includes a phase detector which is responsive to the output of the exclusive OR and the ring oscillator. Thus, once the loop locks, the ring oscillator is synchronized to the frequency of the originating clock for the NRZ data. By slaving the differential inverters of the phase shifter and the ring oscillator to the same delays, the phase shifter provides a dynamically adjusted delay of precisely 90.degree. at the originating clock frequency of the incoming NRZ data.

Abstract: A method of automatically controlling a loop comprising the steps of applying an input signal and an error correction signal to a signal correction circuit to provide a digital corrected signal. Applying the digital corrected signal and a reference signal to an error measurement circuit and providing a difference signal representative of the difference between the corrected signal and the reference signal. Applying the difference signal to a tri-state buffer having an output which is switchable to high impedance and passing the error correction signal to a correction circuit through an integrator and a local generator circuit. The buffer is switched to high impedance when the difference between the error correction signal and the reference signal is zero.

Abstract: Generation of clock waveforms which have a frequency, phase offset, and duty cycle that is relative to a periodic reference signal. The outputs of a voltage controlled ring oscillator are directly applied to drive the inputs of a programmable AND, fixed OR array (PAL) to produce pulses of varied and phase offset and duty cycle. The phase offset has a resolution of one nanosecond. Additionally, the pulses generated can be ORed together within the PAL to produce clock waveforms that are multiples of the input frequency.

Abstract: A radio apparatus with a phase locked loop is disclosed. The apparatus contains a phase detector with first and second inputs, where the first input receiving a reference frequency signal and the second input receives a controllable frequency signal that is controlled by a tuning voltage. Also included is, a loop filter for filtering the output of the phase detector, circuitry for decoding when a phase difference at the inputs of the phase detector exceeds a predetermined value, and a filter bypass circuit. This circuit bypasses operation of the loop filter when the difference at the inputs of the phase detector exceeds a predetermined value, allowing fast voltage changes of the tuning voltage, and providing a short lock time for the phase locked loop.

Abstract: Calibration systems and techniques for phase-locked loops (PLLs) provide precise setting of the center frequency and/or uniform voltage controlled oscillator (VCO) gain characteristics. Center frequency is calibrated by imposing a selected center frequency at the output of the PLL and driving the control voltage V.sub.c across the PLL's filter to a predefined, steady state voltage indicative of PLL circuit calibration. The approach can be employed to calibrate any imposed VCO frequency output. VCO gain calibration is accomplished by employing the center frequency calibration technique only with a low frequency point imposed on the VCO output. A high frequency point on the transfer function is calibrated by applying a known voltage across the filter and driving the VCO output to a corresponding calibration frequency. Once a low frequency point and a high frequency point are calibrated, the slope of the VCO transfer function is defined. Various integrated PLL/calibration system embodiments are presented.

Abstract: A broadband low-gain system for automatically frequency-locking a signal where the system uses digital and analog devices and techniques. The system includes a comparator, an up/down counter, a digital-to-analog converter, a decoder, a ring oscillator and a downcounter. The digital control signal is provided by the decoder and actuates one of a plurality of ring oscillator stages. The analog control signal is provided by the digital-to analog-converter and controls a fine-tune mechanism in the actuated stage. The system includes a master reset for clearing the counters.

Abstract: An all digital phase lock loop (ADPLL), (10) includes a variable digital oscillator (DCO 16), a phase detector (12), a controller (13) including an incrementor (19) and decrementor (21), and a set of oscillator control registers (22). A frequency tracking circuit (20) is separated from the phase acquisition/maintenance logic circuitry. The frequency tracking circuitry (20) uses an anchor value to maintain and update a DCO control value corresponding to a target frequency of operation of the DCO (16). Updates to the anchor value are facilitated by monitoring recent history of an output control signal (ahead or behind) provided by the phase detector (12). The anchor value is changed to maintain the target frequency of operation of the DCO (16), even in the presence of variations in operating environments.

Abstract: A delay matching circuit has a first node (48), a second node (50), a first loading circuit (54, 56), a second loading circuit (58, 60), a third loading circuit (64) and a buffer circuit (62). The first loading circuit couples a first logic state to the first node responsive to a first state of a control signal. The second loading circuit couples a second logic state to the first node responsive to a second state of the control signal. The buffer circuit electrically couples the first and second nodes. The first loading circuit, second loading circuit and buffer circuit are characterized by a first, a second and a third predetermined electrical impedance, respectively. The third loading circuit is coupled to the second node and is characterized by a fourth predetermined electrical impedance. The disclosed delay matching circuit propagates a clock signal input with a delay equal to the Clock-to-Q delay associated with a flip-flop constructed with similar circuit elements.

Abstract: A phase-locked loop circuit includes a voltage controlled oscillator. A phase comparator compares the phase of the output signal of the voltage control led oscillator with a reference signal. A loop filter to which the output signal of the comparator is applied provides a control signal to the voltage controlled oscillator. The voltage controlled oscillator is formed by interconnecting a plurality of oscillator components according to a desired wiring pattern. Each wiring pattern determines the basic oscillation frequency of the voltage controlled oscillator. A loop filter is formed by interconnecting a plurality of loop filter components according to another wiring pattern. Each wiring pattern determining the time constant of the loop filter. The oscillator components, the wiring pattern interconnectors, the comparator, the loop filter components and its wiring pattern interconnectors are disposed on a single substrate.

Abstract: The present invention provides a method and an apparatus for controlling and measuring the phase window of a data separator that is suitable for implementation in an automatic test equipment (ATE) system. The test circuit comprising cross-coupled flip-flops uses the pump up (PU) and pump down (PD) signals produced by a phase detector of a phase-locked loop (PLL) to digitally monitor the phase window. The PLL captures a fixed frequency data pattern provided to the data separator and tracks its frequency. The clock inputs of the cross-coupled flip-flops are driven by the pump up and pump down signals output by the phase detector. Once the PLL has captured the fixed frequency data pattern and settled, a single data bit is shifted from its initial position in the center of the phase window. The single data bit is shifted so that its phase leads or lags its initial position. When the single data bit is shifted in the data pattern, the phase detector correspondingly sets PU high, PD high, or both PU and PD high.

Abstract: A phase locked loop (PLL) (40) simultaneously has both relatively-low power consumption and relatively-low jitter on a clock output signal. The PLL (40) includes a phase detector (41) and a phase error accumulator (42) connected to the output of the phase detector (41). The phase error accumulator (42) samples an output of the phase detector (41) at a relatively-high clock rate, but accumulates these samples and provides an output thereof to a loop filter (43) at a relatively-low clock rate. Thus the PLL (40) captures short periods of phase delay to maintain low clock output signal jitter, while at the same time, however, the loop filter (43) need only adjust its output periodically, at the relatively-low rate, thereby saving power. The phase detector (41) detects a metastable condition on a phase detector latch (60) and resolves to an up pulse or a down pulse to further reduce clock output signal jitter.

Abstract: A method and apparatus for controlling the phase of a system clock, in which one of a first clock signal and a second clock signal is selected and output to a system as a system clock signal, the first clock signal being generated by a frequency synthesizer synchronized with an external clock signal supplied from a reference clock signal oscillator provided externally of the system, and the second clock signal being supplied from another reference clock signal oscillator provided internally of the system, and the phases of the first and second clock signals are controlled, prior to switching between the first and second clock signals and supplying the switched clock signal to the system as the system clock signal. The switching is delayed for a period while there is a phase shift between the first and second clock signal , when the system clock signal is switched between the first and second clock signal.

Abstract: Method and apparatus for controlling a PLL so that handover between fine and coarse loops take place at 2.5% of the nominal VCO frequency and where the coarse and fine loops error are combined in a summer circuit which employs a series circuit having a P-channel and N-channel FET with common drains and where the drains connected to the summer output node.

Abstract: In a PLL frequency synthesizer capable of minimizing power consumption in the power saving operation, there are disposed a voltage controlled oscillator, a phase detector, an active filter, a reference frequency oscillator, a dual modulus prescaler, and a pulse swallow counter having a modulus control terminal. In the power saving operation, the modulus control terminal is set to an inactive state by a controller to prevent power of a power source from being supplied via the pulse swallow counter to the dual modulus prescaler.

Abstract: A power-on reset circuit controls a PLL to prevent overshoot of the VCO during power-up. The power-on reset circuit asserts a control signal upon detecting the power supply potential to the PLL below a predetermined threshold. The control signal enables a pull-down transistor to attenuate the control voltage to the VCO and reduce the output frequency of the VCO. The control signal further blocks the input reference signal to the phase detector. With the input reference signal blocked, the phase detector produces only down pulses to the charge pump during subsequent high to low logic transitions of the feedback signal from the VCO thereby further discharging the loop node and reducing the output frequency of the VCO. Following power-up, the control signal disables the pull-down transistor and allows the input reference signal to reach the phase detector whereby the PLL begins normal frequency acquisition and lock sequencing.

Abstract: A timing circuit having an analog to digital converter to sample an analog signal, a controlled oscillator for controlling sample times of the analog to digital converter, a circuit to detect pulses in the analog signal, a phase error circuit to subtract one of two samples from the other to create a phase error measurement and a frequency error circuit to add two samples together to create a frequency error measurement. The two samples are taken from either side of a pulse. The phase error measurement is used by the controlled oscillator to adjust the sample timing to take samples at desired locations on the pulse. The circuit also contains constant values used to compensate for the pulse being asymmetrical and to compensate for other pulses that occur close to the detected pulse. The circuit also inserts a known frequency in place of the analog signal to establish a frequency of the controlled oscillator.

Abstract: A current sourcing and sinking circuit for driving a charge pump for a voltage-controlled oscillator includes two similar subcircuits, each of which is capable of simultaneously sourcing and sinking output currents. Both subcircuits have identical, corresponding CMOSFET components with two open drain outputs, one of which is a current sourcing output port and the other of which is a current sinking output port. In one subcircuit the current sourcing output port is used while the current sinking output port is terminated drain-to-source with a short circuit. In the other subcircuit the current sinking output port is used while the current sourcing output port is terminated drain-to-source with a short circuit. The similarity of the two subcircuits provides a balanced current sourcing and sinking circuit topology, resulting in substantially equal source and sink current amplitudes and current sourcing and sinking activation timing.

Abstract: A phase-lock loop circuit including a voltage-controlled oscillator for generating a clock signal. The voltage-controlled oscillator includes a plurality of multiplexers coupled in series. The signal generated by the last multiplexer in the series is used as a clock signal. Each of the multiplexers in the series has a select input. Either a first signal or a second signal propagates through the series of multiplexers, depending on a select signal applied to the select inputs of the multiplexers. The second signal is the first signal with a predetermined delay. A 3-input multiplexer is connected to the first and last multiplexers in the series to the form a ring oscillator. The first or second signals output by the last multiplexer in the series is sent to an input of the 3-input multiplexer, and a test signal is sent to a third input of the 3-input multiplexer. The 3-input multiplexer also receives the select signal and a test mode signal.

Abstract: A frequency synthesizer is composed of a reference oscillator, the first and the second integrators, a binary adder, a low pass filter and VCO forming a Phase Locked Loop (PLL). The first integrator, driven by the timing of a reference oscillator, integrates an externally supplied value K and generates the input signal. The second integrator, driven by the output signal of the VCO of the PLL, integrates an externally supplied value L. The binary adder detects the difference between the outputs of the first and the second integrators functioning as a phase comparator. The output of the phase comparator is converted into an analog voltage which is filtered to control the VCO to achieve frequency synthesis by the phase lock function of the loop.

Abstract: A phase locked loop using an oscillating circuit for controlling the frequency by a digital signal according to the present invention comprises a loop filter. The loop filter includes a random walk filter 3, a counter 4, a register 5 and an adder 6. The oscillating circuit 7 emits a signal having a frequency corresponding to the output of the adder 6. Further, a phase/frequency detector 2 emits a phase lag signal LAG and a phase lead signal LEAD according to the phase difference between a signal IN provided to an input terminal 1 and a signal REF provided from the oscillating circuit 7 to thereby increase the degree of freedom for determining a loop constant while avoiding generation of the steady phase error relative to the frequency offset.

Abstract: A PLL is integrated on the same chip as a programmable logic circuit and interconnected therewith in any of several useful ways. In one aspect of the invention, the output frequency of the PLL may be connected to the clock input of registers in the programmable logic circuit. If the PLL performs frequency multiplication, the chip then becomes a high-speed state machine synchronized to a lower-frequency input clock. In another aspect of the invention, the signal present at different parts of the phase lock loop may be provided to inputs of the programmable logic circuit. In another aspect, outputs of the programmable logic circuit may be used to control the operation and/or characteristics of various components in the PLL. For example, if a counter is included in the phase lock loop for causing the loop to generate a frequency multiple of the input signal, the counter may be made programmable according to outputs of the state machine.

Abstract: A voltage controlled oscillator (VCO) operating as a variable length, variable delay, ring oscillator having a current starved inverter and an anti high-gain circuit for each stage. A VCO feedback signal is compared with a reference frequency obtained, for example, from a system crystal oscillator. A phase and frequency detector monitors these two input signals and issues "up" or "down" commands to a digital counter. This digital counter delivers select signals via a decoder and also drives a Digital to Analog Converter ("DAC"). The digital select signal from the counter chooses an operational stage from the multi-stage, tandem-connected VCO. A broadband operation for the VCO is achieved by overlapping the individual frequency ranges associated with each of the individual stages. The DAC moves the operation along each selected frequency range associated with a selected stage until a system lock between the VCO output and the crystal references is achieved.

Abstract: A phase locked loop (PLL) is disclosed, which produces a source clock signal which has a frequency twice that of a reference clock signal fed from the outside and is in synchronism with a reference clock signal. A timer counts pulses of a reference clock signal in order to measure time corresponding to the lock-in time of the PLL and delivers a count completion signal when the value of counting reaches a predetermined value. A start controller is in control of a clock buffer so that, after a count completion signal is delivered, the clock buffer starts feeding a source clock signal to a load circuit as an internal clock signal, in synchronism with a reference clock signal. A stop controller is also in control of the clock buffer so that, when a clock stop request signal becomes asserted, the clock buffer stops feeding an internal clock signal, in synchronism with a reference clock signal.

Abstract: A digital phase lock loop is provided, comprising a digital voltage controlled oscillator, a phase detector, and an up/down counter. The digital voltage controlled oscillator is responsive to a first set of control signals received from the up/down counter to provide an output signal. The phase detector receives and compares the frequency of the output signal with the frequency of a reference signal and, based on the comparison, outputs to the up/down counter a second control signal which determines the status of the first set of control signals. The digital voltage controlled oscillator comprises (i) an array of delay elements and (ii) a decoder for receiving the first set of the control signals from the up/down counter and for selectively activating one or more of the delay elements in response thereto. The decoder provides a separate output line for each of the delay elements which is to be selectively activated.

Abstract: An embodiment of the present invention is a retriggered oscillator timebase including a phase lock loop controlled ring for direct retriggering by a reference oscillator. The ring has taps at various successive stages that are output to an on-the-fly selector that can add any ten-bit value to a current-tap selection to enable a next-tap selection. Such on-the-fly addition can increase the period of a signal each cycle and thereby divide the reference frequency. Ring outputs are also used to drive two other retriggered rings for a plurality of NANO timing generators. The use of two rings allows retriggering of one of the rings before the other has completed a whole one-shot cycle. An on-the-fly selector subtracts a value from a present "NANO" select to a next "NANO" select to convert back the timebase to the fixed reference frequency for phase and frequency comparison. The subtraction acts as a frequency multiplication whose output "t.sub.0fx " is equal to the reference frequency.

Abstract: A frequency locked loop includes a phase comparator receiving first and second periodic signals and having a first output providing pulses if the first signal is in phase advance with respect to the second signal and a second output providing pulses in the opposite case; an oscillator providing the second signal; a counter, the state of which determines the frequency of the oscillator, having an incrementation input and a decrementation input; and a sampling circuit for transmitting each Nth of the pulses either to the incrementation input if the pulse occurs at one of the first and second outputs of the comparator, or to the decrementation input if the pulse occurs at the other of the first and second outputs.

Abstract: A phase-locking oscillator circuit having improved phase noise characteristics is disclosed herein. The oscillator circuit includes a tuned oscillator for providing a carrier signal at a tunable carrier frequency. The carrier signal is applied to an input port of a phase modulator operative to impress an RF signal upon output terminal. An error detection and feedback network generates an error signal by comparing a predefined characteristic of the RF output signal to a reference signal. The network includes a loop filter arrangement which operates upon the error signal so as to provide a tuned oscillator tuning signal to a tuning port of the tuned oscillator and a modulator control signal to a control port of the phase modulator. In an exemplary implementation the error detection and feedback network includes a phase detector for generating the error signal in response to the phase difference between the RF output signal and the reference signal.

Abstract: A phase locked loop (20) includes a standby control circuit (30) and recovers from standby with minimum lock time. A reference counter (21), a loop counter portion (22, 23) and a phase detector (24) are disabled in response to an activation of a standby signal. Both the reference counter (21) and the loop counter portion (22, 23) are enabled in response to a deactivation of the standby signal. A voltage controlled oscillator (VCO) (26) output signal is decoupled from an input of the loop counter portion (22, 23) in response to an activation of a loop counter output signal. The VCO output signal is next recoupled to the input of the loop counter portion (22, 23) in response to an activation of a reference counter output signal. Finally, the phase detector (24) is enabled. In one embodiment, the loop counter portion (22, 23) includes a prescaler (22) which does not have a separate reset input, and a separate loop counter (23).

Abstract: Frequency divider and multiplier circuits are provided comprising a voltage controlled oscillator, a presteer circuit comprising a frequency comparator, a sampling phase detector circuit comprising a sampler, a pair of prescalers for providing frequencies in the divider/multiplier circuits by a predetermined number D, a programmable divider for dividing one of the frequencies in the divider/multiplier circuits by a selectable N and a summing circuit. In operation, the presteer circuit drives the VCO toward a predetermined frequency. When the VCO reaches a predetermined frequency, the output of the presteer circuit is disabled and the sampling phase detector takes over, locking the VCO to the predetermined desired frequency.

Abstract: An integrated circuit for detecting harmonic lock of a phase-locked loop includes a frequency synthesizer for receiving a reference clock signal and for generating an oscillator clock signal. A phase generator receives the oscillator clock signal and generates a phase of the oscillator clock signal. A shift register receives as an input the reference clock signal and is clocked by the phase of the oscillator clock signal to produce an output that is a repetitive sequence of logic states. In an alternate embodiment, a harmonic decode circuit decodes the shift register output to determine which harmonic the phase-locked loop has locked onto.

Abstract: A phase lock loop comprises a voltage controlled oscillator, a phase detector and a loop filter comprising a charge pump and a filter network. The voltage controlled oscillator generates an output signal having a frequency which is responsive to a control voltage. The phase detector is responsive to the output signal and to a reference signal to generate a control signal indicative of a phase difference of the output signal and the reference signal. The charge pump is responsive to the control signal and to the control voltage to apply a charge indicative of both the phase difference and the control voltage to the filter network to develop the control voltage. Because the charge supplied by the charge pump depends on the control voltage as well as the phase difference of the output signal and the reference signal, the rate of adjustment of the output signal frequency depends on the present output signal frequency.

Abstract: A phase locked loop including a switch between a phase detector output and a VCO input to open the PLL during a frequency change is provided. While the PLL is open, an analog error correction signal is generated by sampling any residual error coming from the phase detector, and generating the analog error correction signal to counter the residual error. Once analog error correction signal is available, the switch is closed and the error correction signal is added to the phase detector output and the PLL is allowed to settle to an optimized frequency.

Abstract: A digitally controllable oscillator is provided with a variable-frequency ring oscillator comprising an odd number of inverting circuits connected to each other in a ring. The frequency of the output signal of the ring oscillator is determined by a digital input signal specifying the frequency of the output signal of the ring oscillator. The number of times of circulation of a pulse signal through the ring oscillator is counted. A pulse generator generates a pulse signal upon the coincidence of the counted number of times of circulation of the pulse signal through the ring oscillator with a number corresponding to the digital input signal. A series of these operations is repeated to make the pulse generator generate pulse signals successively at a period corresponding to the digital input signal.

Abstract: An autoranging phase-lock-loop circuit compares an oscillator signal output from a range programmable voltage controlled oscillator, which generates the oscillator frequency within one of a plurality of operating ranges, to a reference signal and commands the voltage controlled oscillator to step to a next operating range if the voltage controlled oscillator cannot lock onto the reference signal within a prescribed time.

Abstract: A television receiver is subject to certain operational conditions which result in poor, unreliable or unusable separated sync pulse signals. During such conditions the use of unsuitable sync signals for synchronization and the like is inhibited to prevent mis-triggering or spurious synchronization. A television receiver contains circuitry for extracting a sync signal, a voltage controlled oscillator (VCO) for generating a scanning signal, and a comparator comparing the scanning signal to the separated sync signal. A microprocessor is used to verify the separate sync signal for invalid or unusable signals and has an output activated during such conditions. The phase comparator has a current output coupled to a integrating capacitor or LPF which develops a varying positive or negative voltage to raise or lower the frequency of the VCO for scanning in phase with the separated sync.

Abstract: A circuit and method for generating drive signals having a frequency synchronized to a reference frequency signal is disclosed. The circuit includes a PLL that includes a motor, and a circuit for generating a signal having a frequency proportional to the speed of the motor. A phase detector produces a signal for a time proportional to a phase difference between the motor speed signal and a reference frequency signal. A first phase difference measuring circuit produces a first voltage output signal at a first gain proportional to the phase difference when the duration of the phase detector signal is less than a predetermined time. A second phase difference measuring circuit produces a second output signal at a second gain when the duration of the phase detector signal is greater than the predetermined time. The first and second output signals are summed and applied to control the speed of the motor.

Abstract: A semiconductor integrated circuit having a clock signal generator comprising a ring oscillator, a divider, a phase comparator, and an up-down counter. The ring oscillator provides variable oscillation frequencies determined by a sum of the delay times provided by the circuit elements constituting the oscillator. The divider divides the oscillation frequency from the ring oscillator by a specified number. The phase comparator compares the frequency of the signal from the divider with the frequency of the external clock signal. The up-down counter controls the oscillation frequency of the ring oscillator by selectively operating switches connected with the ring oscillator based on the comparison result from the comparator. The clock generator is controlled by an external clock signal to generate an internal clock signal having a higher frequency and outputs both signals.

Abstract: A lock detection circuit (2) for a phase lock loop (PLL) for detecting when a signal generated by the PLL is substantially locked to a reference signal (REFERENCE). The lock detection circuit includes a circuit for generating first (UP) and second (DOWN) pulses, the first and second pulses respectively representing positive and negative differences between a parameter, such as phase, of the PLL signal and a parameter of the reference signal, and a first counter (4) for counting sets of first and second, pulses, each set comprising a first pulse followed by a second pulse, the first counter on counting a predetermined number of sets of pulses providing a first count complete signal.

Abstract: The frequency control and phase control of a voltage-controlled oscillator (50) of a phase-locked loop (100) comprise two current paths. The frequency control system comprises a filter (75) that converts pulse output current (i.sub.1) of a charge pump (70) generated by phase error signals (X.sub.1, X.sub.2) to a DC voltage, and a resistor (R.sub.1 or R.sub.2) that converts that voltage to DC current (i.sub.3), and the phase control system comprises a charge pump (80) that generates a pulse output current (i.sub.2) using the phase error signals (X.sub.1, X.sub.2). The frequency and phase of the oscillator output (V.sub.OUT) of the voltage-controlled oscillator (50) is controlled by a composite current i.sub.4, which is the sum of the DC current (i.sub.3) and the output current i.sub.2. Since it is possible to make the natural angular frequency proportional to the data transfer rate while the damping factor remains unchanged, by changing the value of the currents (i.sub.3, i.sub.

Abstract: A digital PLL circuit capable of stabilizing a phase comparison operation to largely reduce a jitter of an output signal, including a peak detection circuit for detecting a peak of an input signal level, a two-points sampling circuit for sampling two data points determined at a predetermined time interval in the peak to output two sample values, an inclination calculation circuit for calculating an inclination value from the two sample values, and a discrimination circuit for discriminating whether the inclination value is zero or either a positive or negative value to output a control signal for a VCO depending on the discrimination result.

Abstract: A phase locked loop system including first and second counters connected respectively to first and second registers. The first register contains a number M and the second register contains a number N. The first counter is responsive to a reference signal Fref and the second counter is responsive to an output signal Fout. The first counter provides an output signal F1 responsive to M cycles of Fref and the second counter provides an output signal F2 responsive to N cycles of Fout. The F1, F2, Fref and Fout signals are connected to a phase detection circuit where the phases of Fref and Fout are compared under the control of the larger states of F1 and F2. The output signal of the phase detection circuit is connected to a voltage controlled oscillator that produces the output signal Fout proportional to the phase detection circuit output signal. The Fout signal is looped back to the second counter until the phase locked loop system settles when Fref/M equals Fout/N.

Abstract: The loop gain of a phase locked loop is made to be controllably responsive to the transition density of an input data signal. In one embodiment a charge pump, positioned between the phase detector and the loop filter, supplies pulse-amplitude-modulated current pulses to the loop filter, the amplitude of pulses being related to the data transition density.

Abstract: A phase-locked loop according to the present invention includes first and second frequency demultipliers, and a plurality of phase/frequency detectors. The first and second frequency demultipliers divide frequency of first and second signals by a predetermined number. Each of the plurality of phase/frequency detectors compares two signals supplied from the first and second frequency demultipliers. In accordance with a comparison result of the plurality of phase/frequency detectors, phase of the second signal is adjusted to be synchronized with the first signal.

Abstract: A phase-locked loop is provided for operating in either a steady-state mode or a transient mode. The steady-state mode obtains high rejection of noise disturbances to maintain lock of the phase-locked loop. The transient mode provides a near deadbeat response in order to quickly acquire a new phase-locked loop frequency when a new frequency command is received.

Abstract: An embodiment of the present invention is a single-chip GPS receiver front-end comprising a radio frequency amplifier, a voltage-controlled oscillator operating at a first local oscillator frequency, a divide by seven and one-half counter for deriving a second local oscillator frequency from the first and a first and second mixer. The local oscillator frequency is mid-way between two carrier frequencies of interest that may be received by the radio frequency amplifier and the first mixer produces a first intermediate frequency. The second local oscillator frequency is then beat with the first intermediate frequency in the second mixer to produce a second intermediate frequency. A dual-conversion super heterodyne configuration is therefore employed in which the first and second local oscillator frequencies are derived from a single oscillator and the first local oscillator frequency is seven and one-half times the second local oscillator frequency.

Abstract: A dual-mode detector which has phase-detection and phase-and-frequency-detection modes of operation, each mode of operation having the same gain. The detector includes a detection and feedback circuit for detecting phase and frequency differences, and for generating first and second feedback signals for controlling the voltage-controlled oscillator in response to the phase and frequency differences. A mode-switching circuit switches the detection and feedback circuit between the phase-detection and the phase-and-frequency-detection modes of operation. A programmable delay circuit delays signals from the mode-switching circuit and provides delayed signals to the detection and feedback circuit. Finally, an optional edge detection circuit converts predetermined data signals to a format recognizable by the detection and feedback circuit.

Abstract: A low noise frequency synthesizer 10 that uses uses frequency dividers 13, 15, at least one of which(divider 15) is incrementable and decrementable in half integer steps, and analog gain compensation in a phase/frequency detector 14 to achieve lower noise, lower spurious levels and faster switching speed than traditional methods of frequency synthesis. The key features of the present invention are its half integer dividers 13, 15 and the ability to adjust the phase detector gain to compensate the loop for varying divide numbers. The synthesizer 10 comprises two dividers 13, 15 that provide two reference frequency signals that are a function of an input signal and an output signal of the synthesizer 10. A voltage controlled oscillator (VCO) 18 provides the output signal (f.sub.O) of the frequency synthesizer 10. A phase/frequency detector 14 compares the reference frequency signals and provides a phase error output signal that drives the VCO 18.

Abstract: A phase lock loop operates independent of temperature and process variation by digitally loading a VCO until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit sets the loop node voltage to V.sub.DD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector monitors the output frequency of the VCO and passes control signals to a load control circuit to activate digital loads and slow down the VCO to the desired operating frequency.