Abstract: Phase-locked loop oscillators that are designed to set the clock rate of electronic circuits based on combinations of logic circuits and to be integrated, at the same time as these electronic circuits, into one and the same chip. There is proposed a phase-locked loop oscillator based purely on combinations of logic circuits so as not to make use of integration techniques different from those used for the electronic circuits based on combinations of logic circuits, for which they are designed to set the clock rate.

Abstract: A phase lock loop circuit for a digital radio generates the sampling frequency for sampling an incoming signal by storing the samples of the incoming signal in an accumulator at a first frequency. The accumulator is unloaded at the sampling frequency. A microprocessor monitors the rate in which the samples are stored in the accumulator and provides a switching signal to vary the sampling frequency in small increments to prevent the accumulator from overflowing or underflowing.

Abstract: A phase locked loop (PLL) circuit is described which uses a Schmitt trigger block (28) to achieve a very small steady state phase error at an input of a phase comparator block (21) over the entire PLL lock voltage range. The amount of hysteresis which each Schmitt trigger circuit (281, 282) in the Schmitt trigger block (28) has depends on the damping factor .zeta. of the PLL circuit as well as the temperature and voltage coefficients of a VCO's input voltage. The midpoint of the positive and the negative thresholds of the hysteresis curve of each Schmitt trigger circuit (281, 282) is set by the current voltage characteristics of charge pump circuits in a charge pump block (22). Responsive to the PLL's lock voltage (VCNT), the Schmitt trigger block (28) commands a control logic circuit (29) to turn ON or turn OFF as the case may be PMOS pump UP transistors to that of NMOS pump DOWN transistors. It is this ratio which determines the PLL's steady state phase error.

Abstract: In a PLL circuit used in a display monitor, it is made possible to design a PLL circuit using a VCO of excellent frequency stability. In this PLL circuit, low jitter of display monitor is realized without having to consider variations of oscillation frequency of VCO practically. It solves the problems of effects of variations of oscillation frequency on the cost and productivity. This PLL circuit preliminarily detects the range of frequency dividing range of the frequency dividing ratio of the dividing circuit capable of locking the PLL circuit with respect to the input signal with known frequency by frequency detecting means. The detected frequency data is stored in the memory. On the basis of the frequency data, the frequency dividing ratio of the dividing circuit is set. By this setting, even if different input signals are entered, the VCO operates at a frequency near the center of the variable range of the oscillation frequency.

Abstract: Method and circuit aspects for improving lock-in time following power-up in a phase-locked loop are provided. The circuit and method for providing same includes a phase-locked loop, the phase-locked loop comprising a low pass filter, and a pulse generation circuit coupled to the low pass filter. The pulse generation circuit provides a control pulse of predetermined duration to increase a voltage across the low pass filter and reduce lock-in time in the phase-locked loop following power-up. The pulse generation circuit further includes a plurality of logic gates, the plurality of logic gates including a plurality of inverters coupled to a NAND gate.

Abstract: A prescaler which can be used in a PLL includes a counter section and an extender section. The counter section has a pair of staged, synchronous flip-flops which generate a frequency divided signal by frequency dividing an input oscillation signal by either two or three. The extender section has a plurality of staged, asynchronous flip-flops which generates a second frequency divided signal. A switching circuit connected between the extender section and the counter section controls whether the counter section operates as either a binary counter or a ternary counter. Power conservation is achieved by limiting the counter section to only a pair of flip-flops.

Abstract: Charge pump steering systems and methods force a charge pump of a loop filter of a phase locked loop to charge or discharge a capacitor for a predetermined time that it is independent of the phase detector error signal. Thereafter, the charge pump is activated in response to a phase detector error signal. Accordingly, rather than relying on the error signal to activate a charge pump, the charge pump may be activated for a period of time which will add or remove a requisite amount of charge to or from the loop filter. Decreased lock times can thereby be produced while allowing a reduction of the size and cost of the charge pump. The invention is preferably applied to an integral charge pump in a phase locked loop.

Abstract: A digitally-controlled oscillator (DCO) (60), such as may be used in clock generator or clock recovery circuitry in an integrated circuit, is disclosed. The disclosed DCO (60) is a single-stage oscillator including a variable load implemented as a binary-weighted array of switched capacitors (40). Each of capacitors (40) has a plate connected to a common node (X), and a plate that receives a signal corresponding to one bit of a digital control word (DCOCW). The common capacitor node (X) is also connected to the input of a Schmitt trigger (42) that produces the output clock signal (OUTCLK) and a feedback signal that is applied to logic (38, 39) that inverts the common node of the capacitors (40). The switching time at the input of Schmitt trigger (42) depends upon the variable load presented by the array of switched capacitors (40), which is controlled by the digital control word (DCOCW). As a result, the clock signal (OUTCLK) is digitally synthesized by a single stage of the DCO (60).

Abstract: A signal processor utilizes a globally nonlinearly coupled array of nonlinear dynamic elements. In one embodiment of the invention, these elements take the form of bistable overdamped oscillators. The processor exploits the phenomenon of stochastic resonance to amplify a weak periodic signal embedded in noise. In this signal processor, a system or plurality of nonlinearly coupled overdamped oscillators is subject to a weak periodic signal embedded in a noise background. For communication or detection applications, this weak signal component is the signal of interest. A reference oscillator is chosen from the plurality of overdamped oscillators, and is given a time scale for relaxation that is longer than the remaining oscillators. The output of the reference oscillator is analyzed for signal processing purposes in response to the signal and noise.

Abstract: A phase locked loop is described which uses a first and second voltage-controlled oscillator. The first voltage-controlled oscillator is input into a feedback circuit which is used to produce a control signal. The control signal runs both the first and second voltage-controlled oscillators. A synchronization circuit is used to synchronize the first voltage-controlled oscillator with the synchronization pulse. In one embodiment, the synchronization circuit can use the second voltage-controlled oscillator to produce a timing interval to control the turning on and off of the second voltage-controlled oscillator in order to facilitate this synchronization. Because the output of the first voltage-controlled oscillator is sent to the feedback, the output of the phase locked loop will not drift due to parameter differences between the first and second voltage-controlled oscillators.

Abstract: The present invention provides a reliable method for oscillating an oscillator having an oscillator output without fail. The method includes steps of detecting whether the oscillator is regularly oscillating, and releasing the oscillator to oscillate when the oscillator is regularly oscillating, and holding the oscillator from oscillating until an enough control voltage is built-up therefor when the oscillator is not regularly oscillating. The present invention also provides a start up circuit for an oscillator having an oscillator output having a first state in a first instance and a second state in a second instance.

Abstract: A phase locked loop includes a differential charge pump to cancel static phase error and reduce sensitivity to noise. The differential charge pump comprises two substantially identical single-ended charge pumps so that under locked condition, changes in voltage at the charge pumps' output terminals are substantially identical, thereby maintaining a substantially constant difference between the charge pumps' output voltage. A differential input voltage-controlled oscillator receives the output of the differential charge pump and generates a clock signal with a frequency proportional to the voltage difference output by the differential charge pump. A common mode bias circuit adjusts the common mode voltage output by the differential charge pump to optimize the voltage swing available at the differential charge pump's output terminals.

Abstract: The invention relates generally to transmission of digitized information and more specifically to a digital receiver locking device that provides a decreased lock-in time and minimizes requirements to a permissible frequency and phase matching error. Outputs of a digital phase detector 1 are coupled, respectively, to an addition input of an analog adder 2 and a first information input of a multiplexer 3 having an output coupled to a subtraction input of the analog adder 2. An output of the adder 2 is connected via a low-pass filter to an input of a voltage controlled oscillator (VCO) 5 having an output connected to a clock input of a decision unit 6 whose information input is coupled, along with a first input of the phase detector 1 and a first input of a lock state detection circuit 7, to an input of the locking device. A second input of the phase detector 1 and a clock input of the decision unit 6 are coupled to an output of the VCO 5.

Abstract: A high speed frequency generator is disclosed. The frequency generator includes a frequency oscillator producing an output signal of a predetermined frequency, a first frequency divider frequency-dividing the first frequency oscillator's output signal, and a second frequency divider frequency-dividing an input signal by a predetermined factor. A flip-flop receives a signal generated from the second frequency divider and produces an output signal in accordance with an input clock signal. A pulse-width detector detects a width of the output signal of the flip-flop. A comparing part compares an output signal of the pulse-width detector with a reference value to control a counter that counts to a prescribed digital value that corresponds to a desired frequency. A digital-analog converter converts an output digital value from the counter into an analog value.

Abstract: A frequency synthesizer includes a first counter for counting cycles of an input clock and for generating a reference output bus, a VCO for generating an output signal, a second counter for counting cycles of the output signal and for generating a VCO output bus, and a phase detector for measuring the phase error between the reference bus and the VCO output bus and for generating a control signal which is applied to the control input of the VCO. The phase detector includes circuitry for computing a corrected bus by multiplying the VCO output bus with a correction coefficient proportional to the reciprocal of the modulo count of the second counter.

Abstract: A method and apparatus for biasing the voltage controlled oscillator (VCO) (110) of a Phase Locked Loop (PLL) (100) includes a bias circuit (114) providing a peak minimum/maximum voltage detector (202) tied to the control line (116) of the PLL (100). During operation, the detector (202) detects a minimum or maximum voltage on the VCO control line (116) as the bias control voltage (118) applied to the VCO (110) is varied. Detection of such a minimum or maximum voltage is equivalent to the detection of a minimum or a maximum frequency, which in turn equates to the detection of an optimal bias condition for noise.

Abstract: A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit comprising:a voltage controlled oscillator having a control node and having an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.

Abstract: A first phase comparator 22 of digital type and a second phase comparator 32 of sampling type are provided. Near a lock phase, an output current Iout2 is fed from the second phase comparator 32 to a voltage-controlled oscillator 14 through a change-over switch 40. In other phases, an output current Iout1 is fed thereto from the first phase comparator 22. When a reference signal fs is missing, a complementing circuit 50 complements a pulse to at least the reference signal fs input to the first phase comparator 22. A noise detecting/removing circuit 60 detects and removes noise from the reference signals fs, permits the reference signals fs to be fed to the first and second phase comparators 22 and 23, and halts the operations of the two phase comparators 22 and 32 for only a predetermined period of time after the noise has been detected.

Abstract: A method for removing an external frequency divider and clock formation circuit from a feedback path of a phase locked loop and a phase selector circuit are provided for synchronizing an external frequency divider with a reference clock of a phase locked loop. A reference clock signal is applied to the phase locked loop. An output of the phase locked loop is coupled through a predefined delay and provides a delayed feedback clock signal input to the phase locked loop. The external frequency divider is located at the output of the phase locked loop external to the predefined delay and outside the feedback clock signal path of the phase locked loop. A phase selector circuit identifies a correct phase of the reference clock signal and starts the external frequency divider. The phase selector circuit includes an edge detector, a synchronization divider, and a reset machine.

Abstract: The present invention designs and implements a high-speed PLL circuit and a high-speed synthesizer using the high-speed PLL circuit which has an increased switching speed, a reduced number of jitters and a reduced magnitude of spurious response. In order to achieve the above, the present invention provides a PLL circuit forming a closed loop wherein: one of the inputs of a phase comparator 1 serves as the input of the PLL circuit and the output of phase comparator 1 is connected to the input of a loop filter 2; the output of loop filter 2 is connected to the input of a voltage-controlled oscillator (VCO) 3; the output of the VCO 3 serves as the output of the PLL circuit; and the output of the VCO 3 is supplied to the other input of phase comparator 1 through a frequency divider 4. The circuit form and circuit constants of loop filter 2 are determined so that the transfer function of the closed loop becomes a Gaussian function.

Abstract: A method and apparatus for controlling an output frequency of a phase locked loop is accomplished by determining a plurality of divider ratios which are based on an input frequency, parameters, and a desired output frequency. Each of the divider ratios is representative of a ratio between the output frequency and input frequency of the phase locked loop. Having determined the plurality of divider ratios, another determination is subsequently made to determine whether the plurality of divider ratios enable the phase locked loop to produce the output frequency within a given frequency tolerance, i.e., within an allowable error. The determination is based on whether changing the divider ratio from the one of the plurality of ratios to an adjacent ratio causes the output frequency to change more than the allowable error. If so, the plurality of ratios needs to be recalculated based on a change in the input frequency and/or one of the parameters.

Abstract: An improved high-frequency all-digital phase-locked loop for locking a local signal in phase with an input signal is disclosed. It contains a novel digital control oscillator which includes: (a) a delay line comprising L delay gates for generating L clocks, where L is an integer and each of the delay gates has a delay time .PHI.; (b) a programmable up-down N-counter, where N is an integer; (c) a multiplexer which selects one of the L clocks based on a count of the up-down N-counter programmable; and (d) an adaptive-compensative circuit for determining the value of N based on the following conditions: ##EQU1## The adaptive-compensative circuit is implemented with a boolean encoder. This improved design allows all-digital PLL's to be constructed without a high frequency system clock, while, at the same time, maintains excellent stability and generates minimum output jitters.

Abstract: A stabilized frequency oscillating circuit outputs a pixel clock signal to an image scanner for controlling pixel rate at various writing positions along a scan line. The circuit includes a synchronization circuit having a first control signal component output to adjust a nominal output frequency of the oscillator; and a frequency profiling circuit having a second control signal component output which varies as a function of writing position along the scan line to determine a corrected output frequency of the oscillator which varies as a function of writing position along the scan line.

Abstract: A lock detector for a phase locked loop circuit, wherein an oscillator is controlled by a control signal produced by comparing the output signal of the oscillator to a reference signal. The lock detector samples the control signal, examines a plurality of samples according to criteria associated with a prescribed lock condition between the reference signal and the oscillator output signal, and generates a lock signal indicative of the lock condition being met if the samples satisfy the criteria. In a favorable embodiment, the lock detector forms a first group of samples sampled at a rate controlled by the reference signal and a second group of samples sampled at a rate controlled by the oscillator output signal. The samples are stored and shifted at the respective rates in respective shift registers. The contents of each stage of the shift registers are then examined according to a logic function.

Abstract: It is an object of the present invention to reduce the amount of spurious noise generated by an emission line spectrum of a signal propagating around the PLL of a PLL frequency synthesizer carrying out digital-signal processing.In order to achieve the object described above, the present invention provides a PLL frequency synthesizer with the following configuration.In a PLL frequency synthesizer having a charge-pump circuit, a waveform converter is provided at a stage behind the charge-pump circuit. The waveform converter converts the voltage waveform on a time axis of a rectangular wave output by the charge-pump circuit into a waveform which: is symmetrical with respect to a predetermined point of time; oscillates so as to have no direct-current component; and has a maximum value of the absolute values of maximums of wave heights thereof located at the center wherein the absolute value decreases uniformly as the wave height is separated farther away from the center.

Abstract: A pulse-width modulation signal generator having a pre-phase converter which includes N pre-delay circuits connected in cascade, and N main phase converters each of which includes M main delay circuits, where N and M are natural numbers greater than one, and N>M. The output of each of the N pre-phase circuits is supplied to one of the N main phase converters to generate phase converted clock signals used for generating a pulse-width modulation signal.

Abstract: A phase-frequency detector provides a decreased blind spot near 360.degree. of phase error and a resulting increased phase error detection range. In one embodiment, the phase-frequency detector includes two latches that are set in response to the detection of positive transitions in respective input clock signals. A reset controller resets both latches when they both get set. The duration and sequence of the latch states are thereby indicative of phase errors between the input clock signals. Two edge-triggered pulse generators provide a sustained indication of a detected positive transition in the respective input clock signals. When the time duration of the sustained indications is set equal to the reset time required by the latches and reset controller, the blind spot of the phase-frequency detector is largely eliminated.

Abstract: It is an object of the present invention to provide a frequency synthesiser with a lock speed-up arrangement in a simple and effective form. In accordance with the invention there is provided a frequency synthesiser including a voltage controlled oscillator, a phase detector which receives a base frequency signal and a feedback signal derived from the output of the voltage controlled oscillator and a filter circuit connecting the output of phase detector to a frequency control voltage input of the voltage controlled oscillator, the filter circuit having a reference voltage connection, and a speed-up circuit for applying a voltage signal to the reference voltage connection when a frequency change is demanded.

Abstract: A digital phase detector and charge pump circuit system reset circuit and method resets a digital phase detector according to the charge outputs between the charge pump circuits and a following loop filter. The sensing circuitry emulates portions of the circuitry of the digital phase detector and charge pump circuit system and minimizes deadband time. Current mirror portions of the charge pump circuit alternate between p-channel and n-channel devices to regularize output voltage levels produced by the charge pump circuit system.

Abstract: A PHS relay station demodulates a digital signal from a received radio-frequency signal by use of a reproduction clock produced from the digital signal. The relay station has an oscillator which generates a clock and a variable-ratio frequency divider for the clock outputted from the oscillator. A bit clock is produced from the output of the divider. A signal processor processes the digital signal by use of the bit clock. A detector detects a specific code in the digital signal in synchronism with the bit clock. The length of time that passes after the specific code detection signal is generated until the reproduction clock changes its level is detected as the phase deviation between the reproduction clock and the bit clock. The phase deviation is eliminated by temporarily changing the frequency division ratio of the divider in accordance with the amount of the deviation.

Abstract: A frequency synthesizer is supplied with an input signal of frequency .function..sub.i to provide an output signal .function..sub.o where .function..sub.o=.function..sub.i M/N and M and N are integers. The input signal is first applied to a divider circuit for division by M/K where K is an integer and the resultant is applied as inputs to a phase locked loop. The phase locked loop includes a ring oscillator of frequency .function..sub.i N/M, a frequency multiplier circuit for multiplying by K, and a frequency divider circuit for dividing by N. The ring oscillator uses a combinational logic circuit that combines the outputs of four differential delay elements to produce a frequency multiplication of four.

Abstract: A phase-lock loop (PLL) has an oscillator having a plurality of operating curves. During PLL auto-trim operations, the oscillator is automatically trimmed to an appropriate oscillator operating curve for use during normal PLL operations. In particular embodiments, the PLL is a charge-pump PLL having a phase/frequency detector (PFD) that generates error signals based on comparing an input signal and a PLL feedback signal; a charge pump that generates amounts of charge corresponding to the error signals; a loop filter that accumulates the amounts of charge to generate a loop-filter voltage; and a voltage-controlled oscillator (VCO), where the VCO output signal is used to generate the PLL feedback signal. During normal PLL operations, the loop-filter voltage is applied to the voltage input of the VCO.

Abstract: A lock detector (16) includes a set circuit (64), a reset circuit (120), and a latch circuit (80). The latch circuit (80) provides an output signal (82) in response to the temporal relationship of the first input signal (12) and the second input signal (14). The set circuit (64) initiates the transition of the latch circuit (80) to the locked state, while the reset circuit (120) initiates the transition of the latch circuit (80) to the not-locked state.

Abstract: A circuit and a method are provided for reducing power consumption in a phase-locked loop (PLL) by controlling how long the bias current for the charge pump is turned on. In such a circuit, a bias check circuit that indicates when the bias current has stabilized, and a self-adjusting control circuit including an internal counter are provided to measure how long the bias current takes to start up when the PLL is locked. Then the self-adjusting control circuit prevents the bias current from turning on until there is just enough time for it to stabilize before a charge pump event. A default control circuit is also provided to turn the bias current on for specified intervals when the PLL is out of lock.

Abstract: A phase synchronous circuit, in the process of locking an internal signal to an input signal by a PLL loop, makes a frequency of the internal signal stepwise approximate to a frequency of the input signal under digital PLL control at a first stage, and adjusting a phase under analog PLL control at a next stage, thus controlling a variable frequency oscillator at the two stages. A gain with which an analog PLL control system is burdened can be thereby reduced, and a gain of VCO may not be set larger than required even if a frequency of an output signal f.sub.out is high.

Abstract: A phase detection apparatus produces a phase difference signal in response to the phase difference between two applied input signals. The phase detector includes a lead/lag indicator receiving the input signals, and a logic block receiving the input signals. The logic block generates an output signal in response to the time delay between corresponding amplitude transitions, such as rising edges, of each of the input signals. The lead/lag indicator records which one of the two input signals leads in phase and generates an enable signal that steers the output signal from the logic block to one or the other of the phase detector's two output terminals.

Abstract: Various circuit techniques to implement continuous-time filters with improved performance are disclosed. The present invention uses RMC type integrators that exhibit lower harmonic distortion. In one embodiment, a novel high-gain two-pole operational amplifier is used along with RMC architecture to achieve lower harmonic distortion. In another embodiment, the present invention uses dummy polysilicon resistors to accurately compensate for the distributed parasitics of the polysilicon resistors used in RMC integrator. In yet another embodiment, the present invention provides an on-chip tuner with a differential architecture for better noise immunity.

Abstract: A self-tuning clock recovery phase-locked loop (PLL) includes a programmable divide-by-M, a phase-frequency detector, a programmable voltage-controlled oscillator (VCO), a programmable divide-by-N, and a PLL tuning circuit, which in normal mode operation, perform as a conventional PLL. When the frequency of an input clock signal to the PLL changes by more than a threshold value, however, the PLL tuning circuit causes the PLL to be retuned for the new frequency by adjusting offset and gain parameters in the PLL such that the input voltage to the VCO is mid-way in its input voltage range when the output clock frequency of the PLL is approximately equal to the input clock frequency multiplied by a closed loop gain of the PLL, so that the VCO is operating in a linear region having wide dynamic frequency range.

Abstract: A phase lock loop timing generator including a voltage controlled oscillator as a current-limited ring oscillator composed of multistage inverters connected in series in a ring form using a phase lock loop. From nodes of the inverters, .phi.0 to .phi.8 signals are obtained and an AND or OR of the signals are calculated to generate an internal timing. The obtained timing pulse is defined by % of a clock cycle of a reference clock signal and thus a timing depending on an external cycle can be set. Further, a timing prior to the clock edge of the reference clock signal can be generated and by using this timing, an effective current cut of an input buffer can be performed. Hence, a timing generation proportional to the external clock cycle without being affected by a production process or the like to enable us to provide a flexible timing designing.

Abstract: A PLL circuit includes a phase comparator that compares an external synchronizing signal and an internal synchronizing signal to detect a phase difference therebetween, and a voltage-controlled oscillator that generates the internal synchronizing signal by oscillation thereof. The frequency of the voltage-controlled oscillator is controlled depending upon the phase difference, so that the internal synchronizing signal becomes in phase with the external synchronizing signal. A limiting device is provided, which limits the phase of the external synchronizing signal supplied to the phase comparator to be within a predetermined window period that includes the timing of generation of the internal synchronizing signal.

Abstract: A digital PLL circuit is provided that has a frequency comparator circuit for comparing the frequencies of an output clock signal and a reference clock signal to generate frequency comparator information. A delay control circuit generates a predetermined digital signal based on the frequency comparator information, and a clock signal generating circuit generates the output clock signal of the PLL circuit. The clock signal generating circuit changes the oscillation frequency of the output clock signal in response to the predetermined digital signal generated by the delay control circuit. According to a preferred embodiment, the number of connected delay stages in a variable delay circuit (of the clock signal generating circuit) is controlled on the basis of the output of the frequency comparator circuit. Additionally, variable load capacitance circuits in the variable delay circuit are controlled mainly on the basis of the output of the frequency comparator.

Abstract: The present invention is directed to providing a phase detector capable of establishing phase-locked-loop operation in a highly accurate and reliable manner. For example, exemplary embodiments detect a phase difference between at least two input signals to phase lock the input signals to one another. Exemplary embodiments include two phase detectors each of which receives the two input signals (e.g., three-state phase detectors), and each of which is forced to operate outside of its dead-band region by introducing predetermined phase delays for its inputs. Each of the two phase detectors detects a phase difference between its respective inputs. The two phase differences are then combined to produce a composite output signal formed as a net charge proportional to the net phase difference detected by the two phase detectors.

Abstract: To provide a PLL circuit with little jitter and a minimum frequency drawing time, a PLL circuit comprises: a phase comparator for generating an up-down signal, which is turned to logic HIGH when a reference clock signal is phase-advanced to an output clock signal and a phase lock signal, indicating synchronization of the output clock signal to the reference clock signal; a timing signal generator for generating a timing signal when the phase lock signal is generated for a certain period after said timing signal generator is initialized with a reset signal; an up-down counter for generating a count value which is incremented when the up-down signal is at logic HIGH and decremented when the up-down signal is at logic LOW according to each pulse of a count clock, memorizing the count value in a nonvolatile memory when controlled by the timing signal, and outputting the memorized count value when initialized by the reset signal; a D/A converter for outputting a control voltage in proportion to the count value; an

Abstract: A lock circuit for indicating a locked/unlocked condition of phased lock loops circuits, which uses a reference clock signal input to a good-cycle counter and to a bad-cycle counter to signal a set/reset latch to output a signal indicating whether or not the phase of the output signal and input clock are in phase. Phase detector inputs are XOR gated to produce a pulse when the phase locked output clock is in a bad cycle indicated by the phase locked output clock not being in-phase with its input clock. Pulses on the XOR gate output on a bad cycle feed a single cycle counter reset circuit. The single cycle counter reset circuit on every cycle resets one of the bad and good counters based on its detection of a bad cycle pulse from the XOR gate. The good-cycle counter's output is to the SET input of the set/reset latch, and the bad-cycle counter's output is to the RESET input of the set/reset latch . We enable specific cycling of both the good and bad counters.

Abstract: A free loop oscillator system including a set of successive delay elements connected in series forming a free running loop oscillator, a set of taps disposed between the delay elements, a circuit for determining the speed of the free-running loop oscillator, and circuit for choosing a given tap in response to the speed of the free-running loop oscillator. Such a system may be implemented as a part of interval timer, a printer controller, a frequency synthesizer, an FM modulator, a digital-to-analog converter, or any other device which requires the availability of finely addressable signals since the taps disposed between the delay elements present signals much finer than any presently available clock.

Abstract: A phase-locked loop (PLL) circuit capable of attaining high-speed frequency transition with enhanced reliability. To this end, outputs of a reference signal source (1) and voltage-controlled oscillator (VCO) circuit (3) are frequency-divided by frequency divider circuits (2, 4), respectively. A phase comparator circuit (5) is provided for outputting an error signal indicative of a phase difference between these signals, if any. A window generator circuit (9) is connected for outputting a window signal; where the error signal does not fall within the range of a pulse width of this window signal, a level generator circuit generates a boost voltage having its potential near the control voltage value of the VCO (3) for use in generating of a target frequency.

Abstract: A phase-locked loop frequency synthesizer system is provided using fractional frequency division and a fractional control number for phase modulating an output of the frequency synthesizer using an incoming information signal. The apparatus includes a delta-sigma converter which adjusts a divisor of the frequency divider by operating upon a magnitude modulated fractional frequency control number. The system further includes a differentiator which provides the magnitude modulated input stream to the delta-sigma modulator by modulating the fractional control number with detected differences in the incoming information signal.

Abstract: The use of a control circuit (160) with either a programmable divider or divider(s) (190) and multiplexer (200) guarantees that, irrespective of the process variations, a voltage controlled oscillator has a low gain Vin-Fout characteristic in the desired frequency range. Low-gain voltage controlled oscillators are fundamental building blocks of low-jitter phase-locked loop (PLL) systems. The programmable divider/divider(s) (190) and multiplexer (200) are placed at an output of a current controlled oscillator(s) (180). A control circuit (160) defines the optimum current range(s) in the current controlled oscillator(s) (180). In the case of when a programmable divider is used, the control circuit (160) keeps changing the division ratio of the programmable divider until the PLL eventually achieves the "locked" state. When divider(s) and a multiplexer (200) are used, the control circuit (160) keeps changing the selected multiplexer input until the "locked" state has been achieved.

Abstract: A PLL including a phase comparator, a VCO, and a charge pump further includes a reset circuit. The reset circuit detects whether both of the charge pump transistors are in an ON state, and if so, generates a reset signal which inhibits the UP and DOWN signals generated by the phase comparator. The reset circuit includes first and second detection circuits and a signal generating circuit.

Abstract: An optical PLL circuit with high precision that has its simplified configuration. An optical-intensity modulator creates difference frequency information (N.times..DELTA.f) by modulating a received optical signal formed of signal optical pulses of a repetitive frequency (N.times.f0) with a reference signal of a frequency (f0+.DELTA.f) and implementing an AND operation of them. The signal is converted into an electric signal by a photo diode. A band-pass filter extracts only the low frequency component (N.times..DELTA.f). A frequency divider produces a frequency component .DELTA.f by dividing the extracted component by N. A multiplier receives the reference signal and the output signal f of a voltage-controlled oscillator and then creates the difference frequency component ((f0+.DELTA.f)-f). A phase comparator compares the low frequency component .DELTA.f with the difference frequency component ((f0+.DELTA.f)-f) and controls the voltage-controlled oscillator to set the phase difference between them to zero.