Abstract: A single-edge triggered phase detector which provides high speed phase detection. The phase detector works on only a single edge of the clock and data signal, which can be either the rising or falling edge. Extracted control signals are latched for at least one half of a clock period or more to ensure full rail to rail swing.

Abstract: A lock detection circuit for a phase lock loop circuit having a phase lock loop circuit, generally a series circuit of a detector, a filter and a VCO with a PLL input terminal and an output terminal. A test circuit is coupled to the phase lock loop and includes a signal generator responsive to the presence of an input signal on the input terminal to inject a test signal into the phase lock loop. The signal generator is preferably a low frequency oscillator wherein the term "low" is defined to mean any frequency from a few hertz up to gigahertz and generally a few kilohertz, as long as this frequency is at least about an order of magnitude less than the frequencies to be encountered at the RF input to the PLL. The signal generated by the signal generator is compared with the signal injected into the phase lock loop which is generally injected ahead of the loop filter.

Abstract: A digital frequency synthesizer includes a digital-to-analog (1), a low pass filter (2), and a controllable oscillator (3), where the oscillator output is the synthesizer output. K number of RS flip-flops (101-108) produce error signals which are coupled to the DAC. The S inputs of the flip-flops come from a phase-splitter (8) which is driven by the more-significant bits unit of an accumulator (5) which is clocked by a reference frequency. The R inputs of the same flip-flops get input pulses from a pulse distributor (9) which is driven by the synthesizer output. The frequency resolution can be increased by adding a less-significant bits accumulator (15), coupled to the more-significant bits unit.

Abstract: A FPLL has first second and third multipliers with the first multiplier supplying demodulated signals to a limiter and the second multiplier supplying signals to the loop filter. A VCO and phase shift circuit supply quadrature signals to the first multiplier and to the third multiplier which is relocated to an AC path in the loop to avoid the effects of offsets due to stray DC voltages and currents. The limiter output is applied to the third multiplier. The third multiplier supplies its output to the second multiplier. An integrated circuit embodiment using an exclusive OR gate as the third multiplier is also shown.

Abstract: A phase-lock-loop circuit includes a digital-to-analog converter of the bit rate multiplier type. The input word to the converter is updated once each horizontal period of a television signal. Phase information contained in an output signal of the bit rate multiplier is obtained in one horizontal period and is retained for affecting the phase in the immediately following horizontal period.

Abstract: Circuits, systems, and methods, relating to a controllably switched phase locked loop. The system indudes a phase locked loop circuit (16) having a clock signal input (16c), a clock signal lock input (16a), and a clock adjustment signal input (16b). The system further includes circuitry (12c) for coupling a clock signal to the clock signal input, circuitry (28) for coupling a first clock adjustment signal to the clock adjustment signal input, and circuitry (24) for comparing the first clock adjustment signal to a second clock adjustment signal. Lastly, the system includes circuitry responsive to the comparing circuitry. This responsive circuitry includes firstly, circuitry (26) for coupling a signal to the clock signal lock input such that the phase locked loop circuit indicates an unlocked state, and secondly circuitry (22, 28) for coupling the second clock adjustment signal to the clock adjustment signal input after the phase locked loop circuit indicates an unlocked state.

Abstract: A dual phase-locked loop (PLL) clock synthesizer is disclosed for generating clock signal in synchronization with the data input signal received over a network environment. The dual PLL clock synthesizer is suitable for processing data streams of any bit sequence without data error caused by interference due to clock signal jittering phenomena. The dual PLL clock synthesizer is particularly suitable for application to high-speed Ethernet network environment such as for decoding to obtain the original data conveyed over the network through selected encoding scheme.

Abstract: In a variable frequency divider capable of N+1/2 frequency division, a programmable frequency divider alternately frequency-divides an input signal by a frequency division ratio N (N being an integer) or by a frequency division ratio N+1. A first signal generating circuit generates a first signal in synchronism with an output signal of the programmable frequency division circuit. A second signal generating circuit generates a second signal which is identical to the first signal but delayed by half a period of the input signal. An output circuit alternately selects the first and second signals, and outputs the selected signal as frequency-divided signal. A delay circuit outputs a delayed signal identical to the first signal but delayed by one period of the input signal. A preset signal generating circuit alternately selects the delayed signal and the first signal, and presets the programmable frequency division circuit with the selected signal.

Abstract: An automatic frequency control circuit comprises an quadrature demodulation unit for creating an in-phase signal and an antiphase signal by quadrature-demodulating a Gaussian Minimum Shiftkeying signal and supplying an electric field strength signal exhibiting an electric field strength of the Gaussian Minimum Shiftkeying signal as well as the created in-phase and antiphase signals; a quality judging unit for judging the quality of the Gaussian Minimum Shiftkeying signal and creating an automatic frequency-controlling data indicating a compensation amount in accordance with the obtained quality signal; a converter for converting into digital signals the in-phase signal, antiphase signal and electric field strength signal supplied from the quadrature demodulation unit and converting the automatic frequency-controlling data into an analog signal; a temperature compensated crystal oscillation circuit for compensating the frequency of the GMSK signal on the basis of the compensation amount indicated by the automa

Abstract: A lock detector suitable for detecting when an output signal of a phase-locked loop circuit is phase-locked to an input reference signal. The lock detector includes a pair of delay lines, that are adjustable, which are used to create a window signal around the reference clock signal. UP and DOWN signals from the PLL circuit are fed to an OR gate to generate an actual out-of-lock signal. When the PLL circuit is phase-locked within an acceptable phase error range, the UP, and DOWN signals, if any, will appear within the generated window signal. When the PLL circuit is not phase-locked within the acceptable phase error range, the UP, and DOWN signals occur outside of the window. The window signal, and the output of the OR gate are connected to an AND gate to generate a gated out-of-lock signal. The gated out-of-lock signal is connected to a switched-capacitor charge pump.

Abstract: A digital loss of lock detection (LLD) device for a phase looked loop (PLL) generates a locked frequency signal synchronized with a reference frequency signal. The LLD comprises first to fifth latching means for detecting when the reference clock failed high/low, when the locked clock failed high/low and when the reference clock is outside the tracking range of the PLL. The first to fifth latching means provide respectively a first to fifth error signals for each type of the above faults.

Abstract: A horizontal lock detector circuit monitors charge pump control signals within a horizontal phase-lock loop to determine when the sampling pulses generated by the video system are locked in phase with the synchronization pulses of the input composite video signal. An output signal is generated by the lock detector circuit which is active when the sampling pulses are locked in phase with the input signal and inactive when the sampling pulses are not locked in phase with the input signal. The charge pump control signals are generated by a phase detector circuit within the phase-lock loop in response to a difference in phase between the sampling pulses and the input signal. Once the sampling pulses are locked in phase with the input signal, the charge pump control signals will become inactive. A current source is enabled when either of the charge pump control signals are active. The current source builds up a first level of charge on a first capacitor during the horizontal blanking period.

Abstract: Phase-locked loop (for signals having rectangular waveforms, comprising, in series, a phase detector, a control signal generator circuit having a loop filter, a controlled oscillator and an auxiliary circuit. The detector recieves a reference signal having a reference frequency from a reference source as first input signal. The detector recieves second and third input signals from the auxiliary circuit. The reference signal and the second input signal are compared by a first logic combination function to deliver a second combination signal. The second and third input signals are compared by a second logic combination function to deliver a second combination signal.

Abstract: The object of the present invention is to provide a clock synthesizer IC which can produce clock signals with much lower radiated EMI.

Abstract: A frequency multiplying device which multiplies the frequency of an externally-supplied reference signal PREF includes a digitally-controlled oscillation circuit, which includes a ring oscillator formed of thirty-two inverting circuits in a ring configuration which are adapted to generate sixteen clock signals having a period that is thirty-two times the inversion time of each inverting circuit and a phase interval that is twice the inverting circuit inversion time, and produces an output signal POUT having a period that corresponds to frequency control data CD at a resolution of the phase difference time of the clock signals, a counter/data-latch circuit which counts the clock signal RCK released by the ring oscillator within one period of the reference signal PREF and delivers the frequency control data CD of the count value to the digital oscillation circuit, and a control circuit which controls the operation of the circuits so that the oscillation output signal POUT having the frequency of the reference s

Abstract: A circuit with a phase-locked loop circuit which generates audio clock signals with zero ppm error from reference clock signals at a reference frequency is presented. The phase-locked loop (PLL) circuit has a first programmable divider circuit connected to the circuit input terminal, a first fixed divider circuit connected to the PLL output terminal and a second programmable divider circuit connected to the first fixed divider circuit, among other elements. The circuit also has several second fixed divider circuits, each second fixed divider circuit connected to the PLL output terminal, and a multiplexer selectively connecting the second fixed divider circuits to the circuit output terminal responsive to a programmable control signal. By properly selecting the integer divisors for the fixed and programmable divisors, the circuit can generate clock signals at any one of the audio sampling frequencies from a video clock signal.

Abstract: A loop circuit such as a delay lock loop or a phase lock loop includes circuitry for changing the strength of the lock after lock has been achieved. Before lock is achieved, the strength of the charge pump circuitry that controls the charge in the low-pass filter in the loop may be relatively weak. After lock has been achieved, the strength of the charge pump circuit may be increased so that the circuit can maintain its locked condition in a noisy environment.

Abstract: Using positive-phase or negative-phase clocks of phase count clock Pf.sub.0, a number M of multilevel quantized phase comparators output as values quantized in multiple levels the phase differences of output signals outputted from first and second N-stage frequency dividers wherein input clocks and output clocks, respectively, of a digital PLL have been N-stage frequency divided and moreover, divided into M groups. An adder adds this phase difference information and outputs advanced pulses or delayed pulses. An N1 counter counts up in response to advanced pulses and both outputs an increment pulse and undergoes setting to initial value N1 upon counting up to 2N1. In response to delayed pulses, the N1 counter counts down, and upon counting down to "0" both outputs a decrement pulse and undergoes setting to initial value N1.

Abstract: A phase locked loop including an in-phase detector (IPD), a quadrature phase detector (QPD), a frequency detector (FD), a squelch, a filter, and a voltage controlled oscillator (VCO). The in-phase detector has an IPD sample input, an IPD input, and an IPD output, where the IPD sample input is coupled to a data input. The quadrature phase detector has a QPD sample input, a QPD input, and a QPD output, where the QPD sample input is coupled to the data input. The frequency detector has a first FD input coupled to the IPD output, a second FD input coupled to the QPD output, and a FD output. The squelch has a squelch input, an enable input, and a squelch output where the squelch input is coupled to the IPD output and the squelch enable is coupled to the FD output. The filter has a filter input coupled to the squelch output and a filter output. The voltage controlled oscillator has a VCO input coupled to the filter output, a VCO in-phase output, and a VCO quadrature output.

Abstract: A precision CMOS one-shot having a delay proportional to a bias voltage. The bias voltage is generated by a phase locked loop which produces a bias voltage to control a voltage controlled oscillator (VCO) where the bas voltage is proportional to a difference between a first oscillatory signal and a reference oscillatory signal. Each CMOS one-shot includes a delay section for receiving the input signal and delaying production of the output signal. A current source supplies a current proportional to the bias voltage to said delay section, and the delay introduced by the delay section is proportional to the current. A latch sets the output signal of the delay section to a predetermined level after said delay has passed. An inverter is connected to an output terminal of the delay section and inverts the output signal from the delay section to generate the output signal of the one-shot. The precision one-shots may be used in a phase locked loop.

Abstract: A novel phase synchronous circuit includes a phase comparator, a first loop filter being electrically connected to the multiplying phase comparator, a second loop filter being electrically connected to the first loop filter, a voltage control oscillator being electrically connected to the second loop filter, an inventor circuit having an input side being electrically connected to the voltage control oscillator and a switching circuit having two input terminals and a single output terminal. The input terminal is electrically connected to the voltage control oscillator. The input terminal is electrically connected to an output terminal of the invertor circuit. The output terminal is electrically connected to an output terminal and also to an input side of the multiplying phase comparator. An input terminal is also electrically connected to another input of the multiplying phase comparator.

Abstract: A frequency synthesizer (100, 500) provides multiple selectable voltage controlled oscillator (VCO) frequency ranges. A VCO control circuit (114) controls the selectable VCO frequency ranges based on lock conditions of selected VCOs within a VCO array (112) or a single variable VCO circuit (502), to provide an extended tuning range to the frequency synthesizer (100, 500).

Abstract: In a Time Division Multiple Access System, multiple offset values are provided to a divider control circuit (213) of a fractional-N synthesizer (200) by utilizing a microprocessor (305). The microprocessor (305) utilizes timeslot information provided to it by a timeslot selector (301), frequency information provided to it by a frequency selector (303) and a read-only memory (307), to provide offset values to the divider control circuit (213).

Abstract: An improved phase locked loop utilizing control logic generated by a phase detector to eliminate sensitivity to uncorrelated noise when the loop is in lock.

Abstract: The present invention discloses a control algorithm of digital processing-phase locked loop(DP-PLL) for network synchronization to prevent phase-hit generated at the time of transition of the operation mode.

Abstract: Based on a phase locked loop (PC1, CP1, VCXO) which receives an incoming data signal (DS) and generates a recovered clock signal (RC), in the event that this incoming data signal (DS) includes low frequency cycling, false phase locking can occur, consequently leading to impaired operation; in order to avoid this, according to the invention, there is also included a false locking detector (FLD) to which is applied the incoming data signal (DS) and the recovered clock signal (RC) and the output of, which is added in an adder circuit (ADD) to that coming from the first loop, for producing voltage pulses when both signals are not at the same frequency, provoking a non-locked state. Only when the frequency is correct, does the false locking detector (FLD) not alter loop operation.

Abstract: A frequency synthesizer including a phase-locked loop, an oscillator of which supplies n phases with increasing delays of a fast clock signal synchronized on a reference frequency, each of said n phases being sent onto a same number m of fractional dividers having their respective outputs sent onto m jitter compensators which each issue, based on said n phases, a clock signal synchronized on said reference frequency.

Abstract: Calibration systems and techniques for analog phase-lock loops (PLLs) providing the capability to dynamically maintain a constant damping factor. Damping factor is calibrated by automatically setting a reference bias current I.sub.r to the PLL's charge pump such that the charge current I.sub.c output therefrom maintains the desired PLL damping characteristic. The technique presented involves selecting a known first frequency F.sub.1 and allowing the PLL circuit to reach steady state, after which a known second frequency F.sub.2 is applied and the PLL circuit is monitored to determine whether steady state at this second frequency F.sub.2 is accomplished within a predetermined target time T.sub.x, which corresponds to the desired damping factor. The determination of whether lock occurs within the target time T.sub.x is then employed to automatically setting the reference current I.sub.r.

Abstract: The invention provides an LSI with a built-in clock generator-controller which minimizes power dissipation of an entire system and reduces production of a skew between an external system clock signal and an internal clock signal.

Abstract: The present invention relates to a method of enhancing the noise Immunity of a phase-locked loop. The phase-locked loop includes a comparator and apparatus for inhibiting the action of the comparator on the phase-locked loop. According to the method, the inhibition is lifted during a main time window resulting from the intersection of a first time window derived from the input signal of the phase-locked loop, and of a second time window derived from the loop-return signal.

Abstract: Compensation circuits are disclosed for correcting phase offset during apparent phase lock of a dual flip-flop phase detector type of phase locked loop, which phase offset is due to circuit delays in the phase detector. Simultaneous "pump up" and "pump down" signals, present even during apparent phase lock because of such circuit delays, are peak sampled through long lime constant filters and summed to derive a compensating signal which is applied to the reference input to the differential amplifier which controls the local oscillator, thereby exactly counteracting the offset component of the voltage appearing at the signal input to the differential amplifier which is developed during normal operation of the phase detector, filter and summing circuit of the phase locked loop at apparent phase lock.

Abstract: A phase control circuit adjusts the width of a PLL clock signal so that a PLL clock signal generated from a master clock signal MCK is in synchronization with an EFM signal. A velocity detector detects offset in velocity by counting a pulse width of an EFM signal with a master clock signal MCK. The phase control circuit alters the pulse width of a PLL clock signal according to the detected offset in velocity to alter the average frequency of a PLL clock signal in proportion to offset of the rotational speed.

Abstract: Compensation circuits are disclosed for correcting phase offset during apparent phase lock of a dual flip-flop phase detector type of phase locked loop. The phase offset is due to circuit delays in the phase detector which result in the issuance of simultaneous "pump up" and "pump down" signals, present even during apparent phase lock. A second pair of flip-flops (or a single flip-flop) of the same type used in the phase detector is sampled to obtain a compensating signal which is applied to the reference input of a differential amplifier in the loop filter. Each of the second pair of flip-flops is forced to assume a permanent state (for example, set) such that their respective Q and Q-bar outputs are always representative of the logic voltage levels at the corresponding outputs of the flip-flops in the phase detector from which the "pump up" and "pump down" are sourced.

Abstract: A controllable crystal oscillator of a receiver having a mixer producing an IF signal is controlled by a feedback loop that includes a phase detector. The IF signal is delayed by an odd multiple of .pi./2 and fed to one input of an exclusive-OR circuit, with the other input receiving the IF signal directly. The phase detection signal from the exclusive-OR circuit can be counted and converted to an analog voltage when the oscillator is a voltage controlled oscillator or it can be counted and used as a digital control signal when the oscillator is a data controlled oscillator.

Abstract: A loop circuit such as a delay lock loop or a phase lock loop includes circuitry for detecting when the output signal of the low-pass filter in the loop has either risen to a voltage which is relatively close to the power voltage of the circuit or has fallen to a voltage which is relatively close to the ground voltage of the circuit. In either case the circuitry reverses the significance of the phase frequency detector output signals that control whether the output voltage of the low-pass filter rises or falls. Alternatively or in addition, the phase frequency detector may be reset. Coarser adjustments may be made to the loop circuit downstream from the low-pass filter in response to a recurrence of the low-pass filter output voltage reaching either of the detected voltages mentioned above.

Abstract: A PLL circuit of the pulse swallow-type prescaler system prevents erroneous module count operations such as are caused by a delay in the module signal, without the need to use a device which operates at high speeds or a device of large power. In a synthesizer of the pulse swallow-type prescaler system, a PLL circuit has a PLL COUNTER circuit and a module pulse generating circuit and a prescaler circuit has a prescaler counter, an extender circuit and a module control circuit which outputs a module control signal MO, for controlling the module operation, upon sensing the logic state of the module pulse generating signal MK, which is output by the module pulse signal generating circuit in response to the output signal MD of the PLL counter circuit.

Abstract: Systems and methods for accurately skewing periodic signals using a matching pair of voltage controlled delay lines, a frequency comparator, and a common control signal to the delay lines as generated by the frequency comparator. A feedback oscillation is established in a loop including one of the voltage controlled delay lines. The frequency comparator controls the frequency of the loop oscillation in direct proportion to a comparison between the oscillation frequency and a subharmonic of a base clock signal. The base clock signal is sent through the second voltage controlled delay line, which by matching of delay line characteristics and a common control signal introduces a clock period of skew or delay over the length of the second voltage controlled delay line. Taps to nodes in the succession of device stages making up the second voltage controlled delay line provides the clock signals with directly proportioned skews, the skews being defined by precise physical divisions of the delay line.

Abstract: A PLL circuit detects a phase difference between a signal relating to an output of a voltage control oscillator and a reference signal, and discrimination between a phase lead and a phase lag, increments or decrements a preset value by the number of pulses corresponding to the detected phase difference in accordance with the detected discrimination between the phase lead and the phase lag, converts the count value into a corresponding voltage, and feedbacks the voltage to the voltage control oscillator. When the reference signal is stopped, the count operation is halted. A plurality of values including an initial value for the value required in the count operation are previously stored, and a desired value is selected from these values.

Abstract: A phase locked loop locks on to the phase of a high speed serial data stream. The phase locked loop includes a multiple bit latch, a multiple-stage voltage controlled oscillator, a phase detection circuit and a feedback circuit. The multiple-bit latch has a plurality of data latch elements and boundary-detect latch elements. Each latch element includes a latch input for receiving the serial data stream, a sample clock input and a latch output. The multiple-stage voltage controlled oscillator has a voltage control input, a plurality of sample clock outputs and an adjustable delay between each sample clock output. Each sample clock output is coupled to a corresponding sample clock input. The phase detection circuit is coupled to the latch outputs of the data and boundary-detect latch elements and has a phase control output. A feedback circuit is coupled between the phase control output and the voltage control input.

Abstract: There is disclosed an integrated circuit including a phase detection circuit having an exclusive gate having first and second gate inputs for receiving first and second gate input signals. The exclusive gate provides at an output, a gate output signal that is the exclusive combination of the first and second gate input signals. A first switched resistance is coupled between a first voltage source and a common node. A second switched resistance, coupled between a second voltage source and the common node, receives the gate output signal of the exclusive gate to control the effective resistance thereof. The first and second resistances develop a signal at the common node. A comparator has a first input coupled to the common node and a second input coupled to a threshold value.

Abstract: A numerical voltage controlled oscillator comprising an integrator for generating an estimated sine waveform and an estimated cosine waveform from a variable control signal; a normalizer, connected to the integrator, for generating a normalization factor from the estimated sine waveform and the estimated cosine waveform; and a multiplier, connected to the normalizer, for multiplying the normalization factor with the estimated sine waveform and the estimated cosine waveform. The multiplication of the estimated sine waveform and the normalization factor produces the sine waveform and the multiplication of the estimated cosine waveform and the normalization factor produces the cosine waveform. The frequency and phase of the sine and cosine waveforms vary with changes in amplitude of the variable control signal.

Abstract: A phase lock loop timing generator including a voltage controlled oscillator as a current-limited ring oscillator composed of multistage inverters connected in series in a ring form using a phase lock loop. From nodes of the inverters, .phi.0 to .phi.8 signals are obtained and an AND or OR of the signals are calculated to generate an internal timing. The obtained timing pulse is defined by % of a clock cycle of a reference clock signal and thus a timing depending on an external cycle can be set. Further, a timing prior to the clock edge of the reference clock signal can be generated and by using this timing, an effective current cut of an input buffer can be performed. Hence, timing generation proportional to the external clock cycle without being affected by a production process or the like provides a flexible timing design.

Abstract: A phase-locked loop includes an input terminal (1) for receiving a binary signal, a phase comparator (3) having a first input (2) coupled to the input terminal (1), having a second input (4), and having an output (5) coupled to an input (9) of a control-signal-controlled oscillator (10) via a control-signal generator unit (7). An output (11) of the oscillator is coupled to the second input of the phase comparator. The phase comparator derives a first pulse (P.sub.1) and a second pulse (P.sub.2) in response to a signal transition from a first value to a second value in the binary signal applied to the first input and an oscillation signal applied to the second input, the first pulse having a pulse width which is a measure of the phase difference between the binary signal and the oscillation signal, and the second pulse having a pulse width proportional to 1/2.f.sub.o, where f.sub.o is the frequency of the oscillation signal.

Abstract: A frequency detector of a phase-lock-loop circuit is used for measuring a frequency error between a frequency of an output signal of an oscillator and a frequency of a synchronizing signal. When the frequency error in each of 32 periods of the synchronizing signal exceeds a predetermined magnitude, the phase-lock-loop circuits begins operating in a coarse frequency correction mode. As long as the 32 periods have not lapsed, the phase-lock-loop circuit operates in an idle mode of operation and the oscillator is not corrected. As a result, during vertical retrace, when equalizing pulses occur, the phase-lock-loop circuit is not disturbed by a large frequency error.

Abstract: A phase locked loop including a VCO having a multi-stage oscillator portion and a combinational logic portion. The multi-stage oscillator portion is configured to oscillate at a VCO clock frequency during a steady state condition under the control of a VCO control signal, and is further operative to develop a plurality of clock phases at the VCO clock frequency, with one of such clock phases used in the determination of the VCO control signal. The combinational logic portion is responsive to at least some of the plurality of clock phases and is operative to combine clock phases to create an output clock having an output clock frequency that is a multiple of the input clock frequency.

Abstract: A high speed divider circuit is provided for phase-locked loops (PLLs). The divider circuit in the feedback loop of the PLL has two divider circuits, a prescalar divide-by-4 circuit, which receives the high frequency signal from the voltage-controlled oscillator (VCO) of the PLL, and a programmable divide-by-N circuit, which resets itself after counting up to N. Responsive to the reset signal from the divide-by-N circuit, the prescalar divider circuit divides the VCO signal by 4+P, where P is a programmable value. This programmable periodic change in the divisor of the prescalar divide circuit allows the divisor in the classic PLL frequency synthesis equation to be set to nearly any number so that the synthesized output frequency of the PLL can be set with very fine resolution.

Abstract: A phase-locked loop circuit includes a voltage-controlled oscillator, a pre-scaler, a main counter, a shift register, and a phase comparison section. The oscillation frequency of the voltage-controlled oscillator is controlled on the basis of phase different information. The pre-scaler frequency-divides an oscillation frequency output from the voltage-controlled oscillator by one of frequency division ratios of 1/j (j is a positive integer) and 1/(j+1) which is selected in accordance with an external control signal. The main counter frequency-divides a frequency division output from the pre-scaler by a frequency division ratio of n (n is a positive integer). The shift register generates .alpha. (.alpha. is an integer equal to or larger than two) time series pulse strings which are synchronized with the output from the pre-scaler and have phases sequentially delayed by one period on the basis of a frequency division output from the main counter.

Abstract: An automatic adjustment circuit for an oscillator converts an output from a register into an analog signal by means of a D/A converter. An oscillation frequency of an oscillator is controlled by an output of the D/A converter. A first counter for counting an oscillation signal of the oscillator 1 resets itself and generates a pulse when a count reaches a predetermined value. A second counter counts a reference frequency pulse having a frequency substantially higher than the oscillation frequency of the oscillator. The second counter, on completion of counting a given preset value, changes an output level. The second counter is preset by said first counter when the first counter resets itself. Outputs from the first and the second counters are processed by an AND operation in an AND circuit. A third counter counts an output from the AND circuit, and provides a count output to the register.

Abstract: A phase locked loop circuit comprising a reference counter, a programmable counter, a phase detector and a lock detector.

Abstract: A phase-locked loop (PLL) frequency synthesizer is connected in reverse to a reference signal and a controlled oscillator loop including a low pass filter and a voltage-controlled oscillator (VCO). Rather than receiving a reference signal through a reference oscillator input and a VCO output signal through a VCO input, the PLL frequency synthesizer receives a reference signal through the VCO input and receives the VCO output signal through the reference oscillator input. Additionally, the output of the PLL is taken from the buffered reference output, thereby eliminating the need for an external buffer. Accordingly, the data loaded into the PLL frequency synthesizer accommodates the reversed input scheme by altering the divide ratios and inverting the phase detector output signal.