Abstract: Disclosed herein is a fractional N-type PLL frequency synthesizer apparatus. A fractional N-type control circuit employed therein for varying N values for each reference cycle is constructed of a combination of a frequency divider (comprising D flip-flops) and a logic circuit (comprising an exclusive OR circuit, AND circuits and an OR circuit), taking the timing provided to output a carry signal into consideration in advance. Owing to such a construction, the fractional N-type PLL frequency synthesizer apparatus can be activated with low noise and can provide a short lockup time.

Abstract: The frequency of a clocking signal is adjusted in response to fluctuations in the power supply voltage. In one embodiment, a control circuit has a plurality of clock input terminals each coupled between selected adjacent ones of the stages of a multiple-stage ring oscillator circuit and has an output clock terminal coupled to an input terminal of the ring oscillator circuit. In this manner, the control circuit may implement a plurality of loops each including a different variety of the stages of the ring oscillator circuit, wherein the clocking signal associated with each of the loops has a unique frequency. A plurality of trip voltages each being equal to a unique predetermined fraction of the power supply voltage are compared to a reference voltage. The control circuit selects, in response to the comparison of the trip voltages and the reference voltage, one of the loops mentioned above to provide its clocking signal to an output terminal of the oscillator.

Abstract: An improved apparatus for combining frequencies which is capable of generating a constant frequency when an external variation is applied thereto by implementing each block using a differential circuit, whereby it is adaptable to a mobile communication system, includes a phase frequency detector for comparing an input signal with a reference signal and for detecting a frequency or a phase error; a filter for differentially amplifying an output of the phase frequency detector for generating a lower frequency voltage corresponding to the error; a voltage control oscillator for generating a frequency corresponding to an output of the filter; a signal distribution unit for dividing the output of the voltage control oscillator into a predetermined times and for outputting a reference signal to the phase frequency detector; and a reference voltage generator for inputting reference voltages to the voltage control oscillator, respectively.

Abstract: An ASIC includes a PLL and digital circuitry to quantize and measure phase and average maximum jitter between a system clock input to the PLL, and a PLL-generated clock signal. The system clock is input to a series-string of delay elements, each contributing a delay of about 1.DELTA.t. Each delay element is associated with a two-input logic element, such as an EX-OR gate or an EX-NOR gate. One input to each two-input logic element is a version of the PLL-generated clock delayed by about (N/2) .DELTA.t. The second input to the first EX-OR is the output from the first delay element, the second input to the first EX-NOR is the output from the second delay element, and so on. Whichever delay element outputs a signal most closely in phase with the delayed PLL-generated clock will have an associated two-input logic element signal with a minimum duty cycle. Each two-input logic element output signal is capacitor integrated, sampled, stored and digitized.

Abstract: A circuit for enabling and disabling generation of an output clock signal is disclosed. The circuit includes a PLL lock detect circuit that generates an active lock control signal when an output reference signal of a phase lock loop (PLL) circuit is phase locked relative to an input reference signal to the PLL. The output reference signal of the PLL, and the lock signal from the lock detect circuit, are both provided to a clock enable circuit. The clock enable circuit includes a negative edge-triggered D-type flip-flop and a two-input AND gate. The lock signal is applied to the D-input of the flip-flop, while the clock signal is applied to the clock input of the flip-flop. The lock signal is generated asynchronously relative to the input clock signal. Therefore, the flip-flop samples the lock signal on each falling edge of the clock signal so as to synchronize the lock signal relative to the input clock signal.

Abstract: A phase locked loop comprises a voltage controlled oscillator, a 1/n frequency demultiplier, a phase comparator, and a modulation circuit. The phase comparator is supplied with a first signal which varies according to a reference clock signal and a second signal which varies according to a feedback signal supplied from the 1/n frequency demultiplier, executes phase comparison between the two signals, and controls the oscillation frequency of the voltage controlled oscillator by varying a control voltage by outputting an up-control signal or a down-control signal depending on phase difference between the signals. The modulation circuit generates the first signal by periodically modulating the reference clock signal with a shift width which is larger than the dead zone width of the phase comparator, and supplies the phase comparator with the first signal.

Abstract: A phase-locked loop (PLL) circuit has a phase comparator for comparing the phases of a local clock frequency and a reference frequency to generate a control signal indicative of a direction of adjustment of the local clock frequency for reducing the phase difference between the two frequencies. A voltage controlled oscillator (VCO) of the PLL responds to application of a control voltage thereto to generate an oscillation signal frequency from which the local clock frequency is derived. A loop filter responds to the control signal from the phase comparator to develop a control voltage for application to the VCO to adjust the local clock frequency in the direction indicated by the control signal to reduce the relative phase difference.

Abstract: A frequency synthesizer that can switch an output frequency fast and generates little spurious output is provided. This frequency synthesizer comprises a phase locked loop including a voltage-controlled oscillator, a high frequency divider, a phase frequency comparator and a low-pass filter. The divisor controller circuit supplies a divisor that varies cyclically to the high frequency divider for a fractional dividing operation. When switching the output frequency, a passing bandwidth of the low-pass filter is enlarged to widen a loop bandwidth of the phase locking loop for fast switching. After switching, the passing bandwidth of the low-pass filter is reduced to narrow the loop bandwidth for reduction of a spurious output, at the timing when a predetermined period has passed for the switched output frequency to stabilize substantially.

Abstract: A frequency synthesizer comprises a voltage controlled oscillator (VCO) with an output frequency f.sub.out that is dependent on a VCO-control voltage input. A divide-by-k counter is connected to receive the output frequency f.sub.out and to output a pair of in-phase and quadrature phase signals f.sub.k. A vector modulator is connected to receive the in-phase and quadrature phase signals f.sub.k and the output frequency f.sub.out, and outputs a single sideband (SSB) modulated output f.sub.n comprising only one of the sum (f.sub.out +f.sub.k) or difference (f.sub.out -f.sub.k) products. A divide-by-n counter is connected to receive the modulated output f.sub.n and to output a feedback frequency sample f.sub.f. And a phase detector is connected to receive the feedback frequency sample f.sub.f and to compare it with a reference frequency f.sub.r. A phase error output signal is provided for the VCO-control voltage input.

Abstract: A method and circuitry for detecting when a PLL achieves phase and frequency-lock to a reference frequency with minimal hardware and power dissipation are disclosed. The invention takes advantage of existing blocks within a PLL to reduce the amount of circuitry required while at the same time reducing error due to mismatch. In one embodiment, the present invention combines a coarse lock-detect circuit with a fine lock-detect circuit to achieve fast response when the input reference is lost, while filtering occasional minor phase hits due to external or internal noise.

Abstract: A fractional frequency synthesizer (100) includes a symmetrical divider (165) having an output frequency signal (135) fractionalized based on half cycles of its input frequency signal (130). The divider (165) is provided with a divisor (145) that varies based on half cycles of the output signal. Preferably, the divider (165) operates to selectively add or subtract an increment, corresponding to one half cycle of the input frequency signal (130), to a half cycle of the output frequency signal (135).

Abstract: In a PLL circuit, the phase of the frequency of an input signal is compared with that of an oscillation frequency generated from a voltage-controlled oscillator. Charge pump circuits are provided which outputs currents pulse-width modulated based on information about the error between the two phases, respectively. An output voltage of a capacitor provided at a stage subsequent to one of the charge pump circuits is converted into a current by a gm amplifier. Further, the converted current is added to an output current of the other charge pump circuit. The so-added output is used as a control input for the voltage-controlled oscillator. The oscillation frequency of the voltage-controlled oscillator is produced as an output signal frequency.

Abstract: A frequency synthesizer has multiple modes of operation including a relatively short-duration frequency seek mode and a relatively long-duration normal mode. The synthesizer responds to a reference frequency signal and produces a periodic signal at a frequency that is a rational number times the frequency of the reference frequency signal. The synthesizer comprises a VCO, a feedforward state machine, a feedback state machine, a phase comparator, controllable gain circuitry between the phase comparator and the VCO, and logic circuitry that coordinates the operation of the feedforward and feedback state machines during the seek mode.

Abstract: A PLL frequency synthesizer for realizing high-speed operation in a frequency synthesizer having a small channel interval .DELTA.f. There are provided n-number of phase comparators, feedback frequency dividers, and reference signal frequency dividers, and a timing generating section for outputting a signal causing each of the frequency dividers to become enabled every cycle of n.times..DELTA.f. An OR gate for superposing each phase comparison signal. Each phase comparison signal is sent to a charge pump after a cycle of n.times..DELTA.f, and the reference frequency is capable of being raised to n times the channel interval .DELTA.f. Further, a control section monitors lock detection of each phase comparator, thus implementing voltage control of each phase comparison system. When the synthesizer arrives at convergence-synchronization, the power sources to all systems are turned OFF except for the phase comparison system initiating the lock signal.

Abstract: An integrated circuit phase-locked loop includes a phase/frequency detector, a charge pump, and a voltage-controlled oscillator (VCO) which are coupled together in series. The VCO has first and second VCO control inputs, and has a VCO output which is coupled to the phase/frequency detector. An off-chip loop filter input is coupled between the charge pump and the first VCO control input for coupling to an off-chip loop filter. An on-chip loop filter is coupled between the first VCO control input and the second VCO control input. The VCO has a lower voltage-to-frequency gain from the first VCO control input to the VCO output than from the second VCO control input to the VCO output.

Abstract: A method and apparatus for generating a finely adjustable clock is accomplished by a ring oscillator, a plurality of counting circuits, and a controller. The ring oscillator generates a plurality of oscillations, wherein each of the oscillations have an approximately equal period and are phase shifted by an approximately equal phase shift. Each of the plurality of oscillations is provided to one of the counting circuits which divides the frequency of the respective oscillation by a given count value to produce corresponding periodic representation. The controller selects one of the corresponding periodic representations based on control signal to be the output oscillation, or clock signal. When the clock signal needs to be finely adjusted, the controller, based on the control signal, selects another one of the corresponding periodic representations.

Abstract: In a frequency synthesizer, a variable frequency divider divides the oscillation signal of a VCO while switching the frequency dividing ratio in accordance with an integral frequency dividing ratio generated by a frequency dividing ratio generating circuit. The VCO is controlled with an output of a loop filter. The frequency dividing ratio generating circuit includes multiple integrators connected in cascade and differentiators which differentiate the carry-out signals of the integrators, so that a phase error generated at the variable frequency divider is obtained from an output of an adder included in the final stage integrator of the frequency dividing ratio generating circuit. A phase error compensation value is output, and further a pulse width of a signal to be used for compensating for phase error is varied in accordance with the phase error compensation value to perform compensation for the phase error.

Abstract: A variable-path-length voltage-controlled oscillator circuit is provided. The oscillator circuit has a ring oscillator formed from a series of voltage-controlled inverter stages. The path length (i.e., the number of inverter stages) in the ring is selected based on path length configuration data stored in memory. The selected path length determines the nominal or center frequency of operation of the ring oscillator. The output frequency of the oscillator circuit is voltage-tuned about this center frequency by varying the delay of each inverter stage in the ring oscillator path. Various types of voltage-controlled inverter stages may be used, including current-starved inverter stages, variable-capacitive-load inverter stages, and differential-delay inverter stages. The voltage-controlled oscillator circuit may be used in a phase-locked loop on a programmable logic device for frequency synthesis or to eliminate clock skew.

Abstract: An error suppressing circuit (301) and method therefor for a phase locked loop (PLL) (300). According to one embodiment of the present invention, a transient condition, for example, a bandwidth switch, in the PLL (300) is detected. The PLL (300) is opened for a period of time (509) responsive to detecting the transient condition. The phase of a reference frequency signal (115) and the phase of a output frequency signal (116 or 117) are synchronized after a lapse of the period of time (509). The PLL (300) is closed responsive to the phase of the reference frequency signal (115) and the phase of the output frequency signal (116 or 117) being synchronized. The present envention advantageously reduces the length of time it takes for the PLL (300) to correct for the phase and frequency error generated by the transient condition, and is capable of operating with various types of PLLs.

Abstract: A method and an apparatus for generating oscillating waveforms using adiabatic circuitry. In one embodiment, an LC oscillating circuit generates oscillating waveforms that are replenished with replenishing circuitry. The replenishing circuitry includes enable circuitry and circuitry that reduces short circuit currents that may flow through the replenishing circuit. Furthermore, the pull-up and pull-down devices of the replenishing circuit are gradually turned on and gradually turned off to reduce the introduction of glitches into the oscillating sinusoidal waveform of the oscillating circuit. A control circuit, such as a phase lock loop circuit, is included with the present invention to receive an external clock reference waveform and match the frequency and phase of the oscillating waveform in the oscillating circuit to the external clock reference waveform.

Abstract: A method and apparatus for recovering the time base of signals which change at periodic intervals is disclosed. The apparatus comprises gated voltage controlled oscillators (GVCO) that are alternated or exchanged, to reduce phase and frequency deviations in the recovered time base signal, such as the deviations induced by inherent GVCO differences. Each GVCO is stabilized by a respective phase locked loop. The respective GVCOs are gated only in response to a chosen polarity transition in the input signal, to make the circuit more tolerant of waveform distortions. More than two GVCOs may be used to provide improved frequency drift resistance. The circuit uses resynchronization control signals, such as the time slot signal in synchronous switching systems, to indicate resynchronization or reassignment of the GVCOs in gaps in the data transmission.

Abstract: The capture range and stability of a phase locked loop are improved by adjusting the free running frequency of a voltage controlled oscillator in response to the output signal of the phase locked loop. The output signal is filtered and amplified, and then compared to a reference signal from the voltage controlled oscillator which is indicative of the free running frequency. A direct current level capture circuit compares the filtered and amplified output signal with the reference signal and generates a control signal which adjusts the free running frequency so as to equalize the output signal and the reference signal. The control signal is generated by sequentially and consecutively enabling a series of filter reset circuits. A switch control circuit controls two feedback paths between the phase detector and the voltage controlled oscillator. The first feedback path includes a low pass filter and is selected by the switch circuit for normal operation.

Abstract: A clock signal reproduction circuit including an A/D conversion circuit for converting an input RF analog signal with a restricted upper limit of a frequency band into a digital signal, a digital phase error calculation unit for digitally calculating a phase error of a digital signal converted in the A/D conversion circuit, a control voltage generating unit including a loop filter, a D/A conversion unit for outputting an analog control voltage signal based on the digital phase error calculated, and an analog voltage-controlled type oscillating circuit for outputting a reproduction clock signal having a frequency of at least 2 times the frequency of the input analog signal. The A/D conversion circuit uses the clock signal output from the analog voltage-controlled type oscillating circuit to convert the input analog signal into a digital format and output a reproduction clock signal from the analog voltage-controlled oscillating circuit.

Abstract: A phase lock loop circuit includes an oscillator, a digital mixer, a comparator, a loop amplifier, and a low-pass filter. The oscillator has an oscillation frequency controlled by a control voltage. The digital mixer is constituted by a digital element to output a difference frequency signal between an oscillation output from the oscillator and an input mixing signal. The comparator compares at least the phase of the difference frequency signal output from the digital mixer with that of a reference frequency signal, and outputs a difference signal. The loop amplifier and the low-pass filter generate the control voltage for the voltage controlled oscillator on the basis of the difference signal output from the comparator.

Abstract: The invention provides a phase synchronization system which stops, when an input of a phase reference signal from the outside stops, oscillation of a voltage-controlled oscillator to achieve reduction in power consumption and can produce and output a system clock signal free from high frequency pulse noise from the voltage controlled oscillator. The system includes a phase comparator, a phase synchronization circuit including a low-pass filter and a voltage-controlled oscillation circuit, a clock detection circuit for detecting the clock signal from the outside, a phase coincidence discrimination circuit for discriminating a phase coincidence condition at the phase synchronization circuit, an AND gate, and a stop/start control circuit including a pair of flip-flop circuits. When the clock signal from the outside stops, oscillation of the voltage-controlled oscillation circuit is stopped with control information from the stop/start control circuit.

Abstract: A delay equalization circuit for minimizing the static phase error in a PLL is provided. The delay equalization circuit includes an external clock signal variable delay path, and an element for creating a pulse with a width proportional to the delay of the external clock signal variable delay path. The delay equalization circuit also includes a delay path in the feedback loop, and second element for creating a second pulse in proportion to the delay of the internal delay path. Finally, the circuit contains a comparison device. The comparison device compares the first and second pulses. The comparison device outputs a difference signal in proportion to the difference in the external and internal path delays. That difference signal is fed back and used to control the external path delay such that the external delay is driven to be substantially equal to the internal delay, minimizing the static phase error of the PLL device.

Abstract: A phase lock loop wherein the reference clock is divided by a variable divider which is capable of dividing the reference clock by a divider ratio of 2, 3, 4, . . . or M depending on the value of a control signal. The control signal is generated from a divider controller in response to a controller input. The noise shaping characteristics of the divider controller results in dithering of the variable divider ratios such that the average frequency of the divided reference clock is at the desired comparison frequency but the quantization noise from the fractional divide is pushed from low frequency to high frequency where it is more easily filtered. The noise shaper can be implemented with many bits of resolution to allow for a wide frequency control range and high frequency accuracy. A dither circuit to prevent limit cycling at the output of the noise shaper.

Abstract: A variable frequency synthesis apparatus and method use a phase prediction signal to enable integer division in the feedback path of a phase-lock-loop to provide an output signal at a rational frequency multiple of an applied reference signal. A fixed integer divide ratio is maintained within each period of the reference signal. The output signal provided by a variable frequency oscillator is frequency divided and is phase compared to the reference signal. The phase comparison produces a predictable, time-varying phase difference signal based on a known frequency difference between the output signal and the reference signal. The phase prediction signal cancels the predictable phase difference signal and isolates an phase error signal used to steer, or adjust, the frequency of the oscillator to precisely equal the rational frequency multiple of the applied reference signal when the phase error signal is minimized.

Abstract: A phase-locked-loop device for generating an output signal of frequency Fo, n phase-lock with an input signal of frequency Fi, where Fo=N(Fi/M). The invention reduces noise and provides optimal-time frequency switching--settling in one cycle of the phase-detector reference signal by applying a signal shaped like a smooth broad hump to the voltage-controlled oscillator upon a frequency change command. It maintains optimal-time switching by keeping the PLL loop-gain constant. The invention reduces noise by eliminating the so called "dead-zone" in the digital phase-detector.

Abstract: A fractional N-frequency synthesizer includes an accumulator outputting an output value, and a spurious signal cancel circuit. The spurious signal cancel circuit includes a pulse forming circuit, receiving a spurious signal cancelling reference signal, a reset signal and the output value of the accumulator, and outputting, in synchronism with the spurious signal cancelling reference signal, a pulse voltage signal having a pulse width proportional to the output value of the accumulator from a time when the reset signal is received, and a constant current circuit controlled by the pulse voltage signal and outputting an output current of the spurious signal cancel circuit.

Abstract: A phase-locked loop (PLL) includes a voltage controlled oscillator (VCO), a charge pump, a phase detector and a frequency detector. The phase detector detects the phase difference between an incoming signal and a VCO signal. The frequency difference between the incoming signal and a reference signal is detected by the frequency detector separately from the phase detector. During the process of attaining phase lock, the phase and frequency detectors operate simultaneously. The VCO signal is phase-locked to the incoming signal when it is present. When the incoming signal is absent, the VCO maintains a frequency close to an intended bit rate by frequency locking to a multiple of the reference signal. It, thus, avoids extreme system behavior and greatly assists rapid reliable phase lock when the incoming signal is applied following a period when it is absent.

Abstract: A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively. The up signal generator includes a first p field effect transistor (FET) having a gate for receiving a set signal, a second p FET having a source coupled to the drain of the first p FET and having a gate for receiving a reference clock signal. A first n FET has a source coupled to the drain of the second p FET and has a gate for receiving the set signal.

Abstract: A semiconductor integrated circuit device including input and output registers, a data-processing circuit block disposed between the registers, a first PLL circuit for supplying a first output clock signal to the input register in response to an input clock signal, and a second PLL circuit for supplying a second output clock signal to the output register in response to the input clock signal. The input register transfers a data signal stored therein to the output register in response to the first output clock signal. The output register stores the data signal and transfers it to another device in response to the second output clock signal. The first and second PLL circuits supply the first and second output clock signals to the input and output registers with keeping the phase differences constant, respectively.

Abstract: A digital phase detector which generates low jitter when the phase-locked-loop is in lock. A delay line, combined with an UP/DOWN phase detector causes substantial overlap in the UP and DOWN signals from the detector. When the PLL is in lock, the overlapping signals substantially cancel each other out, minimizing the variations in the output frequency. Two approaches are disclosed: one delaying the UP signal sufficiently to overlap the DOWN signal, the other using a delay and an exclusive OR gate to generate the DOWN signal.

Abstract: A phase frequency detection circuit and method in a phase lock loop circuit uses delay circuits to limit the period of expression of up and down signals which adjust the output frequency of a voltage controlled oscillator. The pulse frequency detection circuit includes cross-linked latches to drive logic gates which produce output signals for adjusting the output frequency of a voltage controlled oscillator and delay circuitry connected to the outputs of particular logic gates for selective nullification of up and down control signals to a voltage controlled oscillator.

Abstract: A phase lock loop system includes: a phase detecting circuit which operates on the basis of a signal waveform; a current output circuit for generating a current value from a phase difference detected by the phase detecting circuit; a filter which is constructed by only a resistor in a phase locked state by a synchronizing signal and by a capacitor and the resistor upon phase following state; and a voltage controlled oscillator for controlling an oscillation frequency by a voltage output of the filter. The phase lock loop system operates as a primary phase lock loop circuit in the phase locked state by the synchronizing signal and operates as a secondary phase lock loop circuit upon phase following state.

Abstract: A PLL circuit has a feedback loop including a plurality of feedback circuits in parallel and a combining circuit. The feedback circuits receives an output signal of the PLL circuit and produce feedback output signals, respectively. The combining circuit combines the feedback output signals into a feedback signal which is used to be compared to a reference signal. The feedback circuits in parallel each divide a frequency of the output signal by a predetermined number and the combining circuit performs logical OR of the feedback output signals.

Abstract: A frequency multiplying device which multiplies the frequency of an externally-supplied reference signal PREF includes a digitally-controlled oscillation circuit, which includes a ring oscillator formed of thirty-two inverting circuits in a ring configuration which are adapted to generate sixteen clock signals having a period that is thirty-two times the inversion time of each inverting circuit and a phase interval that is twice the inverting circuit inversion time, and produces an output signal POUT having a period that corresponds to frequency control data CD at a resolution of the phase difference time of the clock signals, a counter/data-latch circuit which counts the clock signal RCK released by the ring oscillator within one period of the reference signal PREF and delivers the frequency control data CD of the count value to the digital oscillation circuit, and a control circuit which controls the operation of the circuits so that the oscillation output signal POUT having the frequency of the reference s

Abstract: In a clock recovery circuit in a demodulator of a multi-level quadrature amplitude modulation (QAM) system, an analog/digital (A/D) converter performs an A/D conversion upon a coherent-detected baseband analog signal in synchronization with a sampling clock signal having a time period half of a symbol time period. An phase detector receives successive first, second and third sampled data from the A/D converter, determines whether or not a signal transition formed by the first and second sampled data crosses a zero value within a predetermined time deviation, and compares a polarity of the second sampled data with a polarity of one of the first and second sampled data to generate a phase detection signal. Further, a loop filter is connected to an output of the phase detector, and a voltage controlled oscillator supplies the sampling clock signal to the A/D converter in accordance with an output signal of the loop filter.

Abstract: A phase locked loop including a comparator, a VCO controller, and a VCO having a multi-stage oscillator portion and a combinational logic portion. The comparator is responsive to an input clock and a VCO comparison clock and is operative to produce a comparator output signal. The VCO controller is responsive to the comparator output signal and is operative to produce a VCO control signal. The multi-stage oscillator portion is configured to oscillate at a VCO clock frequency during a steady state condition under the control of the VCO control signal, and is further operative to develop a plurality of clock phases at the VCO clock frequency. The combinational logic portion is responsive to at least some of the plurality of clock phases and is operative to combine clock phases to create an output clock having an output clock frequency that is a multiple of the input clock frequency.

Abstract: A phase lock loop includes a voltage controlled oscillator (VCO), a phase comparator for comparing the phases of the output of the VCO and a reference signal, a charge pump circuit, including a plurality of current sources, for supplying a control voltage by charging or discharging a capacitor based on the outputs of the current sources, and a current source controller for controlling the current output of the current sources by a n-bit current control signal. Charge current and discharge current by the charge pump circuit are controlled in n bits so that a rapid synchronization during lock-in and a low jitter after lock-in can be obtained.

Abstract: A chroma lock detector circuit monitors charge pump control signals within a phase-lock loop to determine when two input signals to the phase-lock loop are locked together in phase and generates an output signal which is active when the two input signals are locked together in phase and inactive when the two input signals are not locked together in phase. The charge pump control signals are generated in response to a difference in phase between the two input signals and will become inactive once the two input signals are locked together in phase. When the charge pump control signals are inactive for a predetermined period of time, the output of the chroma lock detector circuit is activated and will remain active until the charge pump control signals are again active. A current source is enabled when either of the control signals are active. The current source builds up a first level of charge on a first capacitor during the burst period.

Abstract: Within a microprocessor, multiple synchronous clock signals of arbitrary integer and non-integer ratios are produced with conventional digital divider circuitry. The various integer and non-integer clock signals can be provided to processor circuitry, bus circuitry, and coupled memory circuitry. Non-integer ratio clock signals can be produced out-of-phase with the system clock signal.

Abstract: A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit including a voltage controlled oscillator having a control node and having an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.

Abstract: A phase detector for a phase-locked loop ("PLL") circuit under control of a local oscillating clock ("LOSC") signal and a method of operation thereof.

Abstract: A non-linear integrated phase locked loop circuit includes a phase detector for receiving a data signal and a clock pulse and for outputting a pump-up signal and a pump-down signal, a pulse divider connected to the phase detector for receiving the pump-up signal and the pump-down signal and producing a first output at predetermined multiples of the pump-up signal and a second output at predetermined multiples of the pump-down signal. A pulsed filter or integrator is connected to the pulse divider for receiving the first output and the second output and providing a frequency control signal for a voltage controlled oscillator. A three state amplifier is connected to the phase detector for receiving the pump-up signal and the pump-down signal and providing a phase control signal for a voltage controlled oscillator. The voltage controlled oscillator is connected to the pulsed filter and the amplifier for receiving the frequency control signal and the phase control signal and producing a corresponding output.

Abstract: A method for setting a locking frequency operating range of the phase locked loop (PLL) circuit and a phase locked loop (PLL) circuit are provided with range select logic for detecting an unknown reference clock frequency and for setting a locking frequency operating range of the phase locked loop. First a bypass mode for the phase locked loop (PLL) circuit is set. An unknown reference clock frequency is applied to a first counter. A known oscillator clock frequency is applied to a second counter. The first and second counters are reset and a timeout value of the second counter is identified. A first counter count value is compared with precalculated constant values. A set of range bits are latched responsive to said compared values. Two consecutive sets of latched range bits are compared and the steps repeated until a match of two consecutive sets of latched range bits is identified. The matching latched range bits are applied to a programmable range select input of the phase locked loop (PLL) circuit.

Abstract: A voltage controlled ring oscillator (10) integrated with a phase locked loop (101) using CMOS technology. The ring oscillator (10) provides a frequency multiplied harmonic output frequency (42) at a frequency of 2.5 GHz or more while operating at only one-third of that frequency. The ring oscillator (10) uses an odd number of inverter stages (12, 14, 16) and provides high frequency CMOS operation by utilizing the phase shifted signals of the ring frequency at each ring inverter output (20, 24, 28). The ring oscillator (10) draws minimal current and is incorporated in a frequency synthesizer (100) used in a radio communication device (200).

Abstract: A clock recovery unit for recovering a clock embedded in a data communication is disclosed. The clock recovery unit includes an oscillator (50) operating at a frequency close to that of the clock embedded in the data communication. The clock recovery unit also includes an edge detector (30) that produces a synchronization pulse with each transition in the data communication. The edge detector is coupled to the oscillator to force a transition in the oscillator in synchronization with the synchronization pulse produced by the edge detector. A start-up latch (10) that starts and stops the oscillator also forms part of the clock recovery unit. The start-up latch starts the oscillator at the beginning of the data communication, with no preamble bits required. For low-power consumption in stand-by mode, a counter (40) coupled to the start-up latch stops the oscillator after data has been determined not to be present for a preset period of time.

Abstract: A PLL circuit includes a sampling pulse generator and a loop circuit using a sample and hold circuit as a phase detector. The sampling pulse generator generates a sampling pulse signal at each level transition of an NRZ input signal. The sample and hold circuit samples a clock signal and hold a voltage signal corresponding to a voltage of the clock signal according to the sampling pulse signal. A voltage-controlled oscillator included in the loop circuit generates the clock signal whose frequency is controlled based on tho voltage signal received from the sample and hold circuit through a loop filter. The voltage signal remains at an appropriate level even when the NRZ input signal remains at the same level for a relatively long time. The sampling pulse generator includes a delay circuit for delaying the NRZ input signal and an exclusive-OR circuit receiving the NRZ input signal and the delayed signal.