Sensing Modulation (e.g., Frequency Modulation Controlled Oscillator Patents (Class 331/23)
  • Patent number: 12017919
    Abstract: A method of hyperpolarizing diamond particles includes applying a laser to a sample of the diamond particles, irradiating the diamond particles with a sweeping microwave to cause diamond polarization, shuttling the diamond particles through a magnetic field to detect 13C nuclei in the diamond particles, and relaying the diamond polarization to nuclear spins to one of a surrounding solid or fluid.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: June 25, 2024
    Assignee: The Regents of the University of California
    Inventors: Alexander Pines, Ashok Ajoy, Raffi Nazaryan, Xudong Lv, Carlos Meriles
  • Patent number: 11954487
    Abstract: Disclosed are apparatuses, systems, and techniques to perform and facilitate fast and efficient modular computational operations, such as modular division and modular inversion, using shared platforms, including hardware accelerator engines.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: April 9, 2024
    Assignee: Nvidia Corporation
    Inventors: Shuai Wang, Chen Yao, Xiao Wu, Rongzhe Zhu, Yuji Qian, Xixi Xie
  • Patent number: 11955979
    Abstract: An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: April 9, 2024
    Inventors: Reetika K Agarwal, Abbas Komijani, Hongrui Wang
  • Patent number: 11757683
    Abstract: A receiver includes a plurality of linear equalizers receiving an input signal; and a plurality of samplers configured to sample a plurality of equalization signals output from the plurality of linear equalizers according to a clock signal. Each of the plurality of linear equalizers compares the input signal with a reference voltage among a plurality of reference voltages to determine a level of the input signal.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: September 12, 2023
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Daeho Yun, Deog-Kyoon Jeong
  • Patent number: 11264997
    Abstract: Systems, methods, and circuitries are provided to generate a radio frequency (RF) signal having a desired radio frequency fRF. In one example a frequency synthesizer system includes a clock, an opportunistic phase locked loop (PLL), and an RF PLL. The clock circuitry is configured to generate a clock signal having a frequency fXTL. The opportunistic phase locked loop (PLL) is configured to generate a reference signal having a reference frequency fREF that is close to a free-running frequency of an oscillator in the opportunistic PLL. The opportunistic PLL is configured to synchronize the reference signal to the clock signal. The RF PLL is configured to generate the RF signal having the desired radio frequency and to synchronize the RF signal with the reference signal.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Gil Horovitz, Sharon Malevsky, Evgeny Shumaker, Igal Kushnir
  • Patent number: 10459479
    Abstract: A data storage device is disclosed comprising a head actuated over a disk, and preamp circuitry coupled to the head, wherein the preamp circuitry comprises a preamp clock and a clock counter configured to count cycles of the preamp clock. A start command over is transmitted from system circuitry over a serial interface to the preamp circuitry to begin counting a number of cycles of the preamp clock. The system circuitry receives a preamp command over the serial interface from the preamp circuitry, wherein the preamp command is based on the clock counter in the preamp circuitry. The system circuitry generates a frequency adjustment command based on the preamp command, and transmits the frequency adjustment command over the serial interface to the preamp circuitry in order to adjust a frequency of the preamp clock.
    Type: Grant
    Filed: March 31, 2018
    Date of Patent: October 29, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventor: Joey M. Poss
  • Patent number: 8947172
    Abstract: A frequency modulating path for generating a frequency modulated clock includes a direct feed input arranged for directly modulating frequency of an oscillator, and a compensating feed input arranged for compensating effects of frequency modulating on a phase error; wherein the compensating feed input is resampled by a down-divided clock that is an integer edge division of the oscillator. A reference phase generator for generating a reference phase output includes a resampling circuit, an accumulator and a sampler. The resampling circuit is for resampling a modulating frequency command word (FCW) input to produce a plurality of samples. The accumulator is for accumulating the samples to generate an accumulated result. The sampler is for sampling the accumulated result according to a frequency reference clock, and accordingly generating a sampled result, wherein the reference phase output is updated according to at least the sampled result.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: February 3, 2015
    Assignee: Mediatek Inc.
    Inventors: Chi-Hsueh Wang, Kai-Peng Kao, Robert Bogdan Staszewski
  • Patent number: 8830003
    Abstract: An ultrasonic generator is provided, in which the control system can easily be changed in accordance with a cleaning application and a cleaning process. The ultrasonic generator according to the present invention, which causes an ultrasonic transducer to oscillate a signal for ultrasonic vibration, includes a programmable multiple control circuit having a signal generation circuit for generating a signal, and an output adjustment circuit for adjusting the output of the signal from the programmable multiple control circuit, wherein the programmable multiple control circuit has a power control circuit electrically connected to the output adjustment circuit, a phase comparison circuit electrically connected to the output adjustment circuit, a frequency control circuit electrically connected to the phase comparison circuit, and a signal modulation circuit electrically connected to the frequency control circuit via the signal generation circuit.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: September 9, 2014
    Assignee: Kaijo Corporation
    Inventors: Hiroshi Hasegawa, Hiroki Okuzawa
  • Patent number: 8810320
    Abstract: In a circuit having a runaway detector coupled to a phase-locked loop (PLL), the PLL may include a loop filter to receive a control voltage within the PLL and provide a filtered control voltage and a voltage-controlled oscillator to receive the filtered control voltage and provide an output clock signal. The runaway detector may provide a control signal for adjusting the filtered control voltage in response to a predetermined PLL condition. The runaway detector may include a comparator to receive a first and second input voltages, where the second input voltage is based on the output clock signal. When the predetermined PLL condition exists, the runaway detector may be active to adjust the filtered control voltage, thereby enabling the PLL to return to a lock condition.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: August 19, 2014
    Assignee: Marvell Israel (M.I.S.L)
    Inventor: Mel Bazes
  • Patent number: 8742864
    Abstract: In a particular embodiment, a method includes adjusting an input to a divider on a feedback path of a phase locked loop circuit based on a stored digital value representing a portion of a time-based waveform that is applied to a modulator circuit. The stored digital value is retrieved based on an output of the feedback path.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: June 3, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Zhi Zhu, Xiaohua Kong, Nam V. Dang
  • Patent number: 8531244
    Abstract: A high frequency signal processing device is capable of carrying out high-accuracy modulation by a PLL circuit. A digital loop is configured in addition to an analog loop having, for example, a phase frequency detector, a charge pump circuit, and a loop filter. A digital calibration circuit is provided which searches for the optimal code set to a capacitor bank upon frequency modulation. Upon the search for the optimal code, a calibration controller first sets a division ratio based on a center frequency to a divider and determines the value of a voltage control signal using the analog loop. Then, the loop filter holds the value of the voltage control signal therein, and a division ratio corresponding to a “center frequency+modulated portion” is set to the divider, thereby operating the digital loop. The optimal code is obtained by a convergent value of the digital loop.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: September 10, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Shibata, Toshiya Uozumi
  • Patent number: 8368480
    Abstract: Phase locked loop circuits are provided, in which a phase locked loop module includes a voltage controlled oscillator to generate an oscillation signal with an output frequency according to a control voltage, and a gain calibration module triggers the phase locked loop module to induce a frequency variation characterized by a delta function in the output frequency and calculates a gain of the voltage controlled oscillator according to a phase error caused by the frequency variation in the output frequency.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: February 5, 2013
    Assignee: Mediatek Inc.
    Inventor: Ping-Ying Wang
  • Patent number: 8306067
    Abstract: The invention discloses a dual frequency multiplexer by which a first and second coaxial harmonic oscillator type band pass filters are disposed in a box. The box includes a base body, a cover plate and a cover body. The two coaxial harmonic oscillator type hand pass filters are located on the base body and spaced each other by a metal plate; the multiplexer port, first and second ports are positioned on lateral side of the base body. The blocking capacitors are contained in the coaxial chamber of the two coaxial harmonic oscillator type band pass filters. The cover plate is secured on the base body; the first and second direct current circuits are placed on the cover plate; the low pass filters of the first and second direct current circuits are fixed on an edge of a top surface of the coaxial chamber by means of a support member; the cover body and the base body are fastened with each other. The blocking capacitors each are of distributed parameter capacitor.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: November 6, 2012
    Assignee: Comba Telecom System (China) Ltd.
    Inventors: Yingjie Di, Tao He, Bin He, Mengmeng Shu, Jingmin Huang
  • Patent number: 8248167
    Abstract: The present invention discloses a continuous voltage controlled oscillator (VCO) frequency temperature compensation apparatus for a phase locked loop (PLL) and a continuous VCO frequency temperature compensation method for a PLL. The system utilizes a VCO with one digital coarse tuning input, a first analog fine tuning input, and a second analog fine tuning input. The system uses the second analog fine tuning inputs to compensate the VCO for frequency shifts due to temperature fluctuation. When the PLL transitions to the fine lock (FL) mode, the system starts driving the second fine tuning input with a differential amplifier. The differential amplifier compares the first fine tuning input with a reference voltage, and drives the second fine tuning input to compensate the first fine tuning input.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: August 21, 2012
    Assignees: MStar Semiconductor, Inc., MStar France SAS, MStar Software R&D (Shenzhen) Ltd., MStar Semiconductor, Inc. (Cayman Islands)
    Inventor: Eric K. Bolton
  • Patent number: 8174326
    Abstract: In one embodiment, a cross zero best error selection system includes an error input interface, a most significant bit summation component and a multiplexer. The error input interface in coupled to a most significant bit summation component which in turn is coupled to a multiplexer. The error input interface receives a plurality of future error values. The most significant bit summation component sums most significant bits of said future error values. The multiplexer for selects error value based upon said summation of said most significant bits.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: May 8, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventor: Shuliang Li
  • Patent number: 8107582
    Abstract: A method and apparatus for clock recovery in synchronous digital systems. The apparatus includes a phase frequency detector, a loop filter, a compressor, and a clock generator. The phase frequency detector generates a phase error signal based on a difference between an input clock signal and an output clock signal. The loop filter multiplies the phase error signal and filters the multiplied phase error signal. The compressor divides the loop filter output. Based on the compressor output, the clock generator generates an output clock signal is provided as a feedback signal to the phase error detector. The apparatus may also include a glitch cleaner for deglitching the input clock signal.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: January 31, 2012
    Assignee: Beken Corporation
    Inventor: Weifeng Wang
  • Patent number: 8085097
    Abstract: An integrated ramp, sweep fractional frequency synthesizer system on an integrated circuit chip includes an integrated circuit chip having a fractional frequency synthesizer with a fractional divider responsive to a VCO and a ?? modulator for modifying the divisor of the fractional divider; and a ramp generator on the same integrated circuit chip; the ramp generator being responsive to a trigger signal to generate a ramp for sweeping the frequency of said fractional frequency synthesizer.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: December 27, 2011
    Assignee: Hittite Microwave Corporation
    Inventors: Mark M. Cloutier, Tudor Lipan
  • Patent number: 8063669
    Abstract: Described is an apparatus that includes a frequency source and a plurality of time domain direct digital synthesizers each having an input connected to an output of the frequency source and an output providing an output frequency signal. A particular time domain direct digital synthesizer includes a sigma-delta modulator that functions as a second order multi-stage noise shaping sigma-delta modulator. In one exemplary embodiment sigma-delta modulator outputs provide a unitary-weighted word used to switch certain unit capacitors that comprise part of a delay modulator to produce a time-varying delay having a time-averaged value that directly corresponds to a binary value appearing on a plurality of phase accumulator outputs.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: November 22, 2011
    Assignee: Nokia Corporation
    Inventors: Saska Lindfors, Kari Stadius, Liangge Xu, Tapio Rapinoja, Jussi Ryynanen, Risto H. S. Kaunisto, Aarno Parssinen
  • Patent number: 8054137
    Abstract: The invention relates to a method and apparatus for integrating the various circuit components controlling a voltage-controlled oscillator (“VCO”) on an integrated circuit formed on a semiconductor device. In one embodiment, the integrated circuit includes a first digital-to-analog converter (“DAC”) for receiving and converting a digital representation of the frequency modulation for the VCO to an analog form. A filter removes any conversion error from the first analog signal. A second DAC receives and converts a digital representation of the center frequency for the VCO to a second analog signal. The first and second analog signals are combined at an adder and the resulting signal is used by a bridge circuit which controls the VCO.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: November 8, 2011
    Assignee: Panasonic Corporation
    Inventor: Saleh Osman
  • Patent number: 8044725
    Abstract: A signal generator including a DDS-signal source that is configured to operate according to the principle of direct digital synthesis (DDS), and a PLL signal synthesizer that is configured to operate according to the principle of phase locked loop (PLL) using an output signal from the DDS-signal source as a reference signal. The DDS-signal source can be connected via a direct connection, without further frequency division or mixing, directly to an output of the signal generator or directly to a level-adjustment device of the signal generator in order to generate a portion of an overall frequency range of an output signal of the signal generator.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: October 25, 2011
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Bernhard Richt, Joachim Danz, Guenther Klage
  • Publication number: 20110234137
    Abstract: A mode determination circuit is configured to determine whether there is a status change of the electric system associated with a frequency variation of a system control clock, and a clock change circuit is configured to change the system control clock from a system clock to a monitoring clock based on a determination result obtained by the mode determination circuit.
    Type: Application
    Filed: June 3, 2011
    Publication date: September 29, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Katsuyuki IMAMURA, Kosei Fujisaka
  • Patent number: 8022782
    Abstract: A two-point phase modulator and a method of calibrating conversion gain of the same are provided. The two-point phase modulator locks an output frequency signal by charging and pumping charge in a phase-locked loop (PLL) circuit at the beginning of operation, opens a loop of the PLL circuit for a period of time, and applies a step signal, thus calibrating conversion gain of a modulation signal that controls the output frequency signal. Thus, the conversion gain may be accurately calibrated by the calibration operation at one time.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: September 20, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyung-Ki Ahn
  • Patent number: 7948274
    Abstract: A method includes generating a plurality of reference phases of a reference signal and selecting a sub-phase from each of the plurality of reference phases to form a set of selected sub-phases. In the method selecting operates in response to synchronized outputs of a multi-phase phase accumulator that operates synchronously in accordance with one of the sub-phases of the set of sub-phases, and where the outputs of the multi-phase phase accumulator may be synchronized using at least one additional sub-phase.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: May 24, 2011
    Assignee: Nokia Corporation
    Inventors: Tapio Rapinoja, Liangge Xu
  • Patent number: 7893773
    Abstract: A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: February 22, 2011
    Assignee: Broadcom Corporation
    Inventors: Henrik T. Jensen, Hea Joung Kim
  • Patent number: 7777576
    Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A programmable filter is connected to receive the phase error samples and connected to provide a filtered output having a gain and a phase margin to the controllable oscillator. The programmable filter includes a proportional loop gain control having a programmable loop gain coefficient (alpha—?) and an integral loop gain control having a programmable loop gain coefficient (rho—?). Alpha and rho are configured to be programmatically changed simultaneously and are selected such that the gain is changed and the phase margin remains substantially unchanged.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: August 17, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Khurram Waheed, John Wallberg, Robert Bogdan Staszewski, Sudheer Vemulapalli
  • Patent number: 7755439
    Abstract: A PLL circuit for two point modulation includes a first loop filter, a second loop filter, a plurality of switching devices, and a calibration module. The first loop filter filters an output voltage of a charge pump during a gain calibration operation. The second loop filter filters the output voltage of the charge pump during a normal operation. The first loop filter has a bandwidth wider than that of the second loop filter to perform a fast calibration by reducing a lock time. The operation of the first loop filter, the operation of the second loop filter, and the opening of the first loop filter are determined by the switching operations of the switching devices. The calibration module adjusts a gain of analog modulation data based on a frequency error accumulated in the first loop filter after the first loop filter is open during the gain calibration operation.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: July 13, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hwa Yeal Yu, Dong Jin Keum
  • Patent number: 7741928
    Abstract: Circuits and methods for frequency modulation (FM) using a digital frequency-locked loop (DFLL). A digitally controlled oscillator (DCO) generates and adjusts a frequency of a modulated signal based on a digital tuning word. A DFLL control logic circuit receives a feedback of the modulated signal and generates a carrier signal word. A sigma delta modulator circuit receives an input signal and applies dithering to produce a dithered input signal word. An adder circuit receives and sums the dithered input signal word and the carrier signal word to produce the digital tuning word. The DFLL control logic circuit adjusts the carrier signal word to lock a carrier frequency of the modulated signal.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: June 22, 2010
    Assignee: Marvell International Ltd.
    Inventors: David Cousinard, Philippe Mosch, Lydi Smaini, Randy Tsang, Cao-Thong Tu, Miljan Vuletic
  • Patent number: 7737800
    Abstract: Provided is a frequency modulation circuit 1 for outputting a highly precise frequency-modulated signal regardless of variation in a characteristic of a VCO 15. A correction value calculation section 17 calculates a correction value Vt2 based on a voltage value (Vtx?Vt1) resulting from subtracting a control voltage Vt1, which is generated by a control voltage generation section 11, from a control voltage Vtx at which a sensitivity of the VCO 15 is maximized. A variable amplifier 18 amplifies the correction value Vt2. An addition section 13 outputs a control voltage Vt3, which results from adding the amplified correction value Vt2 to the control voltage Vt1, to the VCO 15 via a DAC 14.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: June 15, 2010
    Assignee: Panasonic Corporation
    Inventors: Akira Kato, Kaoru Ishida
  • Patent number: 7728690
    Abstract: Techniques to compensate for nonlinearity of a tuning function of an oscillator are described. The tuning nonlinearity of the oscillator may be modeled as a disturbance input to the oscillator and may be compensated with an equal but opposite disturbance. In one design, a nonlinearity correction signal to compensate for the tuning nonlinearity may be generated, e.g., based on a phase error signal in a phase-locked loop (PLL) and a scaling factor determined adaptively. The nonlinearity correction signal may compensate for the n-th (e.g., second) order tuning nonlinearity, and an n-th order (e.g., squared) modulating signal may be used to derive the scaling factor and the nonlinearity correction signal. A control signal for the oscillator may be generated based on the nonlinearity correction signal and possibly one or more other signals. The control signal may be applied to the oscillator to adjust the oscillation frequency of the oscillator.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: June 1, 2010
    Assignee: QUALCOMM, Incorporated
    Inventor: Gary John Ballantyne
  • Patent number: 7701297
    Abstract: A frequency synthesizer is described illustrating a method for modulation having improved frequency shape for spread spectrum modulation. In particular, the a standard curve is generated, wherein the standard curve modulates an input signal to generate a spread spectrum of frequencies with reduced amplitude and spreading of bandwidth. The standard curve is sampled at a sampling frequency. The length of the standard curve is adjusted such that critical points of the standard curve are captured.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: April 20, 2010
    Assignee: Cypress Semiconductor Corporation
    Inventor: Shuliang Li
  • Patent number: 7692498
    Abstract: A phase locked loop has a controlled oscillator for outputting an oscillator signal depending on a control signal. A comparator generates a comparison result from a comparison between a reference frequency signal and a feedback signal derived from the oscillator signal. The phase locked loop also has a filter block for filtering the comparison result and for deriving the control signal from the comparison result, where the filter block has a loop filter and a rejection filter for the frequency-selective attenuation of at least one first interference frequency in the comparison result.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: April 6, 2010
    Assignee: Infineon Technologies AG
    Inventors: Thomas Mayer, Christian Wicpalek, Thomas Bauernfeind, Linus Maurer
  • Patent number: 7683723
    Abstract: A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-2) of the phase detector is first changed, and the response corresponding to the change is detected by the output of the voltage locked oscillator. The detection is performed by connecting the output of the voltage locked oscillator with the counter and connecting the output of the counter with the integrator. The phase locked loop characteristics are optimized by performing feedback for the detection result on the value of the charge pump current.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: March 23, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yukinori Akamine, Manabu Kawabe, Satoshi Tanaka, Yasuo Shima, Ryoichi Takano
  • Patent number: 7679468
    Abstract: An apparatus for providing a two point phase/frequency modulation system is disclosed herein. The apparatus includes a first network configured to introduce an offset to center a signal applied to a VCO. The apparatus further includes a second network configured to set a gain of the VCO. A phase tracking network is configured to dynamically adjust the offset and the gain.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: March 16, 2010
    Assignee: QUINTIC Holdings
    Inventors: John B. Groe, Kenneth Scott Walley
  • Patent number: 7589586
    Abstract: A high frequency signal detection circuit includes an input terminal for a high frequency signal to be detected, a switch transferring the high frequency signal as intermittent ringing signal to a first node in response to a pulse signal whose frequency is lower than that of the high frequency signal, a transistor amplifying the signal at the first node, and outputting to a second node, a bias generator generating a bias voltage by which the transistor is operated in its weak inversion region, a resonant circuit outputting the bias voltage to the first node, and resonating the high frequency signal, a capacitor removing a high frequency component of the signal at the second node; and a judgment circuit judging whether or not the high frequency signal is inputted by detecting the signal at the second node, which has the same frequency as the pulse signal.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: September 15, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Hiroyuki Toda
  • Patent number: 7579919
    Abstract: Architectures for compensating the frequency drift of an oscillator based frequency synthesizer circuit due to the change of temperature are disclosed. By applying a digitally controlled frequency word which represents the frequency difference between an output signal of a crystal oscillator and a temperature-compensated signal obtained from the output of a frequency synthesizer, the generated frequency signal is controlled so as to be temperature compensated over a wide temperature range. In one embodiment, a frequency locked loop is provided to perform functions to compensate for possible drifts in the reference signal. The frequency locked loop receives a digital frequency corrected control word based on at least a first parameter and a second parameter, wherein the first parameter is a combination of a fixed frequency control word and an automatic frequency correction word, and the second parameter is derived from an external source.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: August 25, 2009
    Inventor: Weixun Cao
  • Patent number: 7573348
    Abstract: An arrangement for determining a gradient factor for a digitally controlled oscillator has a data alignment device and an identification device. The data alignment device can be supplied a modulation signal, a phase error signal and an oscillator control word. The data alignment device is configured to output a modulation setting word based on the modulation signal, output a time interval magnitude based on the phase error signal and a reference interval, and output an oscillator modulation word based on the oscillator control word. The identification device is configured to adapt and output the gradient factor based on the modulation setting word, the time interval magnitude and the oscillator modulation word.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: August 11, 2009
    Assignee: Infineon Technologies AG
    Inventors: Thomas Bauernfeind, Linus Maurer
  • Patent number: 7567629
    Abstract: The invention represents a parallel and distributed approach to clock recovery based on multiple mutually phase shifted sample clock signals (åS) defining a set of orthogonal clock phases. The phase shifted clock signals are used for obtaining an input data sample representation (åU). Input data transition detection is accomplished by determining, for each one of the above clock phases, whether input data samples within a detection window associated with the respective clock phase include an input data transition vector (I). A corresponding clock selection control signal vector (I) is generated based on the input data transition vector (I) to determine a clock selection master. In order to dynamically extract an output clock signal, to control signal vector (I) is then logically combined with a representation (åS?), preferably a rotated version, of the sample clock vector (åS).
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: July 28, 2009
    Inventor: Jesper Jonas Fredriksson
  • Patent number: 7538706
    Abstract: A MASH modulator. The MASH modulator receives a fractional input value, generates an integer output value, and comprises three cascaded first order sigma delta modulators (SDMs) each comprising an accumulator, a plurality of first multipliers, a second multiplier, a first adder, and a second adder. Each of the first multipliers is coupled to a corresponding accumulator. The first adder receives the fractional input value. The second multiplier is coupled between the first adder and the cascaded first order sigma delta modulators. The second adder is coupled to the cascaded first order sigma delta modulators to generate the integer output value.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: May 26, 2009
    Assignee: Mediatek Inc.
    Inventor: Hsiang-Hui Chang
  • Patent number: 7538623
    Abstract: A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: May 26, 2009
    Assignee: Broadcom Corporation
    Inventors: Henrik T. Jensen, Hea Joung Kim
  • Patent number: 7522011
    Abstract: A radio frequency modulator based on direct frequency/phase modulation of output signal of a controllable oscillator (724) that is a part of a phase locked loop (PLL) provides a direct modulator that is able to operate over a wide frequency range with a flat frequency response. A modulation signal is digitally processed (721, 730) before injection to a high-pass path of a direct modulator. Applicability of digital signal processing is based on the fact that the modulation signal is a base band signal. Therefore, the modulation signal (702) occupies such a band in the frequency domain so that a sufficient ratio of a sampling rate to an upper edge frequency of the modulation signal can be achieved. Digital processing is used for compensating an effect of non-flat high-pass PLL transfer function and/or to perform pre-distortion of the input signal of a controlled oscillator to compensate an effect of non-linearity of a controlled oscillator.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: April 21, 2009
    Assignee: Nokia Corporation
    Inventors: Jorma Matero, Niall Eric Shakeshaft
  • Patent number: 7499688
    Abstract: In a communication semiconductor integrated circuit device using offset PLL architectures and including an oscillator circuit and a frequency divider circuit generating an intermediate frequency signal, the oscillator circuit includes an oscillator, a programmable frequency divider which frequency-divides the oscillation signal in accordance with frequency division information, a phase comparator detecting a phase difference between an output signal of the programmable frequency divider and a reference signal, and a frequency control unit for outputting a signal indicative of the phase difference and controlling the oscillation frequency of the oscillator, wherein a frequency division ratio generator circuit generates an integer part I and a fraction part F/G based on band information concerning the use frequency band and mode information along with channel information and for producing the frequency division ratio information to thereby give it to the programmable frequency divider.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: March 3, 2009
    Assignees: Renesas Technology Corp., TTPOM Limited
    Inventors: Toshiya Uozumi, Yasuyuki Kimura, Hirotaka Osawa, Satoru Yamamoto, Robert Astel Henshaw
  • Patent number: 7499689
    Abstract: In a communication semiconductor integrated circuit device using offset PLL architectures and including an oscillator circuit and a frequency divider circuit generating an intermediate frequency signal, the oscillator circuit includes an oscillator, a programmable frequency divider which frequency-divides the oscillation signal in accordance with frequency division information, a phase comparator detecting a phase difference between an output signal of the programmable frequency divider and a reference signal, and a frequency control unit for outputting a signal indicative of the phase difference and controlling the oscillation frequency of the oscillator, wherein a frequency division ratio generator circuit generates an integer part I and a fraction part F/G based on band information concerning the use frequency band and mode information along with channel information and for producing the frequency division ratio information to thereby give it to the programmable frequency divider.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: March 3, 2009
    Assignees: Renesas Technology Corp., TTPCOM Limited
    Inventors: Toshiya Uozumi, Yasuyuki Kimura, Hirotaka Osawa, Satoru Yamamoto, Robert Astel Henshaw
  • Patent number: 7482883
    Abstract: A novel mechanism for gain normalization of a digitally controlled oscillator (DCO) in an all digital phase locked loop (ADPLL)-based transmitter that is operative to split the gain normalization multiplication functionality between a modulating path and a PLL loop. The gain normalization of the modulation loop (referred to as modulation path multiplier) comprises a full bit resolution high precision multiplication function. The gain normalization of the PLL loop, on the other hand, is of significantly lower resolution, hence much lower complexity multiplier logic circuitry is required.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: January 27, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Robert B. Staszewski, John Wallberg
  • Patent number: 7443261
    Abstract: A multimode-based phase modulating apparatus capable of reducing the degradation of modulation precision and suppressing the unnecessary power consumption. This apparatus has a switch for switching the modulation modes of a PLL circuit between a single-point modulation and a double-point modulation. In a case of a narrow modulation bandwidth, the switch is turned off to cease a second digital baseband signal, thereby causing the PLL circuit to perform the single-point modulation in which only a first digital baseband signal from a frequency division rate generating part is used for the modulation. Contrarily, in a case of a wide modulation bandwidth, the switch is turned on, thereby performing the double-point modulation using both the first digital baseband signal and the second digital baseband signal.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: October 28, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Yoshikawa, Shunsuke Hirano
  • Patent number: 7436263
    Abstract: An apparatus that presents an output signal that is modulated by input signal includes: (a) A signal source providing a signal at a reference frequency. (b) A frequency comparer coupled with the signal source and the output signal for comparing the extant output signal frequency with the reference frequency and generating an indicator representing the comparing. (c) Value storing units coupled with the frequency comparer to respond to an indicator and store a parameter associated with one of predetermined frequencies. (d) A selector coupled with the value storing units. (e) A signal controlled oscillator coupled with the selector. The selector responds to the input signal to couple a value storing unit with the oscillator for providing a parameter to the oscillator for effecting the modulation.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: October 14, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Khanh Chu Nguyen
  • Patent number: 7420433
    Abstract: A phase lock loop RF modulator system including a phase lock loop circuit having a phase detector circuit responsive to an input reference signal and a feedback signal, an oscillator circuit responsive to the phase detector circuit for providing an output signal, a forward path from the phase detector circuit to the oscillator circuit, and a feedback path from the oscillator circuit to the phase detector circuit. The system also includes a first modulation port coupled to the feedback path, a second modulation port coupled to the forward path, and a gain mismatch detection circuit responsive to modulation data and a phase error between the reference signal and the feedback signal for providing an indicator output signal that represents the gain mismatch between the first modulation port and the second modulation port.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: September 2, 2008
    Assignee: Analog Devices, Inc.
    Inventors: Cormac E. O'Sullivan, Colin Lyden, Hyman N. Shanan
  • Patent number: 7417514
    Abstract: A direct division modulator is provided. The direct division modulator includes a symbol mapper converting the input data from a binary bitstream to a desired frequency deviation, such as where the frequency deviation data encodes the information from the bitstream. A converter generates a divide value using the desired frequency deviation information, and a summer adds an average value to the divide value. A converter quantizes the divide value and shapes quantization noise associated with the quantized divide value. A divider modulates a reference signal with the quantized divide value and generates an output signal.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: August 26, 2008
    Assignee: Axiom Microdevices, Inc.
    Inventors: Jeff Zachan, David Hartman, Ming Lin, Morten Damgaard, Scott Kee
  • Patent number: 7411469
    Abstract: A circuit arrangement having a plurality of variable capacitance elements such as varactors is described, the varactors having associated electronic control means which controls the capacitance of the variable capacitance elements over a control range. The control range is such that for any particular variable capacitance element a complete variation from a lowest to a highest capacitance is obtained from only a portion of the control range.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: August 12, 2008
    Assignee: Intel Corporation
    Inventors: Colin Leslie Perry, Stephen John Parry, Alessandro F. Deidda, Christopher R. Shepherd
  • Patent number: 7408418
    Abstract: A phase locked loop circuit comprising a phase detector having a first input for receiving a first frequency signal and an output, a first filter adapted to filter the output electric signal of the phase detector, a voltage controlled oscillator adapted to generate a second frequency signal in response to the output filtered signal of the phase detector. The phase detector has a second input for receiving the second frequency signal and is adapted to compare it with the first frequency signal. The circuit comprises means adapted to amplify the difference between an electric signal coupled with the output of the phase detector and a reference electric signal and a second filter adapted to receive the output electric signal of the amplification means and to send an output electric signal to the voltage controlled oscillator. The circuit comprises further means adapted to modify the value of the electric signal in input to the second filter to decrease the response time of the second filter.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: August 5, 2008
    Assignee: STMicroelectronics SA
    Inventor: Philippe Sirito-Olivier
  • Patent number: RE44879
    Abstract: A phase locked loop has a controlled oscillator for outputting an oscillator signal depending on a control signal. A comparator generates a comparison result from a comparison between a reference frequency signal and a feedback signal derived from the oscillator signal. The phase locked loop also has a filter block for filtering the comparison result and for deriving the control signal from the comparison result, where the filter block has a loop filter and a rejection filter for the frequency-selective attenuation of at least one first interference frequency in the comparison result.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: May 6, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Thomas Mayer, Christian Wicpalek, Thomas Bauernfeind, Linus Maurer